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Synergizing spintronics and quaternary logic: a hardware accelerator for neural networks with optimized quantization algorithm

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Abstract

Multi-valued logic (MVL) is a promising solution for high-power consumption and area caused by the limitation of binary systems. Quaternary logic is one of the MVL types more compatible with binary logic. While traditional CMOS technology struggles with achieving multiple threshold voltage levels efficiently, leading to greater complexity and energy inefficiency, CNTFETs offer tunable thresholds ideal for MVL applications. Neural networks can retrieve data from inaccurate data, detect trends, and extract patterns that traditional computing methods or humans find difficult to extract. In artificial neural networks (ANNs), the demand for substantial memory to store numerous weights is a critical consideration. Leveraging emerging technologies like magnetic tunnel junctions (MTJ) for non-volatility and CNTFETs for diverse threshold voltage values presents a groundbreaking stride. This convergence of technologies assures non-volatile storage and facilitates the intricate hardware implementation of MVL systems, marking a pioneering leap forward in crafting the next generation of memory for ANN applications. This paper proposes an algorithm for quantizing neural networks using quaternary logic. According to the proposed algorithm, the circuits required to implement quaternary neural networks are designed. The simulation results demonstrate that the proposed algorithm for quantized neural networks significantly reduces the overall memory requirements compared to their full precision counterparts, with minimal accuracy degradation. Specifically, the accuracy drop is less than 1.67% on CIFAR-10 and 1.22% on CIFAR-100 for ResNet-18, while improvements for MNIST on MLP, CIFAR-10 on LeNet-5, and CIFAR-10 and CIFAR-100 on VGG-16, are even observed.

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The datasets generated during and/or analyzed during the current study are available from the corresponding author upon reasonable request.

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Authors and Affiliations

  1. Faculty of Electrical Engineering, Shahid Beheshti University, Tehran, Iran

    Motahareh BahmanAbadi & Mohammad Hossein Moaiyeri

  2. Department of Electrical and Computer Engineering, The George Washington University, Washington, DC, USA

    Abdolah Amirany

  3. Interdisciplinary Institute for Technological Innovation (3IT), Université de Sherbrooke, Sherbrooke, QC, Canada

    Kian Jafari

  4. Faculty of Engineering, Université de Sherbrooke, 2500 Boul. de l’Université, Sherbrooke, QC, Canada

    Kian Jafari

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Contributions

Motahareh BahmanAbadi was contributed conceptualization, methodology, investigation, software, and writing—original draft. Abdolah Amirany was involved in methodology, investigation, software, and writing—original draft. Mohammad Hossein Moaiyeri was performed methodology, validation, software, writing—reviewing and editing, and supervision. Kian Jafari was done methodology, validation, software, and reviewing and editing.

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Correspondence to Mohammad Hossein Moaiyeri.

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BahmanAbadi, M., Amirany, A., Moaiyeri, M.H. et al. Synergizing spintronics and quaternary logic: a hardware accelerator for neural networks with optimized quantization algorithm. J Supercomput 81, 669 (2025). https://doi.org/10.1007/s11227-025-07176-z

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