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computer-architecture
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Some RISC-V instructions perform writes to 2 destinations, either 2 register or register or program counter. In cases if the source of one sub-operation matches a destination of another one, the order of result output is important. The examples are jalr
and instruction operating with CSRs:
riscv/riscv-tests#258
riscv/riscv-tests#263
Your obj
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For instance, if a user tries to write
jalr x0 0(x1)
the tooltip should also state thatjalr
has the formatjalr [rd] [rs] [imm]
.