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vlsi-circuits

Here are 14 public repositories matching this topic...

OpenTimer / OpenTimer

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A High-performance Timing Analysis Tool for VLSI Systems

parallel-computing eda circuit-simulator cad verilog cpp17 circuit-simulation vlsi circuit-analysis computer-aided-design vlsi-physical-design sta electronic-design-automation vlsi-circuits static-timing-analysis

Updated Apr 18, 2020
C++

luckyrantanplan / nthu-route

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VLSI EDA Global Router

router eda vlsi vlsi-physical-design electronic-design-automation vlsi-circuits globalrouter ispd lattice-graph multi-maze-routing

Updated Jan 22, 2018
C++

purdue-onchip / gds2Para

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GDSII File Parsing, IC Layout Analysis, and Parameter Extraction

parse eda vlsi integrated-circuits interconnect gdsii spef electronic-design-automation vlsi-circuits

Updated Jun 15, 2020
C++

OpenTimer / Parser-SPEF

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A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).

eda circuits cpp17 vlsi computer-aided-design vlsi-physical-design sta spef electronic-design-automation vlsi-circuits parasitic static-timing-analysis

Updated Jan 2, 2019
C++

mida

srohit0 / mida

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Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"

machine-learning deep-neural-networks deep-learning neural-network machine-learning-algorithms artificial-intelligence artificial-neural-networks logistic-regression feedforward-neural-network polynomial-regression vlsi machine-intelligence design-automation electronic-design-automation vlsi-circuits vlsi-design vlsi-machine-learning vlsi-deep-learning

Updated Dec 9, 2018
Jupyter Notebook

OpenTimer / Parser-Verilog

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A Standalone Structural Verilog Parser

flex eda verilog cpp17 circuit computer-aided-design vlsi-physical-design electronic-design-automation vlsi-circuits bison-yacc

Updated Jun 11, 2019
Verilog

ehw-fit / evoapproxlib

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Library of approximate arithmetic circuits

fpga arithmetic approximate-computing vlsi-circuits

Updated Jul 1, 2020
Verilog

levibyte / pyqt_genetic_algo

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genetic algorithm usage for routing optimization ( pyqt )

qt mvc optimization genetic-algorithm routing eda routing-engine pyqt vlsi placement placement-engine placements vlsi-circuits

Updated Mar 24, 2019
Python

paripath / cdf

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Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

characterization power-analysis hspice spice-simulator vlsi-circuits timing-analysis vlsi-design vlsi-cad

Updated Feb 13, 2020
C++

SalomeDevkule7 / Carry-Select-Adder-8-bit

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VLSI Physical Design

cadence-virtuoso vlsi-physical-design vlsi-circuits

Updated Jun 14, 2018

Gregory-Matthews / Dependable-Computing

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Graduate Level - Fundamental design issues involved in building reliable, safety-critical, and highly available systems. Topics include testing and fault-tolerant design of VLSI circuits, hardware and software fault tolerance, information redundancy, and fault-tolerant distributed systems.

markov-model fault-tolerance safety-critical tmr triple-modular-redundancy vlsi-circuits information-redundancy

Updated Dec 1, 2017
MATLAB

NarekAt / GreedyGenes

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A generic object oriented library for solving optimizations problems with heuristic approaches + second-phase Genetic algorithm optimizations

graph-algorithms genetic-algorithm heuristics greedy-algorithms vlsi-circuits

Updated Apr 29, 2018
C++

mihir8181 / VLSI-Design-Digital-System

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This is this VLSI designing Project. This Project is created in Cadence Virtuoso. See the PDF for Pre-Post layout results and other details

digital simulation logic-gates alu vlsi multiplexer cadence-virtuoso andgate orgate 1bitfulladder logicgates vlsi-circuits vlsi-design vlsi-designing vlsi-project 4bitadder 8isto1mux 4bitdivider 4bitmultiplier dflipflop

Updated Mar 22, 2019

RithikNambiar / vim_dotfiles

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Contains vim dotfiles configured for verilog, C++

Updated Jun 3, 2020
Vim script

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