SN54HCT04, SN74HCT04

SCLS042F – JULY 1986 – REVISED OCTOBER 2022

SNx4HCT04 Hex Inverters

1 Features 2 Description
• Operating voltage range of 4.5V to 5.5V These devices contain six independent inverters.
• Outputs can drive up to 10 LSTTL loads They perform the Boolean function Y = A in positive
• Low power consumption, 20-μA max ICC logic.
• Typical tpd = 13ns (1)
Device Information
• ±4-mA output drive at 5V
PART NUMBER PACKAGE BODY SIZE (NOM)
• Low input current of 1μA max
• Inputs are TTL-Voltage compatible SN74HCT04PW TSSOP (14) 5.00 mm × 4.40 mm
SN74HCT04D SOIC (14) 8.65 mm × 3.90 mm
SN74HCT04N PDIP (14) 19.31 mm × 6.35 mm
SN74HCT04NSR SO (14) 10.20 mm × 5.30 mm
SNJ54HCT04FK LCCC (20) 8.89 mm × 8.89 mm
SNJ54HCT04J CDIP (14) 19.55 mm × 6.71 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

xA xY

Functional Block Diagram

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54HCT04, SN74HCT04
SCLS042F – JULY 1986 – REVISED OCTOBER 2022 www.ti.com

Table of Contents
1 Features............................................................................1 7.2 Functional Block Diagram........................................... 7
2 Description.......................................................................1 7.3 Device Functional Modes............................................7
3 Revision History.............................................................. 2 8 Power Supply Recommendations..................................8
4 Pin Configuration and Functions...................................3 9 Layout...............................................................................8
5 Specifications.................................................................. 4 9.1 Layout Guidelines....................................................... 8
5.1 Absolute Maximum Ratings........................................ 4 10 Device and Documentation Support............................9
(1)
5.2 Recommended Operating Conditions ..................... 4 10.1 Documentation Support............................................ 9
5.3 Thermal Information....................................................4 10.2 Receiving Notification of Documentation Updates....9
5.4 Electrical Characteristics.............................................5 10.3 Support Resources................................................... 9
5.5 Switching Characteristics ...........................................5 10.4 Trademarks............................................................... 9
5.6 Operating Characteristics........................................... 5 10.5 Electrostatic Discharge Caution................................9
6 Parameter Measurement Information............................ 6 10.6 Glossary....................................................................9
7 Detailed Description........................................................7 11 Mechanical, Packaging, and Orderable
7.1 Overview..................................................................... 7 Information...................................................................... 9

3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (February 2022) to Revision F (October 2022) Page
• Increased RθJA for packages: D (86 to 138.7); N (80 to 62.7); NS (76 to 90.9); PW (113 to 117.6)..................4

Changes from Revision D (July 2003) to Revision E (February 2022) Page

• Updated the numbering, formatting, tables, figures, and cross-references throughout the document to reflect
modern data sheet standards.............................................................................................................................1

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SN54HCT04, SN74HCT04
www.ti.com SCLS042F – JULY 1986 – REVISED OCTOBER 2022

4 Pin Configuration and Functions

J, D, N, NS, or PW Package
14-Pin CDIP, SOIC, PDIP, SO, or TSSOP
Top View
FK Package
20-Pin LCCC
Top View

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SCLS042F – JULY 1986 – REVISED OCTOBER 2022 www.ti.com

5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage range -0.5 7 V
(2)
IIK Input clamp current (VI < 0 or VI > VCC) ±20 mA
(2)
IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA
IO Continuous output current (VO = 0 to VCC) ±25 mA
VCC or GND Continuous current through VCC or GND ±50 mA
TJ Junction temperature 150 °C
Tstg Storage temperature -65 150 °C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

(1)
5.2 Recommended Operating Conditions
SN54HCT04 SN74HCT04
UNIT
MIN NOM MAX MIN NOM MAX
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VI Input voltage 0 VCC 0 VCC V
VO Output voltage 0 VCC 0 VCC V
Δt/Δv Input transition rise/fall time 500 500 ns
TA Operating free-air temperature -55 125 -40 85 °C

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating SMOS Inputs, literature number SCBA004.

5.3 Thermal Information

D (SOIC) N (PDIP) NS (SO) PW (TSSOP)
THERMAL METRIC 14 PINS 14 PINS 14 PINS 14 PINS UNIT
RθJA Junction-to-ambient thermal
(1) 138.7 62.7 90.9 117.6 °C/W
resistance
RθJC(top) Junction-to-case (top) thermal
93.8 50.5 48.5 46.9 °C/W
resistance
RθJB Junction-to-board thermal resistance 94.7 42.5 51.5 60.6 °C/W
ψJT Junction-to-top characterization
49.1 30.1 15.9 5.6 °C/W
parameter
ψJB Junction-to-case (bottom) thermal
94.3 42.2 51 60 °C/W
resistance
RθJC(bot) Junction-to-case (bottom) thermal
N/A N/A N/A N/A °C/W
resistance

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

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www.ti.com SCLS042F – JULY 1986 – REVISED OCTOBER 2022

5.4 Electrical Characteristics

VCC TA = 25°C SN54HCT04 SN74HCT04
PARAMETER TEST CONDITIONS(1) UNIT
(V) MIN TYP MAX MIN MAX MIN MAX
IOH = – 20 μA 4.4 4.499 4.4 4.4
VOH High-level output voltage 4.5 V
IOH = – 4 mA 3.98 4.3 3.7 3.84
IOL = 20 μA 0.001 0.1 0.1 0.1
VOL Low-level output voltage 5.5 V
IOL = 4 mA 0.17 0.26 0.4 0.33
II Input hold current VI = VCC or 0 5.5 ±0.1 ±100 ±1000 ±1000 nA
ICC Supply current VI = VCC or 0. IO = 0 5.5 2 40 20 μA
One input at 0.5V or 2.4
ΔICC(2) Supply-current change V, Other inputs at 0 or 5.5 1.4 2.4 3 2.9 mA
VCC
4.5 to
Ci Input capacitance 3 10 10 10 pF
5.5

(1) VI = VIH or VIL, unless otherwise noted.

(2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.

5.5 Switching Characteristics

CL = 50 pF. See Parameter Measurement Information
TO VCC TA = 25°C SN54HCT04 SN74HCT04
PARAMETER FROM (INPUT)
(OUTPUT) (V) MIN TYP MAX MIN MAX MIN MAX
4.5 14 20 30 25
tpd Propagation delay A or B Y ns
5.5 13 18 27 23
4.5 9 15 22 19
tt Transition time Y ns
5.5 8 14 20 17

5.6 Operating Characteristics

TA = 25°C
Test Conditions TYP UNIT
Cpd Power dissipation capacitance No load 20 pF

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SCLS042F – JULY 1986 – REVISED OCTOBER 2022 www.ti.com

6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test
Point

From Output
Under Test
CL(1)

(1) CL includes probe and test-fixture capacitance.

Figure 6-1. Load Circuit for Push-Pull Outputs

3V
Input 1.3V 1.3V
0V
(1)
tPLH tPHL(1)
VOH
Output
50% 50%
Waveform 1
VOL
tPHL(1) tPLH(1)
VOH
Output
50% 50%
Waveform 2
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 6-2. Voltage Waveforms, Propagation Delays for TTL-Compatible Inputs

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www.ti.com SCLS042F – JULY 1986 – REVISED OCTOBER 2022

7 Detailed Description
7.1 Overview
These devices contain six independent inverters. They perform the Boolean function Y = A in positive logic.
7.2 Functional Block Diagram

xA xY

7.3 Device Functional Modes

Table 7-1. Function Table
(each inverter)
Input Output
A Y
H L
L H

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SCLS042F – JULY 1986 – REVISED OCTOBER 2022 www.ti.com

8 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results.
9 Layout
9.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.

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www.ti.com SCLS042F – JULY 1986 – REVISED OCTOBER 2022

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
10.1 Documentation Support
10.1.1 Related Documentation

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
10.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
10.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

10.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: SN54HCT04 SN74HCT04
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-89747012A ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89747012A
SNJ54HCT
04FK
5962-8974701CA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974701CA Samples
& Green SNJ54HCT04J
5962-8974701VCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974701VC Samples
& Green A
SNV54HCT04J
5962-8974701VDA ACTIVE CFP W 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974701VD Samples
& Green A
SNV54HCT04W
JM38510/65751BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65751BCA
M38510/65751BCA ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 JM38510/ Samples
& Green 65751BCA
SN54HCT04J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 SN54HCT04J Samples
& Green
SN74HCT04D OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HCT04
SN74HCT04DR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HCT04 Samples

SN74HCT04DRE4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT04 Samples

SN74HCT04DRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT04 Samples

SN74HCT04DT OBSOLETE SOIC D 14 TBD Call TI Call TI -40 to 85 HCT04

SN74HCT04N ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT04N Samples

SN74HCT04NE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -40 to 85 SN74HCT04N Samples

SN74HCT04NSR ACTIVE SO NS 14 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 HCT04 Samples

SN74HCT04PW OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HT04

SN74HCT04PWR ACTIVE TSSOP PW 14 2000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 85 HT04 Samples

SN74HCT04PWT OBSOLETE TSSOP PW 14 TBD Call TI Call TI -40 to 85 HT04

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

SNJ54HCT04FK ACTIVE LCCC FK 20 55 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89747012A
SNJ54HCT
04FK
SNJ54HCT04J ACTIVE CDIP J 14 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8974701CA Samples
& Green SNJ54HCT04J

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE OPTION ADDENDUM

www.ti.com 30-Jul-2024

OTHER QUALIFIED VERSIONS OF SN54HCT04, SN54HCT04-SP, SN74HCT04 :

• Catalog : SN74HCT04, SN54HCT04

• Enhanced Product : SN74HCT04-EP, SN74HCT04-EP
• Military : SN54HCT04
• Space : SN54HCT04-SP

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT04DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT04DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT04DRG4 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
SN74HCT04NSR SO NS 14 2000 330.0 16.4 8.45 10.55 2.5 12.0 16.2 Q1
SN74HCT04NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN74HCT04PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74HCT04PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT04DR SOIC D 14 2500 356.0 356.0 35.0
SN74HCT04DR SOIC D 14 2500 356.0 356.0 35.0
SN74HCT04DRG4 SOIC D 14 2500 356.0 356.0 35.0
SN74HCT04DRG4 SOIC D 14 2500 353.0 353.0 32.0
SN74HCT04NSR SO NS 14 2000 356.0 356.0 35.0
SN74HCT04NSR SO NS 14 2000 356.0 356.0 35.0
SN74HCT04PWR TSSOP PW 14 2000 356.0 356.0 35.0
SN74HCT04PWR TSSOP PW 14 2000 356.0 356.0 35.0

Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-89747012A FK LCCC 20 55 506.98 12.06 2030 NA
5962-8974701VDA W CFP 14 25 506.98 26.16 6220 NA
SN74HCT04N N PDIP 14 25 506 13.97 11230 4.32
SN74HCT04N N PDIP 14 25 506 13.97 11230 4.32
SN74HCT04NE4 N PDIP 14 25 506 13.97 11230 4.32
SN74HCT04NE4 N PDIP 14 25 506 13.97 11230 4.32
SNJ54HCT04FK FK LCCC 20 55 506.98 12.06 2030 NA

Pack Materials-Page 3
PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

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EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
GENERIC PACKAGE VIEW
FK 20 LCCC - 2.03 mm max height
8.89 x 8.89, 1.27 mm pitch LEADLESS CERAMIC CHIP CARRIER

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4229370\/A\

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PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

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EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

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PACKAGE OUTLINE
PW0014A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
12X 0.65
14
1

2X
5.1 3.9
4.9
NOTE 3

4X (0 -12 )
7
8
0.30
14X
0.17
4.5 1.2 MAX
B 0.1 C A B
4.3
NOTE 4

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220202/B 12/2023

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220202/B 12/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN
PW0014A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

14X (1.5) SYMM

(R0.05) TYP
1
14X (0.45) 14

SYMM

12X (0.65)

7 8

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220202/B 12/2023
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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