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xilinx-fpga
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acomodi
commented
Jan 17, 2020
Vendor tools dram tests were not enabled until #1234 got merged.
With SymbiFlow/symbiflow-arch-defs#1268 I have temporarily disabled the vivado_targets, to let CI go green (as it has been red for too long now).
This issue is to keep track of the problem with DRAM evaluated on vendor tools with fasm2bels.
Xilinx Virtual Cable Server for Raspberry Pi
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Aug 22, 2020 - C
Open-source CSI-2 receiver for Xilinx UltraScale parts
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Jul 10, 2019 - Verilog
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
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Jun 6, 2020 - C++
Minimal DVI / HDMI Framebuffer
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Aug 9, 2020 - Verilog
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
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Aug 25, 2020 - SystemVerilog
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
calculator
vhdl
matrix-multiplication
verilog
xilinx
hardware-designs
xilinx-fpga
low-level-programming
xilinx-ise
xilinx-vivado
ic-design
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Aug 12, 2017 - Verilog
PS/2 Keyboard IP written in VHDL for Xilinx FPGA
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Jul 11, 2015 - VHDL
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
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Jun 24, 2017 - Verilog
2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)
computer-vision
fpga
image-processing
verilog
optics
optical
2d
xilinx-fpga
frequency-analysis
dragster
cmosis
awaiba
optical-mark-recognition
xilinx-vivado
optical-system
frequency-measurment
dr-2k-7
optical-measurements
2d-scaner
optical-sensors
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Sep 15, 2017 - VHDL
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface
fpga
spi
altera
verilog-hdl
xilinx-fpga
xilinx-vivado
verilog-components
axi
verilog-snippets
spi-hdl
spi-ip-core
spi-pld
spi-fpga
verilog-spi
axi-interfaces
bit-oriented-spi
soft-spi
hard-spi
dragster-spi
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Nov 21, 2017 - Verilog
High-Level Synthesis with Partial Evaluation
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Jul 15, 2020 - CMake
A Xilinx IP Core and App for line scanner image capture and store
image
video
computer-vision
scanner
spi
capture-the-flag
xilinx-fpga
dragster
linescanners
cmosis
awaiba
two-channel-image-capture-system
axi-vdma
axi-quad-spi
video-ip-core
xilinx-vivado
dr-2k-7
xilinx-axi-vdma
xilinx-ip
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Sep 5, 2017 - VHDL
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
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Mar 24, 2017 - VHDL
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Jul 9, 2019 - VHDL
Lab Assigments, Projects for digital systems II Lecture (EEM334)
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Jun 1, 2020 - VHDL
This repository contains all labs done as a part of the Embedded Logic and Design course.
c
arm
vhdl
embedded-systems
verilog
xilinx
vivado
logic-programming
zedboard
verilog-hdl
xilinx-fpga
logic-circuit
xilinx-vivado
embedded-c
vhdl-code
pmod
xilinx-sdk
verilog-programs
verilog-project
embedded-logic
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Jun 10, 2018
Plugins for Yosys developed as part of the SymbiFlow project.
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Aug 28, 2020 - Verilog
A coocbook of HDL (primarily Verilog) modules
fpga
verilog
altera
fifo
hdl
verilog-hdl
xilinx-fpga
frequencies
frequency-analysis
verilog-components
verilog-library
verilog-snippets
clock-divider
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Apr 24, 2017 - Verilog
VHDL implementation of vintage TMS0800 calculator chip
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Updated
May 29, 2020 - VHDL
FPGA Tetris written in Verilog
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Updated
Apr 26, 2018 - Verilog
Our project material for the Computer Architecture course for Computer Engineering students at Politecnico di Torino (Polytechnic University of Turin)
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Jul 24, 2018 - VHDL
Xilinx Vivado demo project with design, IP, SDK interaction, VGA, finite state machine and outputs
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Updated
Aug 30, 2017 - VHDL
Experimental study and analysis on the effect of aggressive voltage underscaling on the reliability of COTS FPGAs: https://ieeexplore.ieee.org/abstract/document/8574581/
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Feb 22, 2019
Quick Verilog Module Isolator - Isolates a design for testing.
fpga
regex
cpp11
verilog
vivado
hdl
verilog-hdl
xilinx-fpga
quartus-prime
high-level-synthesis
dut
vivado-hls
isolator
isolated-modules
intel-quartus
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Dec 11, 2018 - Verilog
way to use xapp1052 with new version of PCIe IP core（AXI bus）
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Apr 5, 2018 - Verilog
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
vhdl
ultrasonic-sensor
xilinx-fpga
7segment
vhdl-modules
vhdl-code
nexys4ddr
parking-sensor
fpga-programming
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Dec 5, 2019 - VHDL
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557 bits isn't too many. Most of these are likely related to the DSP, as 1 DSP is being used: