SPARC

SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu.

Sun Microsystems, Inc. (Sun for short) was an American company that sold computers, computer components, software, and information technology services and created the Java programming language, the Solaris operating system, ZFS, the Network File System (NFS), and SPARC.

SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu.

Stanford's MIPS would go on to be commercialized as the successful MIPS architecture, while Berkeley's RISC gave its name to the entire concept and was commercialized as the SPARC.

Its design was strongly influenced by the experimental Berkeley RISC system developed in the early 1980s.

The Berkeley RISC design was later commercialized by Sun Microsystems as the SPARC architecture, and inspired the ARM architecture.

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors.

The original Sun-4 series were VMEbus-based systems similar to the earlier Sun-3 series, but employing microprocessors based on Sun's own SPARC V7 RISC architecture in place of the 68k family processors of previous Sun models.

SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995.

It is the first microprocessor from Sun to implement the 64-bit SPARC V9 instruction set architecture (ISA).

SPARC V8 added a number of improvements that were part of the SuperSPARC series of processors released in 1992.

The SuperSPARC is a microprocessor that implements the SPARC V8 instruction set architecture (ISA) developed by Sun Microsystems.

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors.

Prominent 32-bit instruction set architectures used in general-purpose computing include the IBM System/360 and IBM System/370 (which had 24-bit addressing) and the System/370-XA, ESA/370, and ESA/390 (which had 31-bit addressing), the DEC VAX, the NS320xx, the Motorola 68000 family (the first two models of which had 24-bit addressing), the Intel IA-32 32-bit version of the x86 architecture, and the 32-bit versions of the ARM, SPARC, MIPS, PowerPC and PA-RISC architectures.

Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne and Fujitsu, among others.

In the late 1980s and early 1990s, the company produced a range of computer workstations and servers based on the SPARC microprocessor architecture, largely compatible with Sun Microsystems' Sun-4 systems.

Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

In 2008, Itanium was the fourth-most deployed microprocessor architecture for enterprise-class systems, behind x86-64, Power ISA, and SPARC.

The SPARC processor usually contains as many as 160 general purpose registers.

In some architectures (such as SPARC and MIPS), the first or last register in the integer register file is a pseudo-register in a way that it is hardwired to always return zero when read (mostly to simplify indexing modes), and it cannot be overwritten.

SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu.

RISC architectures that have 32-bit instructions are usually 3-operand designs, such as the ARM, AVR32, MIPS, Power ISA, and SPARC architectures.

Another feature of SPARC influenced by this early RISC movement is the branch delay slot.

MIPS, PA-RISC, ETRAX CRIS, SuperH, and SPARC are RISC architectures that each have a single branch delay slot; PowerPC, ARM, Alpha, and RISC-V do not have any.

SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments.

Later, the company produced the B5000 SPARC ECL microprocessor (never reached production in a Sun Microsystems product, though used by Floating Point Systems) and the R6000 MIPS ECL microprocessor (which did reach production as a MIPS minicomputer).

In August 2012, Oracle Corporation made available a new specification, Oracle SPARC Architecture 2011, which besides the overall update of the reference, adds the VIS 3 instruction set extensions and hyperprivileged mode to the 2007 specification.

Logical Domains (LDoms or LDOM) is the server virtualization and partitioning technology for SPARC V9 processors.

The first implementation of the original 32-bit architecture (SPARC V7) was used in Sun's Sun-4 workstation and server systems, replacing their earlier Sun-3 systems based on the Motorola 68000 series of processors.

Visual Instruction Set, or VIS, is a SIMD instruction set extension for SPARC V9 microprocessors developed by Sun Microsystems.

In 2007, Sun released an updated specification, UltraSPARC Architecture 2007, to which the UltraSPARC T2 implementation complied.

It is a member of the SPARC family, and the successor to the UltraSPARC T1.

These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack.

Register windows were one of the main features of the Berkeley RISC design, which would later be commercialized as the AMD Am29000, Intel i960, Sun Microsystems SPARC, and Intel Itanium.

Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The 29000 evolved from the same Berkeley RISC design that also led to the Sun SPARC and Intel i960.

SPARC V9, released in 1993, introduced a 64-bit architecture and was first released in Sun's UltraSPARC processors in 1995.

The Oracle SPARC Architecture 2015 allows 64 bits for virtual memory and, for any given processor, between 40 and 56 bits for physical memory.

This includes not only the non-privileged and most of the privileged portions of SPARC V9, but also all the architectural extensions developed through the processor generations of UltraSPARC III, IV IV+ as well as CMT extensions starting with the UltraSPARC T1 implementation:

The T1 is a new-from-the-ground-up SPARC microprocessor implementation that conforms to the UltraSPARC Architecture 2005 specification and executes the full SPARC V9 instruction set.

SPARC (Scalable Processor Architecture) is a reduced instruction set computing (RISC) instruction set architecture (ISA) originally developed by Sun Microsystems and Fujitsu. Later, SPARC processors were used in symmetric multiprocessing (SMP) and non-uniform memory access (CC-NUMA) servers produced by Sun, Solbourne and Fujitsu, among others. SPARC International was intended to grow the SPARC architecture to create a larger ecosystem; SPARC has been licensed to several manufacturers, including Atmel, Bipolar Integrated Technology, Cypress Semiconductor, Fujitsu, Matsushita and Texas Instruments.

Fujitsu produces the SPARC-compliant CPU (SPARClite), the "Venus" 128 GFLOP SPARC64 VIIIfx model is included in the K computer, the world's fastest supercomputer in June 2011 with a rating of over 8 petaflops, and in November 2011, K became the first computer to top 10 petaflops in September 2011.

Other architectures that include similar register file features include Intel i960, IA-64, and AMD 29000.

The design was later adapted by SPARC, MIPS and some later x86 implementation.

At any point, only 32 of them are immediately visible to software — 8 are a set of global registers (one of which, g0, is hard-wired to zero, so only seven of them are usable as registers) and the other 24 are from the stack of registers.

Sun SPARC, AMD Am29000, and Intel i960 are all examples of architectures using register windows within a register-stack as another strategy to avoid the use of slow main memory for function arguments and return values.

The hyperSPARC, code-named "Pinnacle", is a microprocessor that implements the SPARC Version 8 instruction set architecture (ISA) developed by Ross Technology for Cypress Semiconductor.