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Jul 6, 2021 - Verilog
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hdl
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HDL libraries and projects
Hardware Description Languages
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Mar 29, 2021
VeloView performs real-time visualization and easy processing of live captured 3D LiDAR data from Velodyne sensors (Alpha Prime™, Puck™, Ultra Puck™, Puck Hi-Res™, Alpha Puck™, Puck LITE™, HDL-32, HDL-64E). Runs on Windows, Linux and MacOS
lidar
velodyne-sensor
velodyne
sensor-data
hdl
lidar-measurements
lidar-data-manipulation
lidar-camera-calibration
velodyne-hdl-sensors
sensor-streaming
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Aug 23, 2019 - C++
PlutoSDR Firmware
linux
fpga
sdr
iio
transceiver
rf
hdl
plutosdr
adalm-pluto
active-learning-module
plutosdr-fw
plutosdr-firmware
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Jun 7, 2021 - Shell
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
cmake
asic
fpga
cpp
verification
rtl
verilog
xilinx
vivado
systemverilog
systemc
unit-tests
hdl
modelsim
uvm
verilator
quartus
testing-rtl
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Nov 25, 2019 - SystemVerilog
Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework
python
rtl
verilog
ieee
systemverilog
hdl
open-source-hardware
pymtl
hardware-generation
open-source-eda
multi-level-modeling
cycle-level-modeling
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Jul 6, 2021 - Python
Repurposing existing HDL tools to help writing better code
python
vim
language-server
vhdl
issue-tracker
standalone
verilog
xilinx
syntax-checker
systemverilog
trademarks
hdl
modelsim
questasim
ghdl
xilinx-vivado
lsp-server
coc-nvim
vim-ale
vivado-simulator
mentor-msim
hdl-checker
emacs-lsp
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Jun 5, 2021 - Python
Revengineered ancient PDP-11 CPUs, originals and clones
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May 22, 2021 - Verilog
amstan
commented
Apr 12, 2020
Together with issue #4, we should write a few tests for making sure refdeses do stay consistent. Something like a copy of servo_micro, and a ton of patches on top of it (all parented to one servo_micro, not on a chain, more like a star). Apply each of those patches then see if refdeses are sticking.
git checkout c718fbc~1 examples/servo_micro.py
from google/pcbdl@ba3
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
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Apr 16, 2021 - Verilog
Functional Coverage and Constrained Randomization Extensions for Cocotb
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Aug 7, 2020 - Python
ACT hardware description language and core tools.
language
eda
circuit-simulator
cad
dataflow
chp
dataflow-programming
prs
hdl
vlsi
hardware-description-language
production-rules
design-automation
asynchronous-circuits
vlsi-cad
asynchronous-vlsi
communicating-hardware-processes
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Jul 6, 2021 - Verilog
An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.
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May 2, 2019 - Verilog
DDR2 memory controller written in Verilog
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Feb 28, 2012 - Verilog
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During the work on merging #1419 I figured out that the basic BUFGMUX example works differently on Arty Board and Nexys Video.
The example uses three LEDs:
On the Arty Board, the example works as intended. On Nexys Video, when