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verilator
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qrqiuren
commented
Apr 28, 2021
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// File: dly_warning.sv
// verilator lint_off ASSIGNDLY
module dly_warning (
input logic a_in,
input logic [2:0] delaycw,
output logic a_out
);
timeunit 1ns;
timeprecision 1ns;
time dly;
assign dly = 5 * delaycw;
assign #dly a_out = a_in; // Warning ASSA small, light weight, RISC CPU soft core
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Jul 26, 2021 - Verilog
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If this is not the case a page fault should be generated. Right now we generate an instruction access fault.
https://github.com/pulp-platform/ariane/blob/ad70ce1f30dad539e5a365ffe71a02aaf20b397e/src/load_store_unit.sv#L339