Verilog to Routing

Repositories

• vtr-verilog-to-routing

  Verilog to Routing -- Open Source CAD Flow for FPGA Research

  fpga routing eda cad verilog synthesis placement
  C++ 219 487 248 (15 issues need help) 30 Updated Apr 26, 2021

• verilog-to-routing.github.io

  Website for Verilog to Routing
  CSS 2 4 0 0 Updated Aug 17, 2020

• libblifparse

  Parsing library for BLIF netlists
  C++ MIT 8 9 2 1 Updated Jul 1, 2020

• tatum

  Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

  eda cad sta tatum
  C++ MIT 5 27 3 0 Updated Jun 9, 2020

• libsdcparse
  C++ MIT 4 5 2 1 Updated Jan 29, 2020

• vtr-buildbot

  Buildbot Infrastructure for VTR
  HTML 3 3 0 0 Updated Dec 12, 2019