#
chisel
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ccelio
commented
Oct 20, 2017
Summary:
A nice-to-have feature is the ability to enable and disable hardware features from the software.
Examples:
- Enable TSO memory consistency
- Enable watchdog timer
- Change predictor behaviors
High-level thoughts:
- Do not use non-standard Control/Status Registers (CSRs). The address space will get too congested, not indexable, messy to assemble for, etc.
- Inst
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
boom
rocket
rocket-chip
chip-generator
chisel
riscv
rtl
peripherals
soc
out-of-order
superscalar
risc-v
firesim
accelerators
chipyard
hwacha
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Updated
Jul 23, 2021 - C
LogicalError
commented
Sep 23, 2020
See title.
Hardest part is probably icon design, and where to place it
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Updated
Jan 23, 2020 - Scala
Provides dot visualizations of chisel/firrtl circuits
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Updated
May 28, 2021 - Scala
nijssen
commented
May 16, 2020
Example:
module Adder :
...
output io : {..., signed : UInt<1>, ...}
Will cause an output of:
UInt<1> signed;
To which the compiler complains:
error: declaration does not declare anything [-fpermissive]
This is because signed
is a C++ keyword, in addition to being the name of that signal.
The behavior should be changed to not emit names that a
A fault-injection framework using Chisel and FIRRTL
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Updated
Sep 4, 2018 - Scala
Quasar 2.0: Chisel equivalent of SweRV-EL2
scala
processor
chisel
riscv
rtl
chisel3
open-source-hardware
verilator
asic-verification
axi4
ahb-lite
asic-design
swerv
swerv-el2
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Updated
Apr 13, 2021 - Scala
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
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Updated
Jul 30, 2019 - Scala
Implementation of the Advanced Encryption Standard in Chisel
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Updated
Nov 14, 2019 - Scala
Network components (NIC, Switch) for FireBox
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Updated
Dec 13, 2020 - Scala
A series of RISC-V soft core processor written from scratch. Under developing, we use all open-source toolchain such as chisel, mill build tool and verilator, etc. Among them AM and difftest framework are from the NJU-ProjectN
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Updated
Jul 23, 2021 - Verilog
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Type of issue: other enhancement
Impact: no functional change
Development Phase: request
Other information
This is more a meta-issue mostly related to the beginners user experience. I think most of these issues are not done by more experienced devs.
If the current behavior is a bug, please provide the steps to reproduce the problem: