Yale Asynchronous VLSI and Architecture Group

dflowmap Public
Convert ACT dataflow to simulatable ACT CHP

C++ 0 GPL-2.0 0 1 0 Updated Apr 18, 2022
act Public
ACT hardware description language and core tools.

C++ 53 GPL-2.0 14 0 2 Updated Apr 18, 2022
magic Public
Magic VLSI Layout Tool

C 0 63 0 0 Updated Apr 16, 2022
interact Public
Command-line design environment for asynchronous logic

C++ 3 GPL-2.0 1 1 0 Updated Apr 16, 2022
chp2prs Public
Automated conversion from CHP to PRS using syntax-directed translation

C++ 3 GPL-2.0 5 4 0 Updated Apr 16, 2022
stdlib Public
ACT standard library

Makefile 2 Apache-2.0 2 0 0 Updated Apr 15, 2022
Xyce Public
The Xyce™ Parallel Electronic Simulator

C 0 GPL-3.0 32 0 0 Updated Apr 12, 2022
phyDB Public
Library that holds the physical database

C++ 2 LGPL-2.1 1 0 0 Updated Apr 5, 2022
prs2fpga Public
Translate production rules into Verilog for accelerated simulation on FPGAs

C++ 0 GPL-2.0 0 0 0 Updated Mar 20, 2022
SPRoute Public
A parallel global router using the Galois framework

C++ 11 4 0 0 Updated Mar 13, 2022

Pinned