verilog-hdl

Various HDL (Verilog) IP Cores

Python-based Hardware Design Processing Toolkit for Verilog HDL

Veriloggen: A Mixed-Paradigm Hardware Construction Framework

NNgen: A Fully-Customizable Hardware Synthesis Compiler for Deep Neural Network

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

High throughput JPEG decoder in Verilog for FPGA

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

2017级北航计算机学院计算机组成原理课程设计(MIPS CPU)

A complete Open Source Design for Testing (DFT) Solution

Image Processing Toolbox in Verilog using Basys3 FPGA

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

5-stage pipelined 32-bit MIPS microprocessor in Verilog

This is a higan/Verilator co-simulation example/framework

Verilog generation tool written in Rust

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

中山大学计算机组成原理实验 (2018 秋)：用 Verilog 设计并实现的简易单周期和多周期 CPU

Gigabit Ethernet UDP communication driver

A simple implementation of a UART modem in Verilog.

FPGA implementation of deflate (de)compress RFC 1950/1951

This is a tutorial on standard digital design flow

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

An efficient implementation of the Viterbi decoding algorithm in Verilog

Simple 8-bit computer build in Verilog

Implementing Different Adder Structures in Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

Interface Protocol in Verilog

Super scalar Processor design