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altera

Here are 144 public repositories matching this topic...

hdl-util / hdmi

Star

Open

Translate README.md

sameer commented May 16, 2020

If you speak another language, I would appreciate your help in translating the README.md.

For tables, checklists, or other data that might change, please indicate that that information is in the main README. Otherwise every change to the main README will need to be replicated to the other READMEs.

^ I've tried to do this a bit in the French README. The only thing you need to replicate when

Read more

help wanted good first issue

VLSI-EDA / PoC

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IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Updated Nov 29, 2020
VHDL

f32c / f32c

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A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

arduino fpga mips riscv xilinx altera lattice

Updated Jul 23, 2020
VHDL

pConst / basic_verilog

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Must-have verilog systemverilog modules

Updated Aug 18, 2021
Verilog

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Sep 3, 2021
Python

OpenFPGAduino / OpenFPGAduino

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All open source file and project for OpenFPGAduino project

nodejs javascript c iot arduino arm opensource fpga cpp hardware verilog blockly grove-shield iiot altera

Updated Oct 27, 2018
Makefile

thinkoco / c5soc_opencl

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DE1SOC DE10-NANO DE10-Standard OpenCL hardware that support VGA and desktop. And Some applications such as usb camera YUYV to RGB , Sobel and so on.

fpga opencl mandelbrot altera de1-soc vga sobel usb-cameras intelfpga de10-nano

Updated Nov 7, 2020
Verilog

drandyhaas / Haasoscope

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Docs, design, firmware, and software for the Haasoscope

python open-source fpga eagle open-hardware data-acquisition verilog oscilloscope altera

Updated Jul 7, 2021
Verilog

suoto / vim-hdl

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Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

productivity pathogen vhdl vim-plugins verilog xilinx syntastic syntax-checker altera systemverilog trademarks vundle modelsim hdlcc-issue-tracker vimhdl-issue-tracker vim-hdl registered-trademarks

Updated Jun 1, 2021
Python

mithro / ixo-usb-jtag

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usb-jtag - Altera USB Blaster Emulation with a FX2

fpga xilinx altera usb-devices openocd jtag numato-opsis digilent-atlys cypress-fx2 ezusb digilent opsis numato urjtag

Updated Jul 7, 2021
C++

capitanov / intfftk

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Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

Updated Aug 14, 2020
VHDL

awesome-fpga-boards

iDoka / awesome-fpga-boards

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Second life for FPGA boards which can be repurposed to DYI/Hobby projects

microsoft awesome fpga zynq intel xilinx awesome-list ethernet altera lattice jtag bmc antminer qsfp pci-e ecp5 colorlight chubby75

Updated Jan 12, 2021

MohammedRashad / FPGA-Speech-Recognition

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Expiremental Speech Recognition System using VHDL & MATLAB.

fpga distance matlab vhdl speech-recognition signal pattern-recognition uart altera digital-signal-processing audio-processing hamming-distance euclidean-distances speech-recognition-engine domain-signals

Updated Mar 18, 2018
VHDL

panda5mt / KyogenRV

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The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

fpga intel chisel riscv chisel3 altera risc-v rv32i avalon-mm

Updated Apr 11, 2021
Scala

capitanov / fp23fftk

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Floating point Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source lang. - VHDL).

Updated Aug 14, 2020
VHDL

VladisM / MARK_II

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Simple SoC in VHDL with full toolchain and custom board.

toolchain cpu fpga compiler vhdl assembler intel altera soc vbcc mark-ii max10

Updated Jun 4, 2018
VHDL

HPS2FPGAmapping

robseb / HPS2FPGAmapping

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SoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)

linux fpga python-script intel bootloader altera can-bus fpga-soc embedded-linux quartus-prime intel-fpga altera-fpga hps fpga-configuration soc-fpga fpga-fabric mapping-hps-peripherals rsyocto

Updated Jun 9, 2021
Verilog

HengRuiZ / from-key-array-to-the-LED-lattice

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fpga vhdl altera

Updated Aug 8, 2017
VHDL

halfmanhalftaco / fpga-docker

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Tools for running FPGA vendor toolchains with Docker

fpga vhdl verilog xilinx altera lattice quartus

Updated Aug 24, 2021
Makefile

delhatch / Spectrum

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Spectrum analyzer system using a 512-point FFT, in a Cyclone IV FPGA. Reads i2s audio from the codec and then does all FFT/VGA functions. Nios just reads the FFT result and draws the display bars. VGA frame buffer on-chip. VGA signals generated on-chip. See the included video files to watch it in action.

fpga audio-analysis verilog spectrum-analyzer fft altera rtaudio vga de2-115 vga-frame-buffer

Updated Feb 9, 2018
VHDL

PyFPGA / pyfpga

Star

Open

Improve the Vivado block design example

rodrigomelo9 opened Feb 11, 2021

enhancement good first issue

Open

Verify windows support

4

thinkoco / de10-nano-riscv

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A RISC-V SoC ( Hbird e203 ) on Terasic DE10-Nano

riscv altera risc-v intelfpga de10-nano

Updated Jul 29, 2020
Verilog

sevvalmehder / 32-bit-MIPS-Processor

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A 32-bit MIPS processor used Altera Quartus II with Verilog.

register mips processor opcodes datapath altera quartus

Updated Sep 20, 2018
Verilog

thotypous / alterajtaguart

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Altera JTAG UART wrapper for Bluespec

bluespec uart usb-serial-adapters altera hardware-libraries jtag

Updated Mar 27, 2014
C

dilshan / max2-audio-dac

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24-bit Stereo Audio DAC for Raspberry Pi

audio raspberry-pi altera cpld dac i2s-audio r-2r epm240t100c5n

Updated Jan 27, 2020
Verilog

obiwanjacobi / Zalt

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Zalt is a home brew Z80 computer with a modern(isch) chipset.

c z80 z80asm altera kicad cpld quartus psoc5lp wincupl

Updated Sep 2, 2021
C

stpe / jniosemu

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JNiosEmu is an educational Nios II based development environment and emulator with the purpose of making it easy to learn programming in assembler. Assemble your source with a single button click, immediately see how values change in a register or memory. All this without any prior knowledge of assembler programming or complex tool chains.

java emulator assembler altera nios

Updated Mar 17, 2021
Java

Wissance / QuickSPI

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Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Updated Nov 21, 2017
Verilog

capitanov / adc_configurator

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ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)

ddr dsp vhdl xilinx adc ddc altera dds digital-signal-processing fir jesd204b analog-signals serial-interface cic dac adc-configurator serdes-mode

Updated Aug 29, 2018
VHDL

delhatch / Red_Tracker

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Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

fpga image-processing verilog altera vga de2-115 vga-controller

Updated Jan 19, 2018
Verilog

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