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63 public repositories
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F# RISC-V Instruction Set formal specification
Small Processing Unit 32: A compact RV32I CPU written in Verilog
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Updated
Oct 21, 2021
Assembly
Simple single cycle RISC processor written in Verilog
Updated
Mar 23, 2018
Verilog
9444 RISC-V 64IMA CPU and related tools and peripherals.
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
Updated
Jun 19, 2021
VHDL
Implementation of the RISC-V 32 bit Integer and Compressed Instructions in Verilog.
Updated
May 29, 2020
Verilog
Open source ISS and logic RISC-V 32 bit project
A RISC-V virtual processor, written in Rust.
Updated
Aug 26, 2020
Rust
Implementation of a 24 bit RISC processor
Updated
Nov 18, 2019
Verilog
Fork of a RISC-V compliant CPU, which originated in a project at the HAW Hamburg
Single Cycle RISC MIPS Processor
Updated
Sep 17, 2021
Verilog
A real time Microprocessor impemented in verilog and tested on Xilinx Artix FPGA.
Updated
Mar 15, 2021
VHDL
The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.
Updated
Apr 10, 2021
Verilog
RISC-V five stage pipline CPU
Updated
Jul 26, 2019
SystemVerilog
Updated
Jan 7, 2021
Verilog
Procesador RISC segmentado creado con Proteus con Unidad de control, 5 segmentos, corrección de errores mediante unidad de detección de conflictos (DC) y ALU.
Arbitary superscalar out-of-order RV32I core, with instruction prefetching and write-back no-write-allocate DCache.
Updated
Oct 8, 2020
SystemVerilog
Single Cycle MIPS Pipelined Processor using Verilog
Updated
Aug 22, 2021
Verilog
🔧 MiniJava language compiler written in C++
Verilog implementation of multi-stage 32-bit RISC-V processor
Updated
Nov 2, 2020
Verilog
A Verilog RTL model of a simple 8-bit RISC processor
Updated
Jan 15, 2019
Verilog
A 16-bit RISC CPU inspired by MIPS. I designed this to learn more about computer architecture/organization.
Updated
Aug 3, 2020
Verilog
Updated
Nov 26, 2021
JavaScript
Final project for the class "Digital Design with Verilog and SystemVerilog"
Updated
Oct 19, 2021
SystemVerilog
VHDL implementation of multicycle and pipelined RISC architecture - EE309 Autumn 2018, IIT Bombay
RISC TILE64 implementation in python
Updated
Apr 4, 2017
Python
A small elevator control system that runs on ATMEL's 8-bit microcontroller.
SISA Architecture Emulator
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