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verilog-project

Here are 122 public repositories matching this topic...

sudhamshu091 / 32-Verilog-Mini-Projects

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

verilog verilog-hdl miniproject verilog-project

Updated Jul 17, 2022
Verilog

Gowtham1729 / Image-Processing

Image Processing Toolbox in Verilog using Basys3 FPGA

python fpga ram pixel vhdl python3 verilog brightness convolution vivado motion-blur verilog-hdl basys3 hsync basys basys-board coe verilog-project basys3-fpga

Updated Nov 4, 2020
VHDL

neelkshah / MIPS-Processor

5-stage pipelined 32-bit MIPS microprocessor in Verilog

verilog microprocessor stage computer-architecture microprocessors verilog-hdl mips-architecture mips-processor bits-pilani computer-organization verilog-components verilog-snippets mips-instructions computer-organisation verilog-programs verilog-simulator verilog-project

Updated Apr 3, 2020
Verilog

adibis / DDR2_Controller

DDR2 memory controller written in Verilog

ddr verilog hdl verilog-project

Updated Feb 28, 2012
Verilog

zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial

Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in this ALU. The ALU operation will take two clocks. The first clock cycle will be used to load values into the registers. The second will be for performing the operations. 6-bit opcodes are used to select the functions. The instruction code, including the opcode, will be 18-bit.

cpu processor simd verilog alu adder instruction-set-architecture cadence-virtuoso multiplier verilog-project processor-design

Updated Jul 17, 2022
Verilog

ashishrana160796 / verilog-starter-tutorials

Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.

practice embedded-systems verilog up-for-grabs circuit switches beginner-friendly logic-gates hdl verilog-hdl iverilog verilog-snippets verilog-programs verilog-project

Updated Nov 25, 2020
Verilog

mongrelgem / Verilog-Adders

Implementing Different Adder Structures in Verilog

verilog hardware-designs adder verilog-hdl verilog-project

Updated Sep 3, 2019
Verilog

TheSUPERCD / 8bit_MicroComputer_Verilog

This project was inspired by the efforts of Ben Eater to build an 8 bit computer on a breadboard. Even though this one was not built on a breadboard, it has the functionalities of his computer and modelled using Verilog HDL. This was developed for the Mini Project in Digital Systems course in my 3rd semester at IIT Palakkad.

verilog verilog-hdl 8bit iverilog verilog-project ben-eater verilog-code ben-eaters-cpu

Updated Jul 27, 2020
Verilog

vedic-partap / Computer-Organization-and-Architecture-LAB

Solution to COA LAB Assgn, IIT Kharagpur

cpu mips-assembly verilog hardware-designs coa verilog-project

Updated Jan 10, 2019
Verilog

ultraembedded / minispartan6-audio

Sponsor

miniSpartan6+ (Spartan6) FPGA based MP3 Player

audio fpga verilog sd-card mp3player risc-v spartan6 rv32im verilog-project

Updated Sep 2, 2019
Verilog

pobu-arch / pumpkin

computer-architecture cpu-model microarchitecture verilog-project

Updated Jul 22, 2019
Verilog

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

sarthak268 / Embedded_Logic_and_Design

Sponsor

This repository contains all labs done as a part of the Embedded Logic and Design course.

Updated Jun 10, 2018

adibis / Interrupt_Controller

An 8 input interrupt controller written in Verilog.

verilog hdl verilog-components verilog-project

Updated Mar 22, 2012
Verilog

LutingWang / FPGA

BUAA Computer Organization Project8 FPGA

fpga computer-architecture mips32cpu verilog-project

Updated Jan 19, 2019
Verilog

MaorAssayag / Computer-Engineering-Projects

Digital computer structure, Hardware Design Lab & Introduction to Computers for computer engineering projects in C, C#, Assembly, Pspice.

c visual-studio csharp communication application-design controller assembly verilog autonomous-vehicles comunication codewarrior pspice systemverilog-simulation verilog-project

Updated Jan 19, 2019
Verilog

RPG-7 / HGA101_GPU

gpgpu verilog-project soc-suite

Updated Dec 21, 2020
Verilog

tongplw / Undertale-Verilog

👻 Simple Undertale-like game on Basys3 FPGA written in Verilog

fpga verilog uart fpga-game vga undertale basys3 fpga-board verilog-project basys3-fpga

Updated Jul 3, 2020
Verilog

mihir8181 / VerilogHDL-Codes

Synthesizable Verilog Source Codes(DUT), Test-bench and Simulation Results.

counter fsm asynchronous verilog fifo testbenches verilog-hdl verilog-programs mealy-machine-code moore-machine-code verilog-project fifo-buffer verilog-code n-bit-alu verilogvalidation design-under-test asynchronous-fifo fifo-verilog

Updated May 10, 2019
Verilog

sudhamshu091 / Single-Cycle-Risc-Processor-32-bit-Verilog

Single Cycle RISC MIPS Processor

verilog risc risc-v risc-processor verilog-project

Updated Sep 17, 2021
Verilog

tarlaun / CORDIC

Digital System Design Project - Spring 2020

xilinx-ise cordic cordic-algorithm verilog-project

Updated Aug 7, 2020
Verilog

coole198669 / viterbi_decoder

Hardware Viterbi Decoder in verilog

verilog-project viterbi-decoder

Updated May 28, 2019
Verilog

flasonil / Serial-Multiplier

16 bit serial multiplier in SystemVerilog

verilog systemverilog system-verilog verilog-project

Updated Oct 13, 2018
SystemVerilog

Anand270294 / AES-encryption-VSLI

EE4415 Project : AES Verilog

digital-design verilog-project

Updated Apr 25, 2019
Verilog

luk3Sky / Building-A-Processor---Project

Design of a simulated 8-bit single-cycle processor using Verilog HDL, which includes an ALU, a register file and other control logic

processor-architecture alu hdl verilog-hdl verilog-project

Updated Jan 28, 2019
Verilog

pendkeomkar / SPI

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols that are widely used in today's complex systems.The I2C bus has a minimum pin count requirement and therefore a smaller footprint on the board. The SPI bus provides a synchronized serial link with performance in MHz range.The project implements the bridge between the two protocols and serves as an interface between these two which allow direct communication and a solution to reduce development time and cost for complex embedded systems.

verification verilog spi uvm verification-methodologies verilog-hdl verilog-programs verification-codes verilog-project verification-component

Updated Aug 21, 2018

aekanshd / booths-multiplier-using-verilog

verilog booths-algorithm verilog-project

Updated Feb 11, 2019
Verilog

powerplayer9 / Voice-Based-Motor-Control

A verilog HDL based project to control a servomotor with voice commands from an android phone.

voice-commands bluetooth motor-controller verilog-hdl servo-motor quartus de10-nano verilog-project terasic-rfs

Updated Nov 11, 2019
Verilog

djzenma / 2-FPGAs-UART-Protocol

Transmitter and Receiver FPGAs connected using the UART Protocol to execute arithmetic operations and display the inputs on the transmitter's 7 Segment Display as well as the result on the Receiver's 7 Segments Display.

fpga verilog hardware-designs uart-protocol verilog-project

Updated Aug 31, 2018
HTML

cw1997 / SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol

hardware systemverilog hardware-designs sdram sdram-controller verilog-project

Updated Jul 1, 2022
HTML

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