#
xilinx-fpga
Here are 154 public repositories matching this topic...
rw1nkler
commented
Aug 21, 2020
During the work on merging #1419 I figured out that the basic BUFGMUX example works differently on Arty Board and Nexys Video.
The example uses three LEDs:
- led[2] - blinks with slow frequency
- led[1] - blinks with high frequency
- led[0] - blinks with the same frequency as led[2] or led[1] depending on sw[0] state.
On the Arty Board, the example works as intended. On Nexys Video, when
Xilinx Virtual Cable Server for Raspberry Pi
-
Updated
Mar 14, 2022 - C
agozillon
commented
Jul 23, 2019
Things like XILINX_XRT which are set by the user and others like XILINX_DEVICE_ONLY that are set by the compiler but affect the code users compile may be useful to add.
Minimal DVI / HDMI Framebuffer
-
Updated
Aug 9, 2020 - Verilog
FTDI FT600 SuperSpeed USB3.0 to AXI bus master
-
Updated
Jun 6, 2020 - C++
Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.
fpga
verilog
logic-analyzer
xilinx-fpga
altera-fpga
lattice-fpga
digital-signal-analyzer
ftdi232h
ftdi2232h
-
Updated
Jun 24, 2021 - Verilog
Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.
-
Updated
Feb 9, 2022 - SystemVerilog
Open-source CSI-2 receiver for Xilinx UltraScale parts
-
Updated
Jul 10, 2019 - Verilog
Plugins for Yosys developed as part of the F4PGA project.
-
Updated
Apr 11, 2022 - Verilog
-
Updated
Jul 9, 2019 - VHDL
This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
calculator
vhdl
matrix-multiplication
verilog
xilinx
hardware-designs
xilinx-fpga
low-level-programming
xilinx-ise
xilinx-vivado
ic-design
-
Updated
Aug 12, 2017 - Verilog
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its MultiZone Security Trusted Execution Environment and MultiZone Security Trusted Firmware. The X300 is an enhanced secure version of the - now archived - SiFive's Freedom E300 Platform built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
fpga
rocket-chip
xilinx
fpga-soc
risc-v
xilinx-fpga
bitstream
digilent
e300
artix-100t
sifive-freedom
arty-a7
artix-35t
-
Updated
Oct 19, 2021 - Scala
中国科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
-
Updated
Jun 24, 2017 - Verilog
Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.
fpga
verilog
hdmi
xilinx-fpga
rgb2yuv
gamma-correction
mipi
yuv2rgb
piecewise-linear-approximation
sea-s7
spartan7
-
Updated
Jul 30, 2020 - VHDL
PS/2 Keyboard IP written in VHDL for Xilinx FPGA
-
Updated
Jul 11, 2015 - VHDL
My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)
-
Updated
Jun 1, 2020 - VHDL
2d Images processing system with FPGA (Zynq 7k) from two dragster linescanner (DR-2k-7)
computer-vision
fpga
image-processing
verilog
optics
optical
2d
xilinx-fpga
frequency-analysis
dragster
cmosis
awaiba
optical-mark-recognition
xilinx-vivado
optical-system
frequency-measurment
dr-2k-7
optical-measurements
2d-scaner
optical-sensors
-
Updated
Sep 15, 2017 - VHDL
A Xilinx IP Core and App for line scanner image capture and store
image
video
computer-vision
scanner
spi
capture-the-flag
xilinx-fpga
dragster
linescanners
cmosis
awaiba
two-channel-image-capture-system
axi-vdma
axi-quad-spi
video-ip-core
xilinx-vivado
dr-2k-7
xilinx-axi-vdma
xilinx-ip
-
Updated
Sep 5, 2017 - VHDL
Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
spi-interface
fpga
spi
altera
verilog-hdl
xilinx-fpga
xilinx-vivado
verilog-components
axi
verilog-snippets
spi-hdl
spi-ip-core
spi-pld
spi-fpga
verilog-spi
axi-interfaces
bit-oriented-spi
soft-spi
hard-spi
dragster-spi
-
Updated
Nov 21, 2017 - Verilog
This repository contains all labs done as a part of the Embedded Logic and Design course.
c
arm
vhdl
embedded-systems
verilog
xilinx
vivado
logic-programming
zedboard
verilog-hdl
xilinx-fpga
logic-circuit
xilinx-vivado
embedded-c
vhdl-code
pmod
xilinx-sdk
verilog-programs
verilog-project
embedded-logic
-
Updated
Jun 10, 2018
Learn how to create your own 32-bit system from scratch.
fpga
hardware
vivado
retrogaming
xilinx-fpga
68k
digilent
68000
arty
gcc-cross-compiler
gameduino
68k-assembly
-
Updated
Feb 15, 2022 - Assembly
High-Level Synthesis with Partial Evaluation
-
Updated
Jan 18, 2022 - CMake
Advanced System on Chip Design Education Kit
arm
fpga
hardware
armv7
hdmi
xilinx-fpga
system-on-chip
axi
amba
zynq-7000
axi4
zybo-z7
cortex-a9
arm-cortex-a9
arm-processors
soc-design
-
Updated
Jan 13, 2022 - HTML
This repository contains lab assignments done in the course CS220: Computer Organization at IIT Kanpur
-
Updated
Aug 8, 2019 - HTML
Implemented an ultrasonic sensor to measure and visualize distances on the FPGA 7-seg Display and LEDs.
vhdl
ultrasonic-sensor
xilinx-fpga
7segment
vhdl-modules
vhdl-code
nexys4ddr
parking-sensor
fpga-programming
-
Updated
Dec 5, 2019 - VHDL
VHDL design for rotary encoder. Can be used accessed via digital signals or AXI interface.
-
Updated
Mar 24, 2017 - VHDL
SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
-
Updated
Dec 15, 2019 - Verilog
Improve this page
Add a description, image, and links to the xilinx-fpga topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the xilinx-fpga topic, visit your repo's landing page and select "manage topics."
All the tools in prjxray should have an
xc7prefix, so to make them unique.E.g.
bitreadorbittoolcould enter in conflicts with other tools names.