3.

3 System Tasks and Compiler Directives

In this section, we introduce two special concepts used in Verilog: system tasks and
compiler directives.

3.3.1 System Tasks

Verilog provides standard system tasks for certain routine operations. All system tasks
appear in the form $<keyword>. Operations such as displaying on the screen, monitoring
values of nets, stopping, and finishing are done by system tasks. We will discuss only the
most useful system tasks. Other tasks are listed in Verilog manuals provided by your
simulator vendor or in the IEEE Standard Verilog Hardware Description Language
specification.

Displaying information

$display is the main system task for displaying values of variables or strings or
expressions. This is one of the most useful tasks in Verilog.

Usage: $display(p1, p2, p3,....., pn);

p1, p2, p3,..., pn can be quoted strings or variables or expressions. The format of $display
is very similar to printf in C. A $display inserts a newline at the end of the string by
default. A $display without any arguments produces a newline.

Strings can be formatted using the specifications listed in Table 3-4. For more detailed
specifications, see IEEE Standard Verilog Hardware Description Language specification.

Table 3-4. String Format Specifications

Format Display
%d or %D Display variable in decimal
%b or %B Display variable in binary
%s or %S Display string
%h or %H Display variable in hex
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%c or %C Display ASCII character
%m or %M Display hierarchical name (no argument required)
%v or %V Display strength
%o or %O Display variable in octal
%t or %T Display in current time format
%e or %E Display real number in scientific format (e.g., 3e10)
%f or %F Display real number in decimal format (e.g., 2.13)
%g or %G Display real number in scientific or decimal, whichever is shorter

Example 3-3 shows some examples of the $display task. If variables contain x or z
values, they are printed in the displayed string as "x" or "z".

Example 3-3 $display Task

//Display the string in quotes

$display("Hello Verilog World");
-- Hello Verilog World

//Display value of current simulation time 230

$display($time);
-- 230

//Display value of 41-bit virtual address 1fe0000001c at time 200

reg [0:40] virtual_addr;
$display("At time %d virtual address is %h", $time, virtual_addr);
-- At time 200 virtual address is 1fe0000001c

//Display value of port_id 5 in binary

reg [4:0] port_id;
$display("ID of the port is %b", port_id);
-- ID of the port is 00101

//Display x characters
//Display value of 4-bit bus 10xx (signal contention) in binary
reg [3:0] bus;
$display("Bus value is %b", bus);
-- Bus value is 10xx

//Display the hierarchical name of instance p1 instantiated under

//the highest-level module called top. No argument is required. This
//is a useful feature)
$display("This string is displayed from %m level of hierarchy");
-- This string is displayed from top.p1 level of hierarchy

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Special characters are discussed in Section 3.2.9, Strings. Examples of displaying special
characters in strings as discussed are shown in Example 3-4.

Example 3-4 Special Characters

//Display special characters, newline and %

$display("This is a \n multiline string with a %% sign");
-- This is a
-- multiline string with a % sign

//Display other special characters

Monitoring information

Verilog provides a mechanism to monitor a signal when its value changes. This facility is
provided by the $monitor task.

Usage: $monitor(p1,p2,p3,....,pn);

The parameters p1, p2, ... , pn can be variables, signal names, or quoted strings. A format
similar to the $display task is used in the $monitor task. $monitor continuously monitors
the values of the variables or signals specified in the parameter list and displays all
parameters in the list whenever the value of any one variable or signal changes. Unlike
$display, $monitor needs to be invoked only once.

Only one monitoring list can be active at a time. If there is more than one $monitor
statement in your simulation, the last $monitor statement will be the active statement.
The earlier $monitor statements will be overridden.

Two tasks are used to switch monitoring on and off.

Usage:

$monitoron;
$monitoroff;

The $monitoron tasks enables monitoring, and the $monitoroff task disables monitoring
during a simulation. Monitoring is turned on by default at the beginning of the simulation
and can be controlled during the simulation with the $monitoron and $monitoroff tasks.
Examples of monitoring statements are given in Example 3-5. Note the use of $time in
the $monitor statement.

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Example 3-5 Monitor Statement

//Monitor time and value of the signals clock and reset

//Clock toggles every 5 time units and reset goes down at 10 time units
initial
begin
$monitor($time,
" Value of signals clock = %b reset = %b", clock,reset);
end

Partial output of the monitor statement:

-- 0 Value of signals clock = 0 reset = 1

-- 5 Value of signals clock = 1 reset = 1
-- 10 Value of signals clock = 0 reset = 0

Stopping and finishing in a simulation

The task $stop is provided to stop during a simulation.

Usage: $stop;

The $stop task puts the simulation in an interactive mode. The designer can then debug
the design from the interactive mode. The $stop task is used whenever the designer wants
to suspend the simulation and examine the values of signals in the design.

The $finish task terminates the simulation.

Usage: $finish;

Examples of $stop and $finish are shown in Example 3-6.

Example 3-6 Stop and Finish Tasks

// Stop at time 100 in the simulation and examine the results

// Finish the simulation at time 1000.
initial // to be explained later. time = 0
begin
clock = 0;
reset = 1;
#100 $stop; // This will suspend the simulation at time = 100
#900 $finish; // This will terminate the simulation at time = 1000
end

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3.3.2 Compiler Directives

Compiler directives are provided in Verilog. All compiler directives are defined by using
the `<keyword> construct. We deal with the two most useful compiler directives.

`define

The `define directive is used to define text macros in Verilog (see Example 3-7). The
Verilog compiler substitutes the text of the macro wherever it encounters a
`<macro_name>. This is similar to the #define construct in C. The defined constants or
text macros are used in the Verilog code by preceding them with a ` (back tick).

Example 3-7 `define Directive

//define a text macro that defines default word size

//Used as 'WORD_SIZE in the code
'define WORD_SIZE 32

//define an alias. A $stop will be substituted wherever 'S appears

'define S $stop;

//define a frequently used text string

'define WORD_REG reg [31:0]
// you can then define a 32-bit register as 'WORD_REG reg32;

`include

The `include directive allows you to include entire contents of a Verilog source file in
another Verilog file during compilation. This works similarly to the #include in the C
programming language. This directive is typically used to include header files, which
typically contain global or commonly used definitions (see Example 3-8).

Example 3-8 `include Directive

// Include the file header.v, which contains declarations in the

// main verilog file design.v.
'include header.v
...
...
<Verilog code in file design.v>
...
...

Two other directives, `ifdef and `timescale, are used frequently. They are discussed in
Chapter 9, Useful Modeling Techniques.
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3.4 Summary

We discussed the basic concepts of Verilog in this chapter. These concepts lay the
foundation for the material discussed in the further chapters.

• Verilog is similar in syntax to the C programming language . Hardware designers

with previous C programming experience will find Verilog easy to learn.

• Lexical conventions for operators, comments, whitespace, numbers, strings, and

identifiers were discussed.

• Various data types are available in Verilog. There are four logic values, each with
different strength levels. Available data types include nets, registers, vectors,
numbers, simulation time, arrays, memories, parameters, and strings. Data types
represent actual hardware elements very closely.

• Verilog provides useful system tasks to do functions like displaying, monitoring,

suspending, and finishing a simulation.

• Compiler directive `define is used to define text macros, and `include is used to
include other Verilog files.

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