SpyGlass® area

Rules Reference Guide

Version L-2016.06, June 2016
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Table of Contents

Preface..........................................................................................7
About This Book ...................................................................................... 7
Contents of This Book ............................................................................. 8
Typographical Conventions ..................................................................... 9

Using the Rules in the SpyGlass area Product .............................11

Running the SpyGlass area Product ...................................................... 12
SpyGlass area Rule Parameters............................................................. 13
area_Factor ........................................................................................ 13
audit_cell_details................................................................................. 13
blackbox ............................................................................................ 15
greybox ............................................................................................. 15
proto_2_Nand ..................................................................................... 16
report_all_cells ................................................................................... 17
rptallmodulegatecount.......................................................................... 17
rtl_Nand_Area..................................................................................... 18
size_Buf ............................................................................................. 21
Product Reports .................................................................................... 23
diff .................................................................................................... 23
GateCountReport ................................................................................. 25

Rules in SpyGlass area ................................................................27

Overview............................................................................................... 27
GateCount : Reports gate and instance counts for the complete hierarchy of
design ............................................................................ 28
ResourceShare : Reports sub-expressions in RTL that can be shared to
minimize area ................................................................. 35

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Table of Contents

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Preface

About This Book

The SpyGlass® area Rules Reference Guide describes the SpyGlass rules
that check HDL designs for area-related design issues.

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Preface

Contents of This Book

Contents of This Book

The SpyGlass DFT Rules Reference has the following chapters:

Chapter Describes...
Using the Rules in the SpyGlass Describes how to use the rules in
area Product the SpyGlass area product
Rules in SpyGlass area Describes the rules in the SpyGlass
area product

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Preface

Typographical Conventions

Typographical Conventions
This document uses the following typographical conventions:

To indicate Convention Used

Program code OUT <= IN;
Object names OUT
Variables representing <sig-name>
objects names
Message Active low signal name '<sig-name>' must end
with _X.
Message location OUT <= IN;
Reworked example OUT_X <= IN;
with message removed
Important Information NOTE: This rule...

The following table describes the syntax used in this document:

Syntax Description
[ ] (Square brackets) An optional entry
{ } (Curly braces) An entry that can be specified once or multiple
times
| (Vertical bar) A list of choices out of which you can choose
one
... (Horizontal Other options that you can specify
ellipsis)

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Preface

Typographical Conventions

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Using the Rules in the
SpyGlass area Product

The SpyGlass® area product has the following usage features:

 Running the SpyGlass area Product
 SpyGlass area Rule Parameters
 Product Reports

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Using the Rules in the SpyGlass area Product

Running the SpyGlass area Product

Running the SpyGlass area Product

1. Invoke the Atrenta Console GUI with the following command-line
options, depending upon the language of the design:
%> spyglass
2. Select the required goals containing the rules in the SpyGlass area
product.
Change other settings and analyze your design as described in the Atrenta
Console User Guide.

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SpyGlass area Rule Parameters

SpyGlass area Rule Parameters

This section provides detailed information on the SpyGlass area product
rule parameters.
You can set these parameters in both Atrenta Console and Tcl by using the
following syntax:
set_parameter <parameter_name> <parameter_value>
For more information on setting the parameters, refer to the SpyGlass Tcl
Interface User Guide and Atrenta Console User Guide.

area_Factor
(Optional) Specifies the area factor for the GateCount rule.
The default value of the area factor is 1.0.
Use the area_Factor rule parameter as follows:
set_parameter area_Factor <num>
Where, <num> is a double number.

Used by GateCount
Options Double number specifying the area factor
Default value 1.0
Example
Console/Tcl-based set_parameter area_Factor 1.5
usage
Usage in goal/source -area_Factor=1.5
files

audit_cell_details
(Optional) Specifies the absolute or relative path of the file.
By default, the value of the audit_cell_details parameter is set to

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SpyGlass area Rule Parameters

_null_.
You can specify the absolute or relative path of the file in the
audit_cell_details parameter. The file should contain information in
the following format:
<cell_type> <cell_type value1> <cell_blocktype
value2> <cell_blockgroup value3>
For example, a file may contain the following information, based on the
above format:
MEMORY_Cell storage primitive block
AMS_Cell analog primitive block
Eswitch_Cell routing primitive block
DRAM_Fuse_Cell storage hardmacro block
FuncIO_Cell interface primitive periphery
NonFuncIO_Cell routing primitive periphery
If you specify a file in the audit_cell_details parameter, all the cell
types and their related attribute combination from the file are read by the
GateCount rule.

The audit_cell_details parameter can be used only if the

report_all_cells parameter is set.
NOTE: To use this feature, customer must have the license feature, sgm.

Used by GateCount
Options Absolute or relative path of the file
Default value _null_
Example
Console/Tcl-based set_parameter audit_cell_details "a.txt"
usage
Usage in goal/source -audit_cell_details="a.txt"
files

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SpyGlass area Rule Parameters

blackbox
(Optional) Specifies the gate count of black box modules for the GateCount
rule.
Use the blackbox rule parameter as follows:
set_parameter blackbox <name>=<num>,[{<name>=<num>},]
Where, <name> is the name of the black box module and <num> is an
integer number.

Used by GateCount
Options Name and gate count of black box modules
Default value Empty string
Example
Console/Tcl-based set_parameter blackbox 'AN2=100'
usage
Usage in goal/source -blackbox='AN2=100'
files

greybox
(Optional) Specifies the name and gate count of grey box design unit for
the GateCount rule.
By default, this parameter is set to an empty string.
Set this parameter to a comma-separated list of pairs, with each pair
specifying the grey box name and its corresponding gate count.
Use the greybox rule parameter as follows:
set_parameter blackbox
'name1=num1,name2=num2,name3=num3,...',
Where, <name> is the name of the grey box design unit and <num> is an
integer number representing the gate count.

Used by GateCount
Options Name and gate count of grey box modules

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SpyGlass area Rule Parameters

Default value Empty string

Example
Console/Tcl-based set_parameter greybox 'AN1=100'
usage
Usage in goal/source -greybox='AN1=100'
files

proto_2_Nand
(Optional) Specifies the name of the NAND gate to be used by the
GateCount rule as reference for computing the area in terms of NAND2
equivalent gates.
By default, the name of the reference gate is assumed to be RTL_NAND2
(for originally RTL description that was synthesized by SpyGlass). For
originally structured netlists, the reference is the average of all NAND2
equivalents found in the technology library.
Use the proto_2_Nand rule parameter as follows:
set_parameter proto_2_Nand <name>
Where, <name> is the name of an NAND2 gate macro.

Used by GateCount
Options Name of the NAND gate
Default value RTL_NAND2
Example
Console/Tcl-based set_parameter proto_2_Nand RTL_NAND
usage
Usage in goal/source -proto_2_Nand=RTL_NAND
files

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SpyGlass area Rule Parameters

report_all_cells
(Optional) Extracts the information regarding some special cells, such as
memory cells, used in the design.
By default, the report_all_cells parameter is set to no.
If the report_all_cells parameter is set to yes then the GateCount
rule will not consider these cells for calculating the gate count of a module.
NOTE: To use this feature, customer must have the license feature, sgm.

Used by GateCount
Options yes, no
Default value no
Example
Console/Tcl-based set_parameter report_all_cells yes
usage
Usage in goal/source -report_all_cells=yes
files

rptallmodulegatecount
(Optional) Specifies whether the GateCount rule should report gate count of
all modules.
By default, the rptallmodulegatecount rule parameter is set to no
and the GateCount rule dumps the gate count of the top-level modules and
complete design in the vdb file.
Set the rptallmodulegatecount rule parameter to yes to dump the
gate count of all the modules in the vdb file.

Used by GateCount
Options yes, no
Default value no
Default Value in yes
GuideWare2.0

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SpyGlass area Rule Parameters

Example
Console/Tcl-based set_parameter rptallmodulegatecount yes
usage
Usage in goal/source -rptallmodulegatecount=yes
files

rtl_Nand_Area
(Optional) Specifies that prototype NAND2 cells will be used by the
GateCount rule for SpyGlass synthesized instances.

By default, the value of the rtl_Nand_Area rule parameter is set to

1.0.
You can set the value of rtl_Nand_Area rule parameter to any positive
integer value. If you do not specify this rule parameter then for the designs
synthesized internally by SpyGlass, RTL_NAND2 will be used.

Used by GateCount
Options Positive integer value
Default value 1.0
Example
Console/Tcl-based set_parameter rtl_Nand_Area 2.0
usage
Usage in goal/source -rtl_Nand_Area=2.0
files

size_*
(Optional) These rule parameters are used to specify the area of different
gate macros used in the design.
The GateCount rule calculates the size of each gate type based on the area
value in the associated library (specified by the read_file -type
gateslib <file> command in a project file, and/or the SpyGlass
default gates library). However, SpyGlass may create gate macros to

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SpyGlass area Rule Parameters

realize functionality with large number of inputs in order to create an

optimized netlist. For example, SpyGlass may create an 8-input AND gate
macro instead of using a cascade of 2-input AND gates. Then, the area of
these gate macros is calculated as follows:

Gate Macro Area Associated Synthesis Primitive

Rule
Parameter
N-input AND $size*0.5+0.5 size_And (RTL|INT)_AND,
M_RTL_AND_
N-input OR $size*0.5+0.5 size_Or (RTL|INT)_OR,
M_RTL_OR_
N-input XOR ($size-1)*1.5 size_Xor (RTL|INT)_XOR,M_RT
L_XOR_
MUX with N select $size+1 size_Mux (RTL|INT)_MUX
lines of which only
one is active at a
time and N inputs
LogN MUX with N $size+1 size_LogN_mu M_RTL_MUX_,M_RTL_S
select lines and x ELECT_BOX_,
2^N inputs
Decode operation, $size*2 size_Decoder M_RTL_DEC_
decoding from N
bits to 2^N bits
Unsigned full- $size*3 size_Add_uns M_RTL_ADD_UNS_
adder with 2 N-bit igned
inputs, plus carry-
in and N+1-bit
output plus carry-
out
Binary subtract (a- $size*3.5 size_Subtrac M_RTL_SUB_BIN
b) where a and b t_binary
are both N-bit
Unary subtract (- $size*2.5 size_Subtrac M_RTL_SUB_UNARY_
a) where a is N-bit t_unary
Incrementor (a+1) $size*2.5 size_Increme M_RTL_INCR_
where a is N-bit nt

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SpyGlass area Rule Parameters

Gate Macro Area Associated Synthesis Primitive

Rule
Parameter
Decrementor (a-1) $size*2.5 size_Decreme M_RTL_DECR_
where a is N-bit nt
Fixed-point $size*5 size_Multipl M_RTL_MULT_UNS_
multiplier (a*b) y_unsigned
where a and b are
both N-bit
unsigned integers
Fixed-point $size*5 size_Multipl M_RTL_MULT_SIGN_
multiplier (a*b) y_signed
where a and b are
both N-bit signed
integers
Unsigned fixed- $size*2.5 size_GT_unsi M_RTL_GT_UNS_
point greater-than gned
comparison (a>b)
where a and b are
both N-bit
unsigned integers
Signed fixed-point $size*4 size_GT_sign M_RTL_GT_SIGN
greater-than ed
comparison (a>b)
where a and b are
both N-bit signed
integers
Unsigned fixed- $size*2.5 size_GE_unsi M_RTL_GE_UNS
point greater- gned
than/equals
comparison
(a>=b) where a
and b are both N-
bit unsigned
integers
Signed fixed-point $size*4 size_GE_sign M_RTL_GE_SIGN
greater-than/ ed
equals comparison
(a>=b) where a
and b are both N-
bit signed integers

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SpyGlass area Rule Parameters

Gate Macro Area Associated Synthesis Primitive

Rule
Parameter
Unsigned fixed- ($size-1)*1.5 size_LEQ_uns M_RTL_LEQ_UNS_
point less-than/ igned
equals comparison
(a<=b) where a
and b are both N-
bit unsigned
integers
Signed fixed-point ($size-1)*1.5 size_LEQ_sig M_RTL_LEQ_SIGN_
less-than/equals ned
comparison
(a<=b) where a
and b are both N-
bit signed integers
Equality $size*1.75 size_Equal M_RTL_EQ_
comparison
(a==b) where a
and b are both N-
bit
Non-equality $size*1.75+0.5 size_Not_equ M_RTL_NEQ_
comparison (a!=b) al
where a and b are
both N-bit
Shift operation $size size_Shift M_RTL_LSHIFT_,M_RT
(a>>b or a<<b) L_RSHIFT_
where a and b are
both N-bit

NOTE: In the above table, $size is the number of inputs to a gate.

You can also override the automatically calculated area value for these gate
macros by using the associated rule parameter.

size_Buf
(Optional) Specifies the buffer size (two input NAND equivalents) to
consider.
By default, the value of the size_Buf parameter is set to 1.

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You can set the value of the size_Buf parameter to any positive real
value or zero.

Used by GateCount
Options <positive real value or zero>
Default value 1
Example
Console/Tcl-based set_parameter size_Buf 1.0
usage
Usage in goal/source -size_Buf=1.0
files

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Product Reports

Product Reports
The GateCount rule of the SpyGlass area product generates the following
two reports:

Report Name Description

diff This report compares the results of two SpyGlass
Analysis runs (one before modifications and the
second after modifications) to generate area-related
differences in the two runs.
GateCountReport This report contains module-wise gate count
information. In addition, this report contains the
information, such as area factor, prototype NAND
gate name, prototype NAND gate area, gate count,
and instance count of the complete design.

diff
The GateCount rule generates a report named diff that you can view in the
Atrenta Console GUI. The diff report compares the results of two SpyGlass
Analysis runs (one before modifications and the second after modifications)
to generate area-related differences in the two runs. The diff report has the
percentage change in the area estimate of each design unit with respect to
the current area estimate and its earlier area estimate of the complete
design. Therefore, you can ascertain the impact of your changes on the
area estimate of your design.
The procedure to generate the diff report in the batch mode is as follows:
1. Analyze your design by running a goal containing the GateCount rule.
This step creates a violation database file (say spyglass.vdb) in the
current working directory.
2. Rename spyglass.vdb to say first.vdb.
3. Modify the design as required.
4. Reanalyze your design with the GateCount rule, other commands as
required, and the following additional project file commands:
set_option report diff

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Product Reports

set_parameter diff_with first.vdb

This step creates another violation database file that is compared with
the violation database file of the earlier run (first.vdb). The diff.rpt file is
generated in the current working directory.

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Product Reports

The procedure to generate the diff report in the Atrenta Console GUI is as
follows:
1. Analyze your design in the Atrenta Console GUI by selecting the
GateCount rule and other settings as required.
This step creates a violation database file (say spyglass.vdb) in the
current working directory.
2. Rename the violation database file spyglass.vdb to say first.vdb.
3. Modify the design as required.
4. Reanalyze your design in the Atrenta Console GUI with the GateCount
rule and other settings as required.
5. Generate the diff report by selecting it from the Tools -> Report menu
option.
You are asked to enter the name of the original violation database file.
Enter or select the violation database file of the earlier run (first.vdb) and
click OK.
This step creates and displays the diff report.

GateCountReport
The GateCount rule generates a report named GateCountReport that
contains module-wise gate count information. In addition, this report
contains the information, such as area factor, prototype NAND gate name,
prototype NAND gate area, gate count, and instance count of the complete
design.
NOTE: You can also access the GateCountReport report at the consolidated_reports
directory.
A sample GateCountReport is as given below:
Area Factor: 1.000000
Prototype NAND Gate Name: RTL_NAND2
Prototype NAND Gate Area: 1.000000

Complete Design Gate Count: 35660

Complete Design Instance Count: 12942

Top Module Name: clcell

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Product Reports

Gate Count: 27
Instance Count: 26
==============================
S. No. Module Name Instance Count Gate Count
------------------------------------------------------
1. WORK_reorder_bits_15_4 16 16
2. WORK_reorder_bits_7_2 8 8
------------------------------------------------------

Top Module Name: srtop

Gate Count: 672
Instance Count: 112
==============================
S. No. Module Name Instance Count Gate Count
-----------------------------------------------------
1. WORK_sr_32 64 384
2. WORK_sr_8 16 96
-----------------------------------------------------

Top Module Name: bigmux

Gate Count: 154
Instance Count: 47
Module 'bigmux' has no RTL hierarchy, hence no module-wise
Gate Count report generated.
==============================

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Rules in SpyGlass area

Overview
The SpyGlass area product provides the following rules for checking the
area-related design issues:

Rule Description
GateCount Gate and instance counts for the complete hierarchy of
design
ResourceShar Sub-expressions in RTL that can be shared to minimize
e area

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Overview

GateCount
Reports gate and instance counts for the complete hierarchy of
design

When to Use
Use this rule to report the gate count of a design.

Description
The GateCount rule reports the total estimated number of gates and
instances in the whole design and in the individual modules or
architectures. The gate count is reported in terms of the number of
two-input NAND gates equivalent. This rule reports each gate or macro in
the design as one instance but reports its gate count depending on the size
of the gate or macro.
The following lists the gate count of different gates or macros:
1. For inverters, the gate count is less than 1.
2. For NAND2 and NOR2 gates, the gate count is 1.
3. For AND2 gates and flip-flops, the gate count is more than 1.
The GateCount rule uses the area of the NAND2 gate in a specific gate
library to calculate the area of other gates in the same library. If the
specific library does not have a NAND2 gate, this rule attempts to search
for a NAND2 gate in other specified gate libraries. This rule uses the
minimum-sized NAND2 gate found in these libraries. When a NAND2 gate
is not found, the area of other gates is calculated assuming the area of a
virtual NAND2 gate as 1.
Customizing the GateCount Rule
Input to the GateCount rule can be any one of the following design types:
 RTL design
 Netlist design + library
 Mixed (RTL + netlist) design + library
Depending upon the type of input, the GateCount rule can be customized.
To customize the rule behavior, refer to the Parameters section.

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Overview

Prerequisites
The GateCount rule uses the NAND2 gate with the minimum area to
calculate the gate count if more than one NAND2 gates are found in the
SpyGlass-compiled gates library specified with the read_file -type
sourcelist <file-name>.f command in a project file.

Parameters
 area_Factor: Default value is 1.0. Set this parameter to a double number
that specifies the area factor.
The area_Factor parameter is applicable for all design types (RTL,
netlist, and mixed). Use this parameter to map the gate count
calculated by the rule into another form of representation, such as
reporting physical area or transistor count. Apply this parameter on
complete module gate count, not on individual instance gate count.
If you want to report the transistor count, set the value of the
area_Factor parameter to 4. Similarly, if you want to report physical
area, specify the actual physical area of a NAND gate to the area_Factor
rule parameter.
 blackbox: Default value is an empty string. Set this parameter to a
comma-separated list of pairs, with each pair specifying the black box
name and its corresponding gate count.
 greybox: Default value is an empty string. Set this parameter to a
comma-separated list of pairs, with each pair specifying the grey box
name and its corresponding gate count.
 proto_2_Nand: Default value is RTL_NAND2. Set this parameter to name
of the NAND gate to be used as a reference for computing the area in
terms of NAND2 equivalent gates.
 size_*: Use this parameter to specify the area of gate macros used in the
design. The GateCount rule calculates the size of each gate type based
on the area value in the associated library (specified by using the
read_file -type gateslib <file> command in a project file,
and/or the SpyGlass default gates library).
 audit_cell_details: Default value is _null_. Set this parameter to
absolute or relative path of the file. This enables the GateCount rule to
read all the cell types and their related attribute combination from the
file.

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Overview

 report_all_cells: Default value is no. This indicates the rule extracts

information about some special cells, such as memory cells used in the
design. Set this parameter to yes if you do not want the rule to
consider these cells for calculating the gate count of a module.
 rptallmodulegatecount: Default value is no. This indicates the rule reports
the total estimated number of gates and instances for top design units
only. Set this parameter to yes to report the total estimated number of
gates and instances for all the modules in the design.
 rtl_Nand_Area: Default value is 1.0. Set this parameter to a positive
integer value to specify the usage of prototype NAND2 cells by the
GateCount rule for SpyGlass-synthesized instances.
The rtl_Nand_Area rule parameter is applicable to only RTL portion of
the design. Netlist generated by SpyGlass for RTL code is not optimized
as compared to the implementation tools used. Use this parameter to
fine-tune the gate count of RTL code to take care of the optimizations
being done by your implementation tool (or the richness of your
synthesis library).
The gate-level portion or the gate count for the design is not affected by
this parameter. This is because the netlist part is not expected to be
further optimized. Hence, with the help of this parameter, you can get
more accurate gate count of the complete design.
 size_Buf: Default value is 1. Set this parameter to a positive integer
value to specify the buffer size (two-input NAND equivalents).

Constraints
None

Messages and
Suggested Fix
Message 1
The following message appears for each top design unit <du-name> in the
design:
[INFO] <du-name> : GateCount : <num1> InstanceCount : <num2>
Where, <num1> is the estimated number of gates and <num2> is the
number of gate-level instances in the top design unit.

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Overview

Set the value of the rptallmodulegatecount parameter to yes to report the

estimated number of gates and number of gate-level instances for each
module in the design unit.
Potential Issues
None
Consequences of Not Fixing
None
How to Debug and Fix
For information on debugging, click How to Debug and Fix.
Message 2
The following message appears at the location where the black box design
unit <bb-name> (inferred as black box or specified with the blackbox rule
parameter) is first instantiated in the design:
[INFO] <bb-name> : GateCount : <num> InstanceCount : unknown
Where, <num> is the value of blackbox rule parameter, if specified for the
black box design unit, or unknown.
Potential Issues
None
Consequences of Not Fixing
None
How to Debug and Fix
For information on debugging, click How to Debug and Fix.
Message 3
The following message appears for the complete design:
[INFO] Complete Design : GateCount : <num1> InstanceCount :
<num2>
Where, <num1> is the estimated number of gates and <num2> is the
number of gate-level instances in the design.
For more information on debugging, click How to Debug and Fix.
Potential Issues

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Overview

None

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Overview

Consequences of Not Fixing

None
How to Debug and Fix
Double-click the violation message. The HDL Viewer window highlights the
line for any top design unit for which gate count and instance count are
calculated.

Example Code
and/or Schematic
Example 1
Consider the following VHDL example:
entity top is
port (in1, in2 : inout integer; out1 : out integer);
end entity;

architecture rtl1 of top is

begin
out1 <= in1 + in2;
end rtl1;
The architecture rtl1 has an addition operation and assignment involving
integer ports in1, in2, and out1. This statement is equivalent to 1
macro adder. As multi-bit adders have a gate count of 3 for each bit, the
statement is counted as 96 gates and 1 instance.
Example 2
Consider the following VHDL example:
entity top is
port (in1, in2 : inout integer; out1 : out integer);
end entity;

architecture rtl1 of top is

begin
out1 <= in1;
end rtl1;
The architecture rtl1 has a direct assignment statement involving integer

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Rules in SpyGlass area

Overview

ports in1 and out1. This statement is equivalent to 32 individual buffers,

one for each bit. As buffers have a gate count of 1, the statement is
counted as 32 gates and 32 instances.
Example 3
Consider the following example that reports the gate count for modules,
m1 and m2:
module m1(z, a);

input a;
output z;
assign z = ~a;
endmodule

module m2(z, a, b);

input a, b;
output z;
assign z = a & b;
endmodule

Default Severity
Label
Info

Rule Group
None

Reports and
Related Files
diff, GateCountReport

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Rules in SpyGlass area

Overview

ResourceShare
Reports sub-expressions in RTL that can be shared to minimize
area

Rule Description
The ResourceShare rule reports sharable sub-expressions in the design.
While the RTL description may have many candidates of sharable
sub-expressions, some of them are optimized out during synthesis. The
ResourceShare rule attempts to locate remaining sharable resources in a
flattened netlist.

Message Details
The following message appears at a location where a sharable sub-
expression <expr> is found in the design:
Expression <expr> can be shared: ({File: <file-name> Line:
<num> , })
For every other occurrence of the sharable sub-expression <expr>, the
message provides the source file name <file-name> and the line
number <num>.

Rule Severity
Information

Examples
Consider the following Verilog example:
1: // file : tests.v
2: module top (in1, in2, out1, out2);
3: input [31:0] in1, in2;
4: output [31:0] out1, out2;
5:
6: assign out1 = in1 + in2;
7: assign out2 = in1 + in2;
8: endmodule
SpyGlass finds a sharable sub-expression — (in1 + in2) and generates

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Rules in SpyGlass area

Overview

the following message at line number 7:

Expression (in1 + in2) can be shared: (File: tests.v Line: 6 )
Please note that the file name and line number in the message refers to
another occurrence of the sharable resource than the occurrence where the
message is flagged.

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List of Topics

List of Topics
About This Book ............................................................................................. 7
area_Factor ................................................................................................. 13
audit_cell_details ......................................................................................... 13
blackbox ..................................................................................................... 15
Contents of This Book ..................................................................................... 8
diff ............................................................................................................. 23
GateCountReport.......................................................................................... 25
greybox ...................................................................................................... 15
Overview..................................................................................................... 27
Product Reports ........................................................................................... 23
proto_2_Nand.............................................................................................. 16
report_all_cells ............................................................................................ 17
rptallmodulegatecount .................................................................................. 17
rtl_Nand_Area ............................................................................................. 18
Running the SpyGlass area Product................................................................. 12
size_*......................................................................................................... 18
size_Buf ...................................................................................................... 21
SpyGlass area Rule Parameters ...................................................................... 13
Typographical Conventions .............................................................................. 9

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List of Topics

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