Filtronic

Solid State
Applications Notes
Discrete FET / PHEMT Devices
Revision A
August 1996
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 2
INTRODUCTION
These applications notes describe Filtronic Solid State (FSS) discrete FET /
PHEMT devices and typical applications, effective August 1, 1996. Although every effort
has been made to ensure the accuracy of this information (contained in these
Applications Notes and the associated Datasheets), FSS assumes no responsibility for
errors, omissions, or future specifications changes. Every reasonable effort will be made
to provide updated or corrected applications information or specification changes to all
concerned users.
Filtronic Solid State discrete FET / PHEMT devices are generally sold by
description only. RF specifications, in particular, are based on samples of devices from
individual semiconductor wafers or fabrication lots (groups of 6-10 wafers). All
semiconductor die are 100% DC tested, based on specific test conditions and methods
as described herein. Test methods are based on MIL-STD-750, with modifications where
necessary. Unless otherwise indicated, all specifications listed as minimum or as
maximum are guaranteed at the temperatures indicated (nominally at 22C) and under
the conditions listed. Typical specifications are based on average values, intended to
reflect the majority of actual devices manufactured, but are not guaranteed.
Filtronic Solid State assumes no responsibility for performance or reliability of its
discrete devices when operated outside the recommended electrical or environmental
limits, or if operated in such a way as to exceed the Absolute Maximum Ratings as
indicated on specific Datasheets. Applications information is intended as general
guidance only, and FSS is not responsible for user-provided circuitry.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 3
TABLE OF CONTENTS
Section Page
1.Introduction.........................................................................................................................2
2.Quick Reference Guide......................................................................................................4
3.Cross-Reference Guide .....................................................................................................5
4.General Device Description................................................................................................6
5.PHEMT Device Physics .....................................................................................................8
6.PHEMT Characteristics......................................................................................................11
7.Small-Signal S-Parameters and Lumped Element Models................................................20
8.Biasing Circuits and Stabilization Techniques....................................................................23
9.Large-Signal Models and Optimum Power Match Data.....................................................26
10.Example Circuits ..............................................................................................................29
11.Recommended Assembly Techniques.............................................................................39
12.Parametric Screening and Quality Assurance..................................................................40
13.Discrete Device Uniformity...............................................................................................46
14.Device Reliability ..............................................................................................................48
15.Appendix A.......................................................................................................................49
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 4
2. Quick Reference Guide
Discrete GaAs MESFET and PHEMT Product Family
MODEL STATUS
FREQ.
RANGE
(GHz)
GAIN
(dB)
POWER
(dBm)
NOISE
FIGURE
(dB)
V
DS
(V)
I
DSS
(mA)
PAE
(%)
CHIP
DIM.
(m)
GATE
W/L
(m)
TYPE
LF 3807 (1) 1 - 12 7 24 --- 7 200 40 430x460 700/.5 MES
LF 3814 STD 1 - 12 6 27 --- 7 400 40 430x460 1400/.5 MES
LF 3830 STD 1 - 8 7 31.5 --- 9 700 36 340x930 3000/.5 MES
LF 3850 STD 1 - 8 7 33.5 --- 9 1100 38 380x900 5000/.5 MES
LF 6828 STD 1 - 18 7 19 --- 5.5 80 26 310x440 280/.5 MES
LF 6836 STD 1 - 18 6.5 21 --- 5.5 120 27 330x350 360/.5 MES
LF 6872 STD 1 - 18 6 24 --- 5.5 230 26 370x500 720/.5 MES
LP 7512 STD 1 - 40 8.5
2
--- 1.0 2 35 --- 330x460 200/.25 SHP
LP 7612 STD 1 - 40 9.5
3
21 1.1
4
5 55 50 330x460 200/.25 DHP
LP 6836 PRT 1 - 30 9.5
3
24 --- 8 100 45 330x350 360/.25 DHP
LP 6872 STD 1 - 26 9.5
3
27 --- 8 220 45 370x500 720/.25 DHP
LP 1500 ED
5
1 - 20 9.0
3
30.5 --- 8 465 48 340x800 1500/.25 DHP
LP 1800 ED
5
1 - 20 9.0
3
31.0 --- 8 560 48 340x820 1800/.25 DHP
LP 3000 ED
5
1 - 20 8.5
3
33.5 --- 8 930 45 340x850 3000/.25 DHP
LP 5000 ED
5
1 - 20 8.5
3
36.0 --- 8 1550 45 340x860 5000/.25 DHP
LEGEND:
STD STANDARD PRODUCT
OBS OBSOLETE; MODEL DISCONTINUED.
PRT PROTOTYPE; APPLICATION DEVELOPMENT SAMPLES AVAILABLE
ED ENGINEERING DEVELOPMENT; PROTOTYPE DEVICES AVAILABLE AS INDICATED
MES Standard GaAs MESFET
SHP SINGLE HETEROJUNCTION PHEMT
DHP DOUBLE HETEROJUNCTION PHEMT
NOTES:
1). LF 3807 to be discontinued 10/96. One-half of the LF 3814 can be used as a replacement.
2). Associated Gain at Optimum Noise Figure, measured at 18 GHz.
3). Power Gain at 1dB Gain Compression, device tuned for optimum power at 18 GHz.
4). Low-noise bias, measured at 18 GHz.
5). Prototype devices available 10/96.
FREQ. RANGE is the recommended range based on the devices available gain.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 5
3. Cross-Reference Guide
This guide is based on general performance parameters; optimum circuit performance may require re-design, since the FSS device S-parameters may
differ significantly from other manufacturers devices as listed below. Contact the Foundry for additional information.
NEC
NE24200, 32400 LP 7512 NE24200, 67300 LP 7612, 7512
HI-REL
NE710000
NE720000
NE760000
NE761000
LP 7612 NE800100
NE800200
NE800400
LF 3814
LF 3830
LF 3850
NE900000
NE900100
NE900200
NE900400
LP 7612
LP 6836
LP 6872
LP 1800
MWT (Microwave Technology)
MWT-1, A1
MWT-2
MWT-3, A3
MWT-4
MWT-6
MWT-7, A7, S7
MWT-8, A8
MWT-9, A9
LP 7612
LP 6836
LP 7612
LP 7612
LP 6872, LF 3814
LP 7612
LP 1500, LP 6872
LP 6872
MWT-10
MWT-11, A11
MWT-12
MWT-13
MWT-14
MWT-15
MWT-16
LP 7512
LP 1500
LP 6872, LF 3814
LP 6872, LF 3814
LF 3850
LP 6836, LP 6872
LP 6872
FUJITSU
FHX04X - FHX06X
FHR02X, FHR10X
FSC10X, FSC11X
FSX02X, FSX03X
FSX51X, FSX52X
LP 7512 FSC11X
FSC51X
LF 6828
FSX52X LP 6836 FLX252XV LP 3000
FLC081XP
FLC151XP
FLC301XP
LP 6872, LF 3830
LP 1800, LF 3850
LP 5000
FLK012XP
FLK022XP/XV
FLK052XP/XV
FLK102XP/XV
FLK202XV
LP 7612
LP 6836
LP 6872
LP 1500
LP 3000
FLR024XP/XV
FLR054XV
FLR104XV
LP 6836
LP 6872
LP 1500
FLR016XP/XV
FLR026XP/XV
FLR056XV
LP 7612
LP 6836
LP 6872
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 6
4. GENERAL DEVICE DESCRIPTION
Filtronic Solid State offers discrete devices that
can be classified into three categories: GaAs MESFETs,
Single Heterojunction Pseudomorphic High Electron
Mobility Transistors (SH-PHEMTs), and Double
Heterojunction Pseudomorphic High Electron Mobility
Transistors (DH-PHEMTs). The latter two device types
feature AlGaAs/InGaAs heterojunctions, with GaAs
buffer and cap layers. Notional cross-sections are
shown below:
AuGe / Ni / Au Alloyed Contacts
N+ GaAs Active Layer
N- Buffer Layer
Drain
Contact
Source
Contact
Ti / Pt / Au Recessed Gate
N++ Contact Layer
AlGaAs / GaAs Superlattice
Undoped GaAs Buffer
InGaAs Channel Layer
N+ AlGaAs Layer (5 x 10
17
cm
-3
)
N++ GaAs Contact Layer
Drain
Contact
Source
Contact
Ti / Pt / Au Mushroom Gate
GaAs MESFET STRUCTURE
PHEMT STRUCTURE
Undoped AlGaAs Spacer
Heterojunction
X
Y
Z
Both major device types, the MESFET and the
PHEMT, share several common features, beginning with
the gate structure. This is a standard Pt / Ti / Au layered
structure, which forms a Schottky contact to the
semiconductor; general properties of this type of contact
can be found in numerous references, such as in Sze
1
.
The nominal gate length for FSSs MESFET is 0.5 m,
and 0.25 m for the PHEMT devices. Gate definition is
accomplished by Electron-Beam direct-write techniques,
using a Cambridge E-Beam system; all other patterning
is done with standard contact photolithography
techniques. In both device types, a gate recess channel
is etched into the semiconductor prior to gate
metallization, to reduce parasitic gate-source resistance,
as well as optimizing the devices reverse breakdown
voltage. Note that the gate and gate recess channel are
also offset towards the source contact. The MESFET
gate structure is trapezoidal in cross-section, being
somewhat wider at the bottom than at the top. The
PHEMT gates are mushroom structures, thereby
reducing gate metal resistance that would result from the
narrower 0.25 m base.
Drain and source contacts are alloyed
AuGe/Ni/Au contacts, with overplated Au for bond pads.
The Ge in the contact metal is driven into semiconductor
during the alloy process, where it acts as an amphoteric
dopant, thereby reducing the contact barrier height and
forming the ohmic contact itself. The AuGe/Ni/Au has
been established as a very stable and robust contact
structure. All discrete devices are passivated with silicon
nitride (Si
3
N
4
), which doubles as scratch protection.
Nominal die thickness is 100 m, or 75 m for
power devices ( 1W). The larger power devices
generally include plated via-holes through the die to
minimize parasitic source inductance. The vias are
defined by Reactive Ion Etching (RIE) techniques, a
method also employed on FSSs MMIC products.
All semiconductor structures are grown by
Molecular Beam Epitaxy (MBE), which provides
compositional control to a precision of a few atomic
monolayers, and very stable and repeatable doping level
control. FSS has utilized MBE technology for a wide
variety of device structures for more than 15 years.
Basic material parameters are routinely characterized,
such as: doping level, carrier mobility (both at room
temperature and at 77K), sheet charge density (for
PHEMT devices), and wafer uniformity.
1. S. M. Sze, Physics of Semiconductor Devices, Wiley,
New York, 1981, pp. 245-297.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 8
5. PHEMT DEVICE PHYSICS
The basic High Electron Mobility Transistor
(HEMT) structure is described in many references, and a
review of this devices salient features is included here
for completeness. Sze
1
provides a basic introduction to
heterojunction energy band structures, and a very
complete review of HEMT technology can be found in
Transactions on Electron Devices.
2
Consideration of the basic lumped element
intrinsic MESFET model (see Sec. 7 and Liechti
3
) and its
connection to the underlying device structure shows that
there are several factors that ultimately limit high-
frequency response. The unilateral gain is given by:
G
f
f
U

max
2
2
where G
U
= unilateral gain, f = frequency, and f
max
= the
maximum frequency of oscillation. The gain decreases
at 6 dB/octave until f = f
max
, where the unilateral gain
becomes unity. This f
max
is approximately given by:
f
f
r f
T
io T DG
max

+ 2
where r
io
= input-to-output resistance ratio,
DG
=
2R
G
C
DG
, the drain-to-gate RC time constant, and f
T
=
the unity current gain, defined as:
f
g
C
T
m
GS

1
2
where g
m
= intrinsic device transconductance, and C
GS
=
gate-source capacitance. The frequency f
T
is defined as
that frequency at which the current through C
GS
(i
C
=
2f C
GS
V
C
) is equal to the that produced by the current
generator (i
G
= g
m
V
C
, where V
C
is the voltage
developed across the capacitor C
GS
). At frequencies
above f
T
, the current through C
GS
is greater than that
provided by the current generator, and thus f
T
represents
a fundamental high-frequency limit. Combining
expressions for the transconductance and the gate-
source capacitance:
C
Z L
h
g
v Z
h
GS
S G
m
sat S


where
S
= semiconductor dielectric constant, Z = gate
width, L
G
= gate length, v
sat
= saturated carrier velocity,
and h = depletion layer depth. The result becomes:
f
v
L
T
sat
G

2
Fundamentally the high-frequency performance
is optimized by reduction of the devices gate length,
along with maximizing the saturated carrier velocity. In
addition, the extrinsic resistances R
G
and R
S
must be
minimized, as well as feedback elements such as C
DG
.
While gate length is limited by the
photolithography technology, the carrier velocity can be
enhanced by use of alternative materials, i.e., GaAs
instead of Si, or by use of a two-dimensional electron gas
(2DEG) transistor. This latter device incorporates a
heterojunction, which is a junction of two different
semiconductors. One particular heterojunction of
interest in this case is a Al
0.3
Ga
0.7
As/GaAs N+/P-
combination, which results in a energy band diagram as
show:
Gate Metal N+ Doped AlGaAs Undoped P- GaAs
Undoped
AlGaAs
Spacer
Fermi
Level
Heterojunction
2-D Electron Gas
Conduction
Band
X
Y
Z
HEMT ENERGY BAND DIAGRAM
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 9
Since the Al
0.3
Ga
0.7
As and GaAs have different
bandgap energies, their conduction band levels will not
line up, resulting in a discontinuity as shown. A thin
electron inversion layer is formed on the GaAs side of
the heterojunction, populated by carriers that have
crossed over from the doped Al
0.3
Ga
0.7
As side; a very
thin spacer layer further separates the electron layer
from effect of ionized dopant impurities. This electron
inversion layer has been termed a two-dimensional
electron gas since there may be, under certain
conditions, quantization of the allowed energy levels.
Fairly accurate prediction of the inversion layer sheet
charge density results from the appropriate quantum
mechanical treatment. Also note that, by design, the
Al
0.3
Ga
0.7
As layer thickness and doping level are chosen
to ensure that, at zero applied gate bias, this layer is fully
depleted of mobile carriers. Therefore the only mobile
charge carriers reside in the 2D electron gas layer.
The structure is designed to achieve a 2D
electron gas sheet charge density that is as high as
possible, typically 1.0-2.5 x 10
12
cm
-2
, since this
determines the I
DSS
per unit gate width for the device.
Application of a bias voltage to the drain terminal, with
the source grounded, causes current flow in the X-axis
direction. Control of the 2D electron layer is by
application of the gate voltage, since the sheet charge
density is directly related to the electric field applied
across the heterojunction.
This heterostructure, used in place of standard
MESFET structure, came to be known by various names,
e.g., MODFET, TEGFET, and HEMT, for High Electron
Mobility Transistor. An approximate expression for the
transconductance is given by:
g
Z v
d d
m
S sat

where d + d = total Al
0.3
Ga
0.7
As layer thickness
(including spacer). While this has the same functional
form as with the MESFET, higher g
m
is achieved at
much lower values of drain voltage, since the greater
mobility in the undoped GaAs results in lower knee
voltages (i.e., the onset of velocity saturation). In
addition, the layer thickness is substantially less than a
MESFETs depletion layer thickness. The goal with
HEMT design is to optimize the heterostructure in order
to maximize low-field carrier mobility, saturation velocity,
extrinsic transconductance, and to minimize the input
capacitance C
GS
.
The Pseudomorphic HEMT structure utilizes a
different combination of semiconductors, as shown in the
figure below:
Gate Metal N+ Doped AlGaAs Undoped P- GaAs
Undoped
AlGaAs
Spacer
2-D Electron Gas
Undoped InGaAs
PSEUDOMORPHIC HEMT
ENERGY BAND DIAGRAM
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 10
This structure features a AlGaAs/InGaAs
heterojunction, rather than the AlGaAs/GaAs
combination used for the HEMT device. The relative
compositional ratio of gallium and indium is varied to
establish the desired conduction band discontinuity, but
there are material-related limits that must be considered.
One important factor is that AlGaAs and InGaAs are not
lattice-matched, i.e., the interatomic lattice spacing is
different. Thus a grown heterojunction using this
combination will contain a certain amount of strain, which
ultimately limits the thickness of the InGaAs layer.
Because the two semiconductors are not lattice-
matched, the structure is referred to as a
pseudomorphic HEMT device.
The use of InGaAs provides for even higher
mobility and saturated carrier velocity, along with
improved 2-D electron gas confinement; in addition, by
suitable modification of the basic PHEMT structure, the
second heterojunction can be utilized for an addition 2-D
electron gas layer parallel to the first. Typically this is
done by using another AlGaAs layer below the InGaAs
channel layer. FSSs PHEMT technology features both
types of PHEMT structures, as mentioned earlier; the
DH-PHEMT structure gives much larger I
DSS
per unit
gate width, and therefore much improved power density.
The various device structures and their materials-related
performance parameters are summarized in the
Materials-Related Performance Parameters Table below.
Note first the improvement in low-field mobility
resulting from the use of a 2-D electron gas in the HEMT
and PHEMT devices; there are also dramatic increases
in extrinsic transconductance and high-frequency
performance as well. The last two entries represent
typical FSS performance from the SH- and DH-PHEMT
structures. Also note the substantial improvement in
effective carrier velocity resulting from the use of InGaAs
vs. GaAs, which directly translates into higher cut-off
frequency f
T
.
References:
1). S. M. Sze, op. cit., pp. 122-129.
2). Morkoc, H. and Abe, M., ed., Special Issue on
Heterojunction Field-Effect Transistors, IEEE Trans.
Elec. Devices, Vol. ED-33, No. 5, May 1986.
3). Liechti, C. A., Microwave Field-Effect Transistors -
1976, IEEE Trans. Microwave Theory and Tech., Vol.
MTT-24, No. 6, June 1976, pp. 279-300.
SUMMARY OF MATERIALS-RELATED PERFORMANCE PARAMETERS
DEVICE TYPE
LG
(m)
HALL MOBILITY
(cm
2
/V)
vsat
(cm/s)
IDSS
(mA/mm)
gm
(mS/mm)
fT
(GHz)
fmax
(GHz)
GaAs MESFET 0.50 3000 6.9 x 10
6
170 250 22 45
HEMT 0.65 6000 N/A 120 280 N/A N/A
HEMT 0.25 6000 6.3 x 10
6
220 320 40 80
PHEMT 1.00 7000 11.0 x 10
6
290 310 15 N/A
SH-PHEMT 0.25 7000 7.8 x 10
6
220 450 55 105
DH-PHEMT 0.25 5000 7.8 x 10
6
325 450 50 100
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 11
6. PHEMT CHARACTERISTICS
Current-Voltage (I-V) Characteristics
Based on the material presented in Section 5, it
is clear that the fundamental charge transport and
current control mechanisms in the PHEMT device differs
significantly from the classical GaAs MESFET, and while
there are many similarities between the devices
extrinsically, there are also several important differences.
The first of these lies in the basic I-V curves, and in the
derived transconductance (G
M
) and Drain-Source current
(I
DS
) vs. Gate voltage characteristics. Typical examples
of these are given below for the LP 7612 device, which is
a 0.25 x 200 m discrete DHPHEMT. Note the low
knee voltage, at about V
DS
= 0.5V, representing the
transition from the linear to the saturated region. One of
the most striking aspects is the large value of Drain-
Source current attained with positive gate bias; for the
DHPHEMT device, this maximum Drain-Source current,
denoted I
DSSM
, can be as much as 75 to 100% above
I
DSS
. In contrast, the MESFET might show 20-25% more
current under the same forward gate bias. With both
devices, the amount of forward gate bias that can be
applied is limited to +0.7 to +0.8V, since larger values will
drive the Gate into forward conduction. This PHEMT
phenomenon has a number of implications for circuit
designers.
The transconductance vs. V
GS
curve shows a
pronounced peak at about 80% of V
P
, the pinchoff
voltage, where the current is effectively reduced to zero.
The maximum extrinsic G
m
value is approximately 385
mS/mm, corresponding to an intrinsic transconductance
of about 500 mS/mm. For optimum small-signal gain, an
operating point of 70-80% of I
DSS
is recommended.
Because the devices I-V curves show symmetry
about the V
GS
= 0V curve (i.e., I
DSS
), the standard
guidelines for Class A, AB, and C operation are different
than for the MESFET. It is generally accepted that for
true Class A operation, i.e., no distortion of the amplified
signal, a quiescent operating point of I
DS
= 50% I
DSS
is
the correct choice. This is based on consideration of the
MESFETs I-V curves and the derived G
M
vs. gate
voltage characteristic. Notional examples of these are
shown on the following page.
TYPICAL PHEMT I-V CHARACTERISTICS I
DS
AND G
M
VS. GATE VOLTAGE
LP7612 LP7612
DRAIN VOLTAGE (V) GATE VOLTAGE (V)
D
R
A
I
N

C
U
R
R
E
N
T

(
m
A
)
D
R
A
I
N

C
U
R
R
E
N
T

(
m
A
)
Gate Voltage
Start .8V
Stop -1.2
Step -.2 V
G
M

(
m
S
)
150
120
90
60
30
0
150
120
90
60
30
0
150
120
90
60
30
0
0 1.2 2.4 3.6 4.8 6
.8 .4 0 -.4 -.8 -1.2
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 12
Class A operation requires, in the ideal case, a
distortionless amplification of the input signal, and for a
sinusoidal waveform, this also requires that no harmonic
signals are generated. The standard for the measure of
maximum linear power is the output power at 1 dB of
gain compression (i.e., 1 dB below the small-signal gain),
denoted P
1dB
. In the case of the notional MESFET I-V
curves given above, once the input signal drives the
dynamic operating point into the gate-drain breakdown
region (located in the lower right-hand corner), signal
distortion can be expected. The load-line shown above is
established by the output matching circuit, which must
also resonate out the devices output admittance. For
maximum output power, the load-line must be chosen to
maximize the peak-to-peak voltage and current
amplitudes, since:
P V I
RF P P P P

1
8
In addition, biasing the device at less than 50% of I
DSS
can cause clipping of the output current waveform as the
FET is driven beyond pinchoff (i.e., V
GS
> V
P
, the pinch-
off voltage). Examination of the transconductance vs.
gate voltage characteristic also shows that the region of
constant G
M
is limited. For optimum linearity, MESFETs
are biased at 50% of I
DSS
, and for larger small-signal
gain, bias values of 60-75% are used. Higher power-
added efficiency can be achieved at operating points less
than 50% of I
DSS
, but with degraded linearity.
Because the PHEMT I-V curves show that I
DSSM
is 150-175% of I
DSS
, it can be anticipated that for Class A
operation, a quiescent bias point (QP) of 55-75% of I
DSS
is the correct choice. This bias point allows for a large
current swing while avoiding current cut-off and its
associated generation of harmonics. The selection of
the quiescent Drain voltage then becomes a compromise
between allowing for the largest voltage swing, while
avoiding the Gate-Drain breakdown region.
IDSSM
IDSS
50%
QP
VGS = +0.5V
VGS = 0V
VGS = -VP
V
DS
I
DS
INPUT SIGNAL
APPLIED TO GATE
OUTPUT CURRENT
DELIVERED TO LOAD
V
GS 0.0
G
M
NOTIONAL MESFET
I-V CURVES
MESFET TRANSCONDUCTANCE
CHARACTERISTIC
GATE-TO-DRAIN
BREAKDOWN
REGION
LOAD-LINE
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 13
Power Linearity and
Intermodulation Distortion (IMD)
Because the PHEMT transconductance vs. gate
voltage characteristic shows a peak at 70-80% of I
DSS
, as
opposed to a relatively broad plateau of nearly constant
G
M
, it is reasonable to suspect that the inherent linearity
of the PHEMT is less than that of the MESFET. As is
shown below, however, with a proper choice of the
quiescent operating point, the PHEMT linearity and
Intermodulation Distortion (IMD) performance is
exceptionally good. Regardless of what measure is used
to assess the fundamental linearity, the PHEMT meets or
exceeds the classical power transfer model.
It is useful to review the classical theory of
nonlinearity in memoryless systems,
1
before presenting
actual device data. A truly distortion-free two-port
system will accept any input signal and produce a output
signal that is a scaled version of the input, with only a
linear phase shift. This means that the system transfer
function H(j) is given by:
( ) ( )
H j K j t
o
exp
where K and t
o
are constants. For practical two-port
systems with amplification, some non-linearity is of
course inherent, but if the deviation from ideal linearity is
mild, the two-port can be represented by a power series
expansion of the input voltage, as follows:
e k e k e k e
with e A t
o i i i
i
+ +

1 2
2
3
3
1
cos
where e
i
= input signal, e
o
= output signal, A = input
signal amplitude,
1
= signal frequency, and k
1,2,3
=
expansion series coefficients. Expanding the power
series and combining like terms, the output signal
consists of a DC component, and components at the
fundamental, 2nd, and 3rd harmonic frequency. The
fundamental component has an amplitude which is,
expressed in log units:
G k k A dBm +

_
,

20
3
4
1 3
2
log
where G = power gain. This is compared to the linear
power gain:
G k dBm
o
20
1
log
where G
o
= linear or small-signal power gain. Note that if
k
3
> 0, gain expansion occurs, while if k
3
< 0, then the
two-port exhibits gain compression.
If one now applies a second fundamental
frequency or tone, the simultaneous two-tone input
produces output signal components at: DC,
1
,
2
, 2
1
,
2
2
, and 3
1
, 3
2
; there will also now be
intermodulation products, i.e., second-order products at

1

2
, and third-order products at: 2
1

2
and 2
2

1
. The third-order products are of particular concern,
since they fall within the passband of a typical single-
octave system, whereas the other terms do not. In a
system with impedance R, the output power of the
fundamental in the linear region of the power transfer
characteristic will be, in dBm units:
P
R
dBm
o

_
,

'

10
2
10
1
2
3
log
k A
Once the two-port begins deviating from linearity, the
term k
1
A is replaced by: k A k A
1
9
4
3
3
+ . For all
practical purposes, the two-port can be considered
essentially linear if operated more than 10 dB below the
1 dB compression point. The power of the 3rd-order
intermodulation products is given by:
P
k A
R
dBm
2
3
4
3
3
2
3
1 2
10
2
10

_
,

'

log
Note that the slope of the 3rd-order products increases
at a 3:1 ratio compared to the linear power expression.
Thus if the linear output power is extrapolated, it will
intersect the 3rd-order product extrapolation, as a
function of input power. This intersection point, the 3rd-
order intermodulation intercept point, is useful for
characterizing non-linear systems. This behavior is
depicted in the figure below, along with an idealized two-
tone IMD spectrum.
1. Ha, Tri T., Solid-State Microwave Amplifier Design,
Wiley, New York, 1981, pp. 203-209.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 14
Using the relationships given above and solving
analytically for the intercept point yields the expression:
P
k
k R
dBm
IP

_
,

'

10
2
3
10
1
3
3
3
log
Thus the intercept point in this example is independent of
input power, and from this one also derives the well-
known expression:
P P dBm
IP dB
+
1
10 63 .
Another often-used expression relates the 3rd-order IMD
product power levels to the fundamental power level, as
follows:
P P P dBm
IP 2
1 2 1
3 2


3
1
1
1
Input Power (dBm)
Output
Power
(dBm)
P
IP
3rd-order products
fundamental
FUNDAMENTAL AND 3RD-ORDER IMD PRODUCT
POWER TRANSFER CURVES

1

2
2
2
-
1
2
1
-
2

1

2

INPUT SPECTRUM OUTPUT SPECTRUM

Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 15
Typical two-tone IMD performance data is
presented below for the LP 7612 and LP 6872 discrete
DHPHEMT devices, illustrating the effect of the
quiescent OP. This effect is especially pronounced for
the LP 7612, showing quite clearly that the operating
current needs to be greater than 50% of I
DSS
in order to
show zero gain expansion and optimum IMD
performance. The power linearity was assessed by four
methods:
1). Examination of the power transfer curve;
qualitatively, the presence or absence of gain expansion.
2). Curve-fitting the P
IN
vs. P
OUT
data to the
classical theory.
3). Intercept Point determination by graphical
extrapolation.
4). Intercept Point determination by direct
calculation, using:
P P P dBm
IP 2
1 2 1
3 2


The devices were characterized using the test equipment
configuration shown below.
Low-loss triple-sleeve coaxial tuners match the
DUT to 50 ohms, which are manually tuned for optimum
power and/or gain. The discrete device is eutectically
die-attached onto a gold-plated copper
groundbar/heatsink, which in turn is mounted between a
pair of 50 ohm microstrip lines (on alumina). Bond wires
connect the DUTs Gate and Drain to the microstrip lines.
Coaxial-to-microstrip launchers complete the
measurement fixturing. The TWT amplifier is operated
more than 25 dB below its 1dB compression point, and
does not contribute intermodulation products. Input and
output losses are corrected up to the coaxial-to-
microstrip adapters.
SIGNAL
GENERATORS
TWTA
TUNER
BIAS
TEE
POWER
METER
SENSOR
-VG
DUT
TUNER
+VD
POWER
METER
SENSOR
SPECTRUM
ANALYZER
TEST CONFIGURATION FOR TWO-TONE
INTERMODULATION MEASUREMENTS
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 16
LP 7612 5V 75% IDSS
-30
-20
-10
0
10
20
30
40
3.3 4.3 4.8 6 6.9 8.1 8.5 9.7 10.7 11.7 12.9 14 14.5 15.7 16.6 17.6 18.6 19.6 20.6 21.6 22.6 23.6
INPUT POWER (dBm)
POUT 1-TONE
POUT EXT
GP
P3rd EXT
P3rd ABS
PINT CALC
This data was taken on a LP 7612 DHPHEMT
discrete device, as described above, biased at V
DS
= 5V,
I
DS
= 75% I
DSS
. The actual data, corrected to a single-
tone basis, is shown as the POUT 1-TONE and P3rd
ABS. The first is the fundamental tone P
OUT
vs. P
IN
data, while the second is the actual (absolute) power
level of the 3rd-order IMD products. Note that the actual
3rd-order data follows the expected 3:1 slope line, whose
intersection with the linear extrapolation of the small-
signal power gain shows a 3rd-order Intercept Point of
+35 dBm. The single-tone output power at 1 dB gain
compression, P
1dB
= +21.5 dBm, with a Power-Added
Efficiency PAE = 47%. Thus the device exceeds the
expected: P
1dB
+ 10.6 dB = +32.1 dBm, and the PAE is
consistent with Class A operation. The calculated Power
Gain is shown as GP on the plot above, showing no
gain expansion or other nonideal behavior prior to
compression. Also shown as PINT CALC are the
values calculated from: P P P
IP 2
1 2 1
3 2

,
showing constant IP3 values in the linear region, and
reasonably good agreement with the graphical
determination. Finally, the P
OUT
vs. P
IN
data fits well to
the power transfer model, with k
1
= 3.89, and k
3
= -0.422.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 17
LP 7612 5V 50% IDSS
-30
-20
-10
0
10
20
30
40
-0.3 0.8 1.8 2.9 3.6 4.5 5.4 6 7 8.1 9.1 9.7 10.7 11.8 12.9 13.7 14.6 15.2 16.2 17.2 18.2 19.2
INPUT POWER (dBm)
POUT 1-TONE
POUT EXT
GP
P3rd ABS
P3rd EXT
PINT CALC
In the plot shown above, the operating current
has been reduced to 50% of I
DSS
; the single-tone P
1dB
=
+22.2 dBm, with a PAE of 59%, which indicates Class
AB operation. Note that the extrapolation method for
determining IP3 shows a value of +30.5 dBm, somewhat
lower than the expected 22.2 + 10.6 = 32.8 dBm. Gain
expansion is seen at input power levels between +5 to
+9 dBm, and the power transfer model fits poorly to the
actual data. The table below summarizes the bias
effects on device linearity. The 75D data shows the
effect of de-tuning the output match to the device by 1
dB, to simulate a non-ideal circuit matching environment.
There is no discernible effect on linearity.
LP 7612 DHPHEMT IMD PERFORMANCE VS. OPERATING POINT
V
DS
= 5.0V TEST FREQ. = 18 GHz
I
DS
(%)
P
1dB
(dBm)
PAE
(%)
Gain
Expansion
Calculated IP3
(dBm)
Graphical IP3
(dBm)
30 21.7 59 0.3 dB 28-30 35.0
50 22.2 59 0.8 dB 28.5 30.5
75 21.5 47 None 35.0 35.0
75D 20.5 38 None 35.0 35.5
100 20.7 30 None 28.0 30.0
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 18
Similiar data for the LP 6872 device is shown below:
LP 6872 8V 50%IDSS
-20
-10
0
10
20
30
40
50
13.4 14.5 15.5 16.4 17.5 18 19.1 20.3 21.3 21.9 22.9 24 25 26 27 28 29 30 31 32 33 34
INPUT POWER (dBm)
POUT 1-TONE
POUT EXT
GP
P3rd ABS
P3rd EXT
PINT CALC
LP 6872 DHPHEMT IMD PERFORMANCE VS. OPERATING POINT
TEST FREQ. = 18 GHz
V
DS
(V)
I
DS
(%)
P
1dB
(dBm)
PAE
(%)
Gain
Expansion
Calculated IP3
(dBm)
Graphical IP3
(dBm)
8 30 27.9 42 0.1 dB 38-39 38
8 50 28.3 44 0.2 dB 39-41 43
7 75 28.2 49 0.1 dB 36-39 42
8 75 28.2 43 0.3 dB 35-38 40
8 85 28.3 40 None 41-42 42
The LP 6872 DHPHEMT, nominally P
1dB
= 27
dBm at 18 GHz, exhibits good IMD performance over a
wider range of bias conditions, but once again optimum
linearity is achieved with a quiescent operating point set
at or above 50% I
DSS
. As a further degree of freedom,
the operating voltage can be adjusted over the 6-9V
range without significant degradation of device linearity.
This may be useful for optimizing the gain and power
matching conditions.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 19
Operating Current Pulling:
0
10
20
30
40
50
60
-5 0 5 10 15 20 25
PIN (dBm)
Ids 5v100p
Ids 5v70p
Ids 5v30p
Ids 5v50p
I
DS
vs. Input Power at V
DS
= 5V
I
DSS
= 56 mA
mA
The data presented above shows the typical
current pulling effect for the LP 7612 DHPHEMT
discrete device, biased at V
DS
= 5V, at a test frequency
of 15 GHz. The vertical axis shows the Drain supply
operating current as a function of input power for 30, 50,
70, and 100% of I
DSS
. For most bias conditions, the
operating current pulls up as the device is driven into
saturation; for the PHEMT this is due to instantaneous
current (i.e., RF current) excursions above I
DSS
, as
discussed in Sec. 6. This data shows input power levels
equating to 12 dB of gain compression; note the rapid
decrease in current at extreme drive levels, P
IN
> 18
dBm, that indicates the onset of Gate conduction current.
Continuous RF input power levels that result in large
values of gain compression is not recommended for
reliable operation.
Note that for a quiescent operating point (OP) at
100% I
DSS
, the onset of Gate conduction current occurs
at a slightly lower input power level, and that the
operating current decreases significantly. Any
appreciable amount of Gate current results in a shift of
the OP due to an ohmic drop of about 75-100 mV due to
the Gate metal resistance, which is about 7 for this
device, in addition to the circuits grounding resistor, if
any.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 20
7. SMALL-SIGNAL S-PARAMETERS AND LUMPED-ELEMENT MODELS
A complete listing of small-signal scattering
parameters for all production-released FSS discrete
MESFET and PHEMT devices is available from an
authorized Sales Representative or directly from the
foundry. This DOS-formatted 3.5 diskette contains S-
parameters files in the Touchstone format, which is
denoted by the suffix .s2p on the file names. This
diskette also contains several Readme text files that
contain additional measurement-specific information,
such as bond wire lengths, etc. The S-parameter files
can be viewed using the MS-DOS Editor, or with MS
Windows Notepad (the user will need to Associate
the file with Text File [Notepad.exe]). The S-data file
contains one or two comment lines, followed by a header
line such as:
# S GHZ MA 50
This designates: S-parameters, frequency units in GHz,
Magnitude-Angle format (or RI Real-Imaginary), and 50
ohms normalization. The header line is followed by the
actual frequency and S-parameter data. The
Touchstone format can be directly imported into standard
CAD programs such as HPEEsof Libra or MDS.
Note that some files contain a n in the filename, such
as lp76_1n.s2p, which indicates that bias-dependent
Noise Characterization data is appended to the file, also
in Touchstone format.
For S-parameter characterization, the discrete
device was eutectically die-attached onto gold-plated
molybdenum carriers (for optimum heatsinking), along
with two JMicrotechnology Probepoint substrates. The
devices were then wire-bonded (using 0.0007 or 18 m
gold wire) from the appropriate bond pads to the
substrates. These substrates accommodate the GGB
Picoprobes, which are in a ground-signal-ground
configuration on a 150 m pitch. The input and output
reference planes of measurement are therefore up to the
bond wires; all S-parameter files contain bond wire
effects, as detailed in the Readme files. Actual
measurements were taken by a Hewlett-Packard 8510C
Network Analyzer.
Lumped-element small-signal models were
created by directly fitting to the measured S-parameter
data, by optimization for minimum error between actual
and modeled data. The resulting model was then
subjected to verification testing by comparison with
known parameters such as gate resistance and bond
wire effects. The basic lumped-element model is as
follows:
I = v G
e
DS C M
- j T
D

1+ j
f
F
L
G R
G
C
GS
R
I
GATE
C
DG
C
DC
R
S
L
S
SOURCE
I
DS R
DS
C
DS
R
D
L
D
DRAIN
+
_
VC
LUMPED-ELEMENT MODEL
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 21
FSS FET AND PHEMT LUMPED ELEMENT MODELS
ELEMENT LF 6836 LF 6872 LF 3814 LF 3830 LF 3850 LP 7512
(low/up)
LP 7612
(low/up)
LP 6872
L
G
, nH 0.24 0.14 0.14 0.08 0.06 0.14 0.17/0.20 0.14
R
G
, 10.7 5.3 2.0 1.18 0.20 5.3/6.4 7.0/4.4 1.0
C
GS
, pF 0.58 1.00 1.88 5.17 7.10 0.28/0.27 0.57/0.51 1.49
R
I
, 0.80 0.16 2.79 0.0 0.57 1.50 0.01 1.3
C
DC
, pF 0.02 0.04 0.14 0.09 0.06 0.05/0.04 0.02 0.01
G
M
, mS 90 130 200 470 580 90/100 90/100 230
T
D
, pS 0.03 0.07 0.68 0.01 0.04 0.01 0.04/0.10 0.03
F, GHz 41 45 25 25 30 55/55 50/44 41.2
R
DS
, 300 525 76.8 34.0 30.0 228/282 497/598 173
C
DS
, pF 0.05 0.12 0.12 0.49 0.68 0.03 0.06 0.16
C
DG
, pF 0.04 0.09 0.03 0.05 0.35 0.04 0.01 0.04
R
D
, 1.2 0.76 0.09 0.04 0.10 0.10 0.16/1.5 0.20
L
D
, nH 0.19 0.11 0.12 0.09 0.07 0.10 0.16/0.06 0.13
R
S
, 4.2 1.1 1.82 1.60 0.12 2.94/3.26 2.74/3.26 0.96
L
S
, nH 0.02 0.04 0.02 0.04 0.003 0.02/0.03 0.03 0.03
V
DS
, V 5.5 5 7 9 9 2 5 8
I
DS
, % 50 50 50 50 50 25 50 50
I
DSS
, mA 123 240 246 589 712 40 68 240
NOTES:
1). Model elements optimized to the following accuracies:
S
11
: Magnitude: 2% Phase: 3
S
22
: Magnitude: 4% Phase: 5
S
21
: Magnitude: 10% Phase: 5
S
12
: Magnitude: 10% Phase: 5
Accuracy defined with respect to measured S-data.
2). low/up: low optimized for 2-12 GHz band.
hi optimized for 10-26 GHz band.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 22
Typical modeled vs. measured S-parameter comparison is given below:
B1
S11
dat a
S[ 1. 1]
B2
S11
model
S[ 1. 1]
0.0 0.2 0.5 1.0 2.0 5.0 inf
0.0
0.2
0.5
1.0
2.0
5.0
-5.0
-2.0
-1.0
-0.5
-0.2
Fr equency 2. 0 t o 12. 0 Ghz
LP 7612 Vds5V I ds=50% l dss=68mA
Opt i mi zed f or 2 t o 12 GHz
B1
S22
dat a
S[ 2. 2]
B2
S22
model
S[ 2. 2]
0.0 0.2 0.5 1.0 2.0 5.0 inf
0.0
0.2
0.5
1.0
2.0
5.0
-5.0
-2.0
-1.0
-0.5
-0.2
Fr equency 2. 0 t o 12. 0 Ghz
LP 7612 Vds5V I ds=50% l dss=68mA
Opt i mi zed f or 2 t o 12 GHz
B1
S12
dat a
S[ 1. 2]
B2
S12
model
S[ 1. 2]
Fr equency 2. 0 t o 12. 0 Ghz
LP 7612 Vds5V I ds=50% l dss=68mA
Opt i mi zed f or 2 t o 12 GHz
0.05
0.04
0.03
0.02
0.01
0.0
B1
S21
dat a
S[ 2. 1]
B2
S21
model
S[ 2. 1]
Fr equency 2. 0 t o 12. 0 Ghz
LP 7612 Vds5V I ds=50% l dss=68mA
Opt i mi zed f or 2 t o 12 GHz
6.0
5.0
4.0
3.0
2.0
1.0
0.0
150
120
90
60
30
0 180
-150
-90
-60
-30
-120
180
-150
-120
-90
-60
-30
0
30
60
90
120
150
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 23
8. BIASING CIRCUITS AND STABILIZATION TECHNIQUES
Basic Self-Bias Configuration:
A typical hybrid amplifier circuit utilizing discrete
devices and implemented in microstrip is shown
schematically below, along with a sketch of the actual
circuit. In this particular example, the MESFET or
PHEMT active device is self-biased, so that a single
DC voltage supply is used; this is done by floating the DC
ground of the device with discrete RF bypass capacitors.
The devices gate is DC grounded through the thin-film
resistor as shown, and therefore the required negative
gate-source voltage is established by the voltage drop
across the source resistor. The drain bias is fed through
a quarter-wavelength high-impedance line which is RF
grounded at one end. For this illustration, conjugate gain
matching is accomplished by use of Series-L Shunt-C
matching networks on both the input and output circuits,
implemented as microstrip lines and open-circuited stub
lines.
INPUT MATCHING
NETWORK
OUTPUT MATCHING
NETWORK
RF
OUT
RF
IN
SOURCE RESISTOR
NETWORK WITH RF
BYPASS CAPACITOR
GATE GROUNDING
RESISTOR WITH
RF CHOKE
+VS
DC DE-COUPLING
CAPACITOR (x2)
8/4 HIGH-IMPEDANCE
MICROSTRIP LINE FOR
RF CHOKE (SHORTED STUB)
THIN-FILM RESISTOR
LADDER FOR BIAS
LEVEL SETTING
SERIES-L SHUNT-C MATCHING
NETWORK IMPLEMENTED AS
MS LINE + OPEN-CIRCUITED LINE
RF CHOKE + THIN-FILM
RESISTOR FOR DC GATE
GROUNDING
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 24
Gate Grounding Resistor:
In many instances, the gate DC grounding
resistor and its associated RF choke can serve a dual
role; in addition to providing the necessary DC ground for
the gate of the active device, this network can provide
stabilization at frequencies below the circuits passband.
Typically (and especially for low-noise designs) the RF
choke is implemented as a quarter-wavelength high-
impedance microstrip line. Caution should be used for
lengths other than 90 effective length in the passband,
since the noise performance will be degraded. For low-
noise devices (such as the LP 7512 and LP 7612) a
resistor value of 5-15 ohms is satisfactory. For some
applications it is desirable to eliminate the grounding
resistor, and in these cases care must be taken to
ensure that the circuit is stable below the passband,
especially below 2 GHz, where the inherent gain of the
PHEMT devices becomes very large.
Alternately, the grounding resistor may be placed
at the top of the RF choke, and in this configuration
smaller or large resistor values may be used. This is
sometimes desired for power devices, to avoid re-biasing
if the device begins to draw gate current.
Source Resistor Ladders:
For self-biased circuits, the DC operating current
is established by the voltage drop across the source
resistor(s), so it is important to provide suitable
combinations of resistors. In this instance, the PHEMT
devices simplify the design process, since the Pinch-Off
Voltage (VP) is nominally 0.8V, and is somewhat
invariant with I
DSS
and device size (gate width).
Suggested resistor-ladder values are given in the table
below:
Nominal IDSS
(mA)
RS Sequence
()
30 30 / 15 / 7.5 / 3.25 / 1.63
60 20 / 15 / 7.5 / 3.25 / 1.63
120 5 / 2.5 / 1.25 / 0.63 / 0.31
220 2 / 1 / 0.5 / 0.25 / 0.125
450 1 / 0.5 / 0.25 / 0.125 / 0.06
650 0.8 / 0.4 / 0.2 / 0.1 / 0.05
These values allow for adjustment about a
nominal 50% I
DSS
, which will occur at approximately 50%
V
P
. For FSSs MESFET devices, the Gate-Source
voltage required for a 50% I
DSS
operating point can be
provided for a specific wafer lot if needed.
Stabilization:
The general issue of stability is now considered,
using a LP 7612 PHEMT device as an example. The
data presented in the table following was taken at V
DS
=
5V, I
DS
= 50% I
DSS
, with no source bypass capacitors;
bond wire inductances are included, with gate bond wires
typically 0.004-0.006 long (2 per device), drain wires
0.006-0.008( 2 per device), and source wires 0.006-
0.008 (4 per device). Note that the Stability Factor K is
less than unity at all frequencies, indicating that device
as is potentially unstable, depending upon the load and
source impedances presented to the device. The Gain
column presents either the Maximum Available Gain,
G
MAX
, when k > 1.0, or Maximum Stable Gain, G
MS
, in the
case where K < 1.0. For k < 0, the device is unstable in
a 50 system. Examination of the Stability Circles
1
indicates that the largest regions of potential instability
are in the load impedance plane, therefore careful
attention must be paid when designing output matching
networks. The Stability Factor k is defined as:
k
S S D
S S
where D S S S S

+

1
2
11
2
22
2 2
12 21
11 22 12 21
:
where Sij = two-port power scattering parameters. The
power gains G
MAX
and G
MS
are defined as:
( )
G
S
S
k k
G
S
S
MAX
MS
t

21
12
2
21
12
1
Stability circle definitions can be found in Vendelin
1
.
1. G. D. Vendelin, Design of Amplifiers and Oscillators
by the S-Parameter Method, Wiley, New York, 1982.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 25
LP 7612 S-Parameters, Stability and Power Gain
FREQ. S11 S21 S12 S22 GMAX
GMS
k S21
(dB)
(GHz) MAG ANG MAG ANG MAG ANG MAG ANG (dB)
2 0.95 -37 5.95
152
0.02
73
0.83
-9
25.8 0.18 15.5
6 0.78 -96 4.34 109 0.03 51 0.77 -23 21.1 0.52 12.7
10 0.68 -137 3.13 79 0.04 45 0.74 -35 19.0 0.80 9.9
14 0.65 -166 2.41 56 0.05 48 0.74 -47 17.2 0.89 7.6
18 0.64 171 1.93 36 0.06 54 0.74 -61 15.3 0.84 5.7
22 0.67 152 1.63 18 0.08 57 0.73 -74 13.4 0.61 4.3
26 0.70 131 1.37 0 0.10 56 0.75 -86 11.3 0.35 2.7
30 0.72 115 1.24 -16 0.15 53 0.81 -101 9.2 0.01 1.8
As can be seen from this data, the LP 7612
provides excellent gain to 25 GHz and beyond, but does
require stabilization at lower frequencies. For example, if
the device is to be used in a 6 - 18 GHz gain stage, there
is potential for instability below 5 GHz. One method to
improve this situation is to apply the RF choke /
grounding resistor network to the input of the device;
using a 5 mil wide by 65 mil long (0.13 by 1.65 mm.)
microstrip line (on 10 mil [0.25 mm] alumina), with a 20
grounding resistor gives the following:
FREQ. k GMAX
GMS
2 6.14 14.2
6 0.84 20.8
10 0.76 18.8
14 0.85 17.2
18 0.87 15.4
22 0.71 13.5
26 0.57 11.4
30 0.47 9.4
Now the stability is improved at frequencies below the
passband, with little degradation of G
MS
in the passband
of interest. For additional stabilization above the
passband, the network can be modified to include a
shunt capacitor to ground (implemented as an open-
circuited stub), as shown below:
Both distributed elements are quarter-
wavelength (at the band center frequency f
C
) high-
impedance lines. Above the passband, the open-
circuited line acts as a shunt capacitance to ground,
thereby improving the stability. This lines width may be
varied to improve the roll-off characteristics above the
passband.
For low-frequency applications, classical
resistive shunt feedback may be used to simultaneously
stabilize and match the device. For example, a LP 7612,
with two 50 pF source bypass capacitors, can be
stabilized with a series R-L network (R=450, L=1 nH)
for operation in the 2-4 GHz band. This results in an
insertion gain S
21
= 11.5 dB, and input/output return loss
of better than -8 dB. Note that the phase of S
21
for this
device is such that this technique is useful only for
frequencies below about 8 GHz.
/4 at fC
20
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 26
9. LARGE-SIGNAL MODELS AND OPTIMUM POWER MATCH DATA
Introduction
Two large-signal models were utilized to
characterize the non-linear properties of FSSs discrete
MESFET and PHEMT devices, the Root model
(developed by Hewlett-Packard) and the classical Curtice
model. The Root model extraction consists of a file that
is directly read by Libra (Release 6.0) and MDS. The
Curtice model can also be used with these CAD
programs, but was originally derived for use with SPICE.
Curtice model elements are presented in tabular form in
this section, but the Root model extractions are available
only on the FSS Devices Data Diskette. For
convenience, Optimum Power Match data is presented
below for the devices that were Root-modeled.
The Root model represents a departure from
standard non-linear models in that there are no closed-
form analytical equations that model the I-V curves and
non-linear capacitance effects as in the Curtice model.
Therefore the Root model does not assume any
particular functional relationships for the I-V curves, and
is inherently more accurate. One disadvantage of the
model is that it does not provide any additional insight
into the device physics, so it cannot be compared to
theory directly; it is a file based model.
Root Model Background
The Root model replaces several of the
elements in the linear model (Sec. 7) with contour
maps of charge vs. terminal voltage. Specifically, C
GS
,
C
GD
and C
DS
are replaced with fitted contour functions
that map the charge in the device as a 2-dimensional
function of terminal voltages; the devices parasitic
elements, such as R
G
, L
G
, etc., are modeled with lumped
elements. For example, the charge under the gate, Q
G
,
is fitted to such a contour by measuring the devices S-
parameters at many points along the I-V curves; from
this data the voltage-dependent capacitances C
G
and
C
GD
are mapped as shown in the figure below.
Essentially the Root model derives an admittance matrix
which, along with the parasitic elements, can predict the
non-linear behavior of a device without assuming a
specific functional behavior. The result is a fairly
accurate high-frequency large-signal model. There are
some limitations, however, for example, the requirement
to measure S-data over the devices I-V curves is
impractical with large power PHEMT devices, since they
are inherently unstable in certain regions. Temperature
effects and modeling of Class B and C operation are also
not addressed by the model. Despite these limitations,
the Root model represents one of the most accurate
large-signal models available today that is supported in
commercial CAD software.
( )
( )
C V ,V
Y V ,V
G GS DS
11
meas
GS DS

Im ,

( )
( )
C V ,V
Y V ,V
GD GS DS
12
meas
GS DS

Im ,

V
DS
V
GS
Q
G
dQ
G
= -C
GD
dV
DS
dQ
G
= C
G
dV
GS
Root Model
Q
G
Charge Contour
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 27
SUMMARY OF FSS DISCRETE DEVICE LARGE-SIGNAL MODEL EXTRACTIONS:
DEVICE MODEL
LP 7612 Root
LP 6872
(half-cell)
Root
LF 6836 Root
LF 3814 Root
LF 6872 Root
LF 3830 Curtice
LF 3850 Curtice
POWER PERFORMANCE AND OPTIMUM POWER MATCH
AS PREDICTED BY THE ROOT MODEL:
DEVICE FREQUENCY
(GHz)
OPTIMUM
POWER
MATCH
P
1dB
(dBm)
POWER
GAIN
(dB)
MAG PHASE
LP 7612
5V, 50%
IDSS = 63 mA
12
18
24
30
0.492
0.460
0.440
0.502
75.4
102.0
132.1
161.1
18.4
18.6
18.6
18.3
14.8
11.0
8.9
7.9
LP 6872
8V, 50%
IDSS = 240 mA
6
12
18
24
0.455
0.433
0.506
0.607
105.0
141.0
165.1
-176.0
26.3
27.2
27.4
27.5
19.7
12.7
9.8
8.4
LF 6836
5.5V, 50%
IDSS = 142 mA
12
18
0.404
0.345
87.2
121.4
19.7
20.3
9.7
7.1
LF 3814
7V, 50%
IDSS = 270 mA
4
8
12
0.526
0.448
0.500
92.4
122.2
143.2
23.3
25.3
25.6
16.7
9.7
7.2
LF 6872
8V, 50%
IDSS = 257 mA
6
12
0.486
0.432
76.7
112.5
23.0
24.7
12.4
7.6
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 28
NOTES:
1). Root Model files are found on the FSS Devices Diskette; these files have the extension .raw The file should be
directly read into the simulator; for example, in Libra the Root file should be place in the Data subdirectory in a specific
Project Directory. These files are in ASCII text format. Do not scale the models. Predicted maximum power (at 1 dB
compression) is generally within 1-1.5 dBm of actual values; simulated power performance should be taken as a relative
performance indication, not as an absolute.
2). The LP 6872 Root Model extraction was done for a half device, due to inherent instability in a 50 system. The user
should place two instances of the HPFET item, and connect the Gate, Drain, and Source connections together to form
the complete, composite 6872 device.
CURTICE MODEL EXTRACTIONS:
PARAMETER AND UNITS LF 3830 LF 3850
BETA, 1/V 0.0644 0.3668
GAMMA, 1/V 0.5 0.5
VOUTO, V 5.0 9.0
VTO, V -3.73 -1.735
A0, A 0.01 0.01
A1, A/V 0.001 0.001
A2, A/V
2
-0.001 -0.001
A3, A/V
3
-0.0001 -0.0001
TAU, sec. 0.0 0.0
R1, 0.0 0.0
R2, 0.0 0.0
VBO, V 100 100
VBI, V 0.6292 0.6119
RF, 0.0 0.0
IS, A 1.019 x 10
-11
1.019 x 10
-11
N 1.228 1.186
RDS, 44.84 33.88
CRF, Fd 1 x 10
-6
1 x 10
-6
RD, 0.2 0.474
RG, 0.3 0.01
RS, 0.5 0.24
RIN, 4.401 -2.028
CGSO, Fd 5.89 x 10
-12
1.07 x 10
-12
CGDO, Fd 0.0 0.0
FC 0.5 0.5
CDS, Fd 2.94 x 10
-13
1.67 x 10
-12
CGS, Fd 0.0 0.0
CGD, Fd 1.83 x 10
-13
3.91 x 10
-13
LG, H (gate inductance) 1.07 x 10
-10
6.30 x 10
-11
LD, H (drain inductance) 6.60 x 10
-11
6.20 x 10
-11
LS, H (source inductance) 4.00 x 10
-12
5.00 x 10
-12
LBG, H (gate pad inductance) 3.50 x 10
-11
3.50 x 10
-11
LBD, H (drain pad inductance) 2.50 x 10
-11
2.50 x 10
-11
LBS, H (source pad inductance) 2.50 x 10
-11
2.50 x 10
-11
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 29
10. EXAMPLE CIRCUITS
Gain Stage for the LP 7612 DHPHEMT:
A gain stage was developed for the LP 7612
discrete device, implemented in microstrip on a 10 mil
alumina substrate; the device is assumed to be die-
attached onto a groundbar, with source bypass
capacitors (2 at 8 pF each). This will allow self-biasing,
although the topology shown below does not include
biasing chokes. Optimization of the gain response
assumes that this stage will be utilized in a balanced
configuration, with 90 quadrature hybrids (e.g., Lange
couplers).
ELEMENT TYPE DIMENSIONS (mils)
INPUT CIRCUIT: (Element nomenclature after conventions used in Libra, Touchstone)
1 MLIN W=10 L=40 (50 INPUT LINE)
2,3 MLEF 2 STUBS (OPEN-CIRCUITED MLIN) W=11.9 L=17.5
4 MCROS W1=10 W2=6 W3=W4=11.9
5 MLIN W=6 L=25.5
6,7 MLEF 2 STUBS W=13.8 L=11.6
8 MCROS W1=6 W2=21.1 W3=W4=13.8
9 MLIN W=21.1 L=15.9
10,11 MLEF 2 STUBS W=13.5 L=20.3
12 MCROS W1=21.1 W2=10.2 W3=W4=13.5
13 MLIN W=10.2 L=7
14 MTEE W1=10.2 W2=10.2 W3=2
15 MLIN W=2 L=67 (GATE GROUNDING CHOKE)
16 TFR RS=50 W=2 L=1 (GATE GROUNDING RESISTOR)
17 MLIN W=10.2 L=3
OUTPUT CIRCUIT:
1 MLIN W-5.3 L=28.6
2,3 MLEF 2 STUBS W=9 L=9.4
4 MCROS W1=5.3 W2=11.6 W3=W4=9
5 MLIN W=11.6 L=27
6 MLEF 1 STUB W=6.4 L=22.6
7 MTEE W1=11.6 W2=10 W3=6.4
8 MLIN W=10 L=40 (50 OUTPUT LINE)
INPUT CIRCUIT
OUTPUT CIRCUIT
LP 7612
NOT SHOWN: RF CHOKES
FOR DRAIN BIASING, DC
BLOCKING CAPACITORS
TUNING PADS MAY BE ADDED AS
DESIRED. 50 INPUT/OUTPUT
MLINS MAY BE SHORTENED AS
NEEDED.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 30
Simulated linear (small-signal) performance of
this gain stage is shown below; the SSG was 9.75 dB
over the 4 to 20 GHz band, with t0.25 dB of gain ripple.
Minimum stability (K-factor) was 0.7 at 8 GHz In a
balanced configuration with Lange couplers (W=1.2 mils,
S=0.85 mils, and L=97 mils), the SSG was 9.5 t0.5 dB,
with a minimum k-factor of 2.0. The improvement in
stability in a balanced configuration is typical, since the
potentially unstable regions in the source and load
planes are transformed to areas outside the normal
Smith chart ( 1.0). The Root model was utilized to
simulate the power performance, and the gain stage as
described above showed 5 dB of power slope across the
band.
SINGLE-ENDED GAIN STAGE PERFORMANCE
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
2.0 24.0
Prototype LP 7612 Gain Stage Linear Analysis
7612gain_tb
S21
7612gain
S[2,1]
db
7612gain_tb
K1
7612gain
K
Frequency 2.0 GHz/DIV
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 31
The output circuit can be re-optimized for better
power performance, resulting in the modified output
section shown below. The optimum power match data
presented in the preceding section was used for this re-
optimization, and in a self-biased balanced configuration,
a pair of 7612 devices provided 19.0 to 20.8 dBm of
linear power (simulated) over the 6-18 GHz band as
shown. Note that the devices were biased at about 70%
of I
DSS
, and that the Root model correctly predicted no
gain expansion prior to compression.
ELEMENT TYPE DIMENSIONS (mils)
MODIFIED OUTPUT CIRCUIT:
1 MLIN W=2.1 L=39.7
2 MLEF STUB W=11.5 L=25.5
4 MTEE W1=2.1 W2=10 W3=11.5
5 MLIN W=10 L=40 (50 OUTPUT LINE)
POWER PERFORMANCE WITH MODIFIED OUTPUT STAGE
MODIFIED OUTPUT CIRCUIT
MAY BE MEANDERED TO FIT SPACE
RESTRICTIONS AND ALLOW FOR
TUNING OF ELEMENT LENGTH
13.0
12.0
11.0
10.0
9.0
8.0
7.0
25.0
20.0
15.0
10.0
5.0
0.0
-5.0
-10.0
20.0
7612balpow_tb
PF1
7612balgain
PF
dBm
7612balpow_tb
GAIN
7612balgain
OUT_EQN
dB
Frequency, GHz
6.0
12.0
18.0
Linear Power (P1dB):
6 GHz
12 GHz
18 GHz
Power 5.0 dBm/DIV
Prototype LP 7612 Gain Stage w/Power Match
Balanced Configuration Vds=5.5V Ids=45mA (per device)
Self-Bias RS=8 ohms
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 32
6-18 GHz Power Stage for the LP 6872 DHPHEMT:
ELEMENT TYPE DIMENSIONS (mils)
INPUT CIRCUIT:
1 MLIN W=10 L=40 (50 INPUT LINE)
2,3 MLEF 2 STUBS W=6.9 L=13.7
4 MCROS W1=10 W2=3.2 W3=W4=6.9
5 MLIN W=3.2 L=12
6 MLEF 1 STUB W=17.1 L=4.4
7 MTEE W1=3.2 W2=6.9 W3 =17.1
8 MLIN W=6.9 L=34.6
9,10 MLEF 2 STUBS W=24 L=20.6
11 MCROS W1=6.9 W2=37.5 W3=W4=24
12 MLIN W=37.5 L=16
13 MTEE W1=37.5 W2=37.5 W3=3
14 TFR RS=50 W=3 L=2.5 (GATE GROUNDING RESISTOR)
15 MLIN W=3 L=48 (GATE GROUNDING CHOKE)
17 MLIN W=37.5 L=3
OUTPUT CIRCUIT:
1 MLIN W=4.3 L=20.4
2,3 MLEF 2 STUBS W=30.4 L=16.7
4 MCROS W1=4.3 W2=4.6 W3=W4=30.4
5 MLIN W=4.6 L=33.8
6 MLEF 1 STUB W=14.2 L=26.7
7 MTEE W1=4.6 W2=10 W3=14.2
8 MLIN W=10 L=40 (50 OUTPUT LINE)
INPUT CIRCUIT
OUTPUT CIRCUIT
LP 6872
NOT SHOWN: RF CHOKES
FOR DRAIN BIASING, DC
BLOCKING CAPACITORS
TUNING PADS MAY BE ADDED AS
DESIRED. 50 INPUT/OUTPUT
MLINS MAY BE SHORTENED AS
NEEDED.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 33
The Root model was utilized to optimize the
power performance of this circuit, and with two LP 6872
PHEMTs, in a self-biased balanced configuration,
produced over 30 dBm of linear power, with about 9 dB
of power gain. The model did exhibit some irregularities
under conditions of large input power levels which
created convergence problems during the simulation. In
the plot below, the circuit is not fully compressed by 1 dB
across the band, but does exhibit acceptable output
power over the 6-18 GHz band. Simulated SSG = 9.5
dB, with t0.4 dB of gain ripple.
POWER PERFORMANCE IN A BALANCED CONFIGURATION:
Output Power
Power Gain
15.0
14.0
13.0
12.0
11.0
10.0
9.0
8.0
7.0
6.0
5.0
31.0
30.0
29.0
28.0
27.0
26.0
25.0
24.0
23.0
22.0
21.0
0.0
20.0
Frequency 5.0 GHz/DIV
Prototype LP6872 Power Stage
Balanced Self-Biased at 22.5dBm Input Power
Vd=9.0V Ids=140mA Idss=210mA RS=2.5 ohms
6872balpower_tb
PF1
6872balpower
PF
dBm
6872balpower_tb
GAIN
6872balpower
OUT_EQN
dB
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 34
The plot below shows predicted compression
characteristics in this stage, with a slight amount of gain
expansion (about 0.15 dB), consistent with the quiescent
bias point of 67% (see Sec. 6). Simulated P
1dB
= 30.7
dBm at 16 GHz, with a saturated output power of about
31.5 dBm.
COMPRESSION CHARACTERISTICS AT 16 GHz
Small-Signal Gain
32.0
27.0
22.0
17.0
12.0
Power 2.0 dBm/DIV
Prototype LP6872 Power Stage
Vd=9.0V Ids=140mA Idss=210mA RS=2.5 ohms
6872balpower_tb
PF1
6872balpower
PF
dBm
6872balpower_tb
GAIN
6872balpower
OUT_EQN
dB
11.0
10.0
9.0
8.0
7.0
0.0 26.0
Frequency, GHz
16.0
P1dB = 30.7
Psat = 31.5
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 35
2 GHz 1 Watt Power Stage for the LP 6872:
A 2 GHz, 1W power stage utilizing two LP 6872
DHPHEMT devices is shown below, implemented in
microstrip on Duroid (
R
= 2.2, h = 10 mils [0.25 mm]),
and using a lossy input matching network to achieve
adequate stability and flat SSG.
1
The output circuit is
designed for optimum power match, while the input
circuit is derived from a second-order all-pass network,
with the PHEMTs input capacitance C
GS
(as modified by
the Miller effect) incorporated as one of the networks
elements. The simulated SSG is 17.5-18.0 dB at 21
GHz, with an input return loss of -12 dB, and a worst-
case stability factor of 1.3 (at 2.5 GHz). The
implementation of this circuit utilizes a combination of
lumped element (chip) components and microstrip
elements. The circuit is predicted to provide +30.2 dBm
of linear power at 2 GHz, with a Power-Added Efficiency
of 38%.
1. Arell, T., and Hongsmatip, T., 2-6 GHz Commercial
Power Amplifier, Applied Microwave, Winter 1993, pp.
51-56.
ELEMENT TYPE DIMENSIONS (mils) OR VALUE (units)
INPUT CIRCUIT:
1 MLIN W=30 L=100 (50 INPUT LINE)
L1 IND L=1.6 nH
L2 IND L=1.1 nH
C1 CAP C=1.3 pF
R1 RES R=18 ohms
OUTPUT CIRCUIT:
1 MLIN W=27 L=35
2 MTEE W1=27 W2=30 W3=34
3 MLEF 1 STUB W=34 L=57
4 MLIN W=30 L=100 (50 OUTPUT LINE)
L1
C1
L2
R1
-V
G
100 pF (x4)
LP 6872 (x2)
LAYOUT MAY NEED
TO BE MODIFIED TO
ACCOMODATE ACTUAL
CHIP COMPONENT SIZES
NOT SHOWN: DRAIN
BIASING CIRCUIT
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 36
PREDICTED POWER PERFORMANCE
16.5
16.0
15.5
15.0
14.5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.0 20.0
6872cbandpow_tb
PF1
6872cbandpow
PF
dBm
6872cbandpow_tb
GAIN
6872cbandpow
OUT_EQN
dB
Frequency, GHz
1.5
2.0
2.5
3.0
Linear Power (dBm):
1.5 GHz 29.7
2.0 GHz 30.2
2.5 GHz 30.5
3.0 GHz 30.5
Power 5.0 dBm/DIV
Prototype 2 GHz Power Amplifier
Two LP 6872 PHEMTs
Vds=9V Ids=290mA Dual Bias Vgs=-0.3V
32.0
30.0
28.0
26.0
24.0
22.0
20.0
18.0
16.0
14.0
12.0
10.0
8.0
6.0
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 37
6-18 GHz Low Noise Stage for the LP 7512 SHPHEMT:
ELEMENT TYPE DIMENSIONS (mils)
INPUT CIRCUIT:
1 MLIN W=10 L=40 (50 INPUT LINE)
2,3 MLEF 2 STUBS W=10 L=13
4 MCROS W1=10 W2=9.4 W3=W4=10
5 MLIN W=9.4 L=33
6,7 MLEF 2 STUBS W=10.8 L=14.8
8 MCROS W1=9.4 W2=20.4 W3=W4=10.8
9 MLIN W=20.4 L=40.3
10,11 MLEF 2 STUBS W=18.4 L=16.1
12 MCROS W1=20.4 W2=7.5 W3=W4=18.4
13 MLIN W=7.5 L=9.8
14 MTEE W1=W2=7.5 W3=2
15 MLIN W=2 L=67
16 TFR RS=50 W=2 L=1
17 MLIN W=7.5 L=3
OUTPUT CIRCUIT:
1 MLIN W=12 L=31.3
2,3 MLEF 2 STUBS W=27.7 L=20
4 MCROS W1=12 W2=10.3 W3=W4=27.7
5 MLIN W=10.3 L=17.3
6 MLEF 1 STUB W=20 L=16
7 MTEE W1=10.3 W2=10 W3=20
8 MLIN W=10 L=40 (50 OUTPUT LINE)
INPUT CIRCUIT
OUTPUT CIRCUIT
LP 7512
NOT SHOWN: RF CHOKES
FOR DRAIN BIASING, DC
BLOCKING CAPACITORS
TUNING PADS MAY BE ADDED AS
DESIRED. 50 INPUT/OUTPUT
MLINS MAY BE SHORTENED AS
NEEDED.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 38
The simulated noise and gain performance of
this stage is shown below; nominal performance was 1.9
dB noise figure from 12-18 GHz, with SSG = 8.5 t 0.6 dB
over the 6-18 GHz band. Significantly lower noise figure
can be achieved with this device for narrower
bandwidths; the typical LP 7512 performance is 1.0 dB
NF at 18 GHz.
SINGLE-ENDED NOISE PERFORMANCE
Gain
10.0
9.0
8.0
7.0
6.0
5.0
Power 2.0 GHz/DIV
Prototype Single-Ended LP 7512 Low Noise Stage
Vds=2V Ids=15mA
7512noise_tb
S21
7512noise
S[2.1]
dB
7512noise_tb
NF1
7512noise
NF
dB
6.0
5.0
4.0
3.0
2.0
1.0
2.0 20.0
Noise Figure
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 39
11. RECOMMENDED ASSEMBLY TECHNIQUES
Handling of Discrete Devices:
Handling of FSS Discrete Devices must at all
times be done with Electrostatic Discharge (ESD)
precautions, as outlined below. The devices may be
manually handled with clean sharp tweezers by grasping
the device on its edges. Some devices include airbridge
structures that are easily damaged with careless
handling.
Automatic handling equipment may be used, but
soft, conductive pick-up collets are preferred. Collets
must be grounded to prevent static charge accumulation.
The optimum collet size is such that the device is
contacted around its periphery and away from the active
structures in the center. Rectangular cross-sections are
preferred.
Die Attach:
The recommended die attach is the eutectic
die attach, using a 80/20 Gold/Tin eutectic solder, which
has a melt temperature of about 280C. Eutectic die
attach should be done under forming gas (90% N
2
, 10%
H
2
) for best results. If forming gas is not available, then
clean dry N
2
gas should be used. Eutectic die attach in
ambient air is not recommended. Pre-sized eutectic
preforms are available in a variety of sizes; use a
preform whose dimensions are close to the device being
attached. The device can be placed using clean sharp
tweezers, once the preform has melted on the heated
stage (which is typically 285-290C); the assembly
should be removed from the heated stage as soon as
the die is positioned. For large devices (greater than 0.5
x 0.5 mm or 20 x 20 mils), the assembly should be
cooled at a rate of about 10C per minute, to reduce
thermal stresses. Maximum time at the eutectic
temperature is 1 min.
Other solder materials may be used; contact the
Foundry for compatibility. Another acceptable die attach
method is the use of conductive epoxy (gold or silver
filled), which is assembled at room temperature and then
cured per the manufacturers directions. The epoxy die
attach should not be used for power devices, since the
thermal resistivity of the device will be degraded.
Die Placement:
In general devices should be placed as close as
possible to the matching circuits, regardless of the type
of substrate material used. For example, with microstrip
circuits implemented on alumina, the die should be
placed within 0.001 (0.025 mm) of the input matching
circuit to minimize the gate bond wire lengths. If source
bypass chip capacitors are used, they should be placed
as close as possible to the device to minimize source
bond wire length.
The optimum heatsink material is gold-plated
copper, molybdenum, or Cu composites, which allow for
efficient heat dissipation. Less desirable is kovar, and
direct die-attach onto duroid or alumina should only be
used for low noise applications. All heatsink material
should be gold (100 in min.) over nickel plated. Poor
heatsinking will result in high operating channel
temperatures and degraded device reliability.
Lead Bond:
The recommended lead bond technique is
thermocompression wedge bonding with 0.001 (25 m)
diameter gold wire. This should be done on a heated
stage at 230-240C, with a heated bonding tool at 150-
160C. Dry N
2
or forming gas is the preferred ambient
during bonding. The bond tool force should be 35-38
gm. Ultrasonic bonding is not recommended. Contact
the Foundry for additional information.
Storage:
FSS discrete devices should be stored in clean
dry Nitrogen gas at room temperature (20-25C).
Alternately, storage at room temperature in clean dry
ambient air is acceptable; in any case, the parts should
be stored with proper ESD precautions.
ESD Precautions:
Standard ESD precautions for Class 1A devices
(0-500V) should be observed in storing, handling, and
assembling FSS discrete devices. Users should follow
the measures outlined in MIL-STD-1686, Electrostatic
Discharge Control Program, and MIL-HDBK-263,
Electrostatic Discharge Control Handbook.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 40
12. PARAMETRIC SCREENING AND QUALITY ASSURANCE
Filtronics Quality Assurance procedures for its
discrete FET and PHEMT devices are patterned after the
JANC level requirements of MIL-STD-19500J. FSS
offers its discrete devices in three basic grades, as
follows:
Commercial/Military Grade (C/MG)
(Bulk purchase)
Sorted Military Grade (SMG)
High-Reliability Grade (HiRel)
These grades differ with respect to the level of
parametric screening and visual inspection. All grades
are warranted to meet or exceed the performance
specifications as indicated for each device type on the
appropriate Datasheet. Test methods and visual
inspection criteria are per MIL-STD-750, as detailed
below. The discrete device fabrication, test, and Quality
Conformance Inspection (QCI) sequence is as follows:
GaAs SUBSTRATE INSPECTION
AND PREPARATION
MOLECULAR BEAM
EPITAXIAL GROWTH
EPITAXIAL CHARACTERIZATION
Defect Density
Sheet Carrier Density
Hall Mobility
LOT FORMATION
6-10 wafers/lot
PROCESSING / FABRICATION
FINAL ELECTRICAL AND
VISUAL INSPECTION
100% DC TEST
GROUP A TESTS
Subgroups 1 and 2
10 devices / wafer
ACCEPT/REJECT 10/1
GROUP B TESTS
Bond Pull / Die Shear
5 devices / wafer
ACCEPT/REJECT 5/0
LOT ACCEPTANCE INSPECTION
Per Sequence Below
ACCEPT/REJECT 10/1
PREPARATION FOR SHIPMENT
COMMERCIAL/MILITARY GRADE
Sample Visual Inspection
Film Frame Packing
SORTED MILITARY GRADE
100% Visual Inspection
Packing (Waffle or Gel Pack)
HIGH-RELIABILITY GRADE
Wafer Lot submittal for
JANS screening
SCRIBE AND BREAK
SAMPLE VISUAL INSPECTION
FILTRONIC SOLID STATE
DISCRETE DEVICE
FABRICATION AND
QUALITY ASSURANCE
SEQUENCE
STABILIZATION BAKE
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 41
TABLE 1 GROUP A TESTS AND METHODS
SUBGROUP TEST OR INSPECTION SYMBOL MIL-STD-750
METHOD
1 DC Characteristics:
Saturated Drain-Source Current
Transconductance
Peak Transconductance (opt.)
Pinch-Off Voltage
Gate-Source and Gate-Drain Leakage Current
Gate-Source and Gate-Drain Breakdown Voltage
Forward Gate Voltage (opt. for JANS level)
I
DSS
G
M
G
M PEAK
V
P
I
GS
, I
GD
BV
GS
, BV
GD
V
GF
3413
3455 (60 Hz)
3455 (50%V
P
)
3403
3401, 3411
3401, 3411
2 RF Characteristics:
Optimum Noise Figure
Associated Gain at NF
MIN
Max. Output Power at 1 dB Gain Compression
Power Gain at P
1dB
Power-Added Efficiency at P
1dB
NF
MIN
G
A
P
1dB
G
P
PAE ()
3246.1
3255
NOTE: Noise Figure is not measured on power devices, and power performance (P
1dB
, G
P
, PAE) is not characterized on
low noise devices.
LOT ACCEPTANCE INSPECTION
SMALL LOT ASSEMBLY
10 devices / wafer
DIE ATTACH / LEAD BOND
INTERNAL VISUAL INSPECTION
HERMETIC LID SEAL
STABILIZATION BAKE
GROUP A TESTS
Subgroup 1
DC POWER BURN-IN
96 Hours, TCH = 175C
GROUP A TESTS
Subgroup 1
ENDPOINT AND DELTA CALCULATIONS
Per Datasheet and Delta Limits Table
LOT ACCEPTANCE INSPECTION
SEQUENCE:
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 42
TABLE 2 GROUP B TESTS AND METHODS
TEST OR INSPECTION MIL-STD-750
METHOD
CONDITION SMALL LOT
ACCEPT/REJECT
n/c
Bond Strength (Bond Pull)
Die Shear
2037
2017
All leads 5/0
5/0
TABLE 3 LOT ACCEPTANCE INSPECTION TESTS AND METHODS
TEST OR INSPECTION MIL-STD-750
METHOD
CONDITION SMALL LOT
ACCEPT/REJECT
n/c
Internal Visual Inspection
Stabilization Bake
DC Power Burn-In
Endpoint Calculations
Delta Calculations
2072
1031.4
1039
FSS Worksmanship Standards
24 hr. at 200C in N
2
ambient
96 hr. at 175C channel temperature
Per Datasheet min/max values
Per Table 4 Limits
---
---
---
10/1
10/1
TABLE 4 DELTA LIMITS
DELTA PARAMETER SYMBOL DELTA LIMITS FOR
DC POWER BURN-IN
Saturated Drain-Source Current
Transconductance
Peak Transconductance (opt.)
Pinch-Off Voltage
Gate-Source and Gate-Drain Leakage Current
Gate-Source and Gate-Drain Breakdown Voltage
I
DSS
G
M
G
M PEAK
V
P
I
GS
, I
GD
BV
GS
, BV
GD
t20%
t20%
---
t20%
t150% or 2.0A
t25%
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 43
In summary, 25 devices are taken at random
from each wafer submitted for QCI screening, with 5
devices used for Bond Pull/Die Shear testing, 10 for
Group A testing, and 10 for Lot Acceptance Inspection
(LAI). The devices used in Group A testing are die
attached and lead bonded into 50 ohm microstrip
evaluation circuits, and triple-sleeve low-loss coaxial
tuners are used to provide optimum impedance matching
for power, gain, and noise figure measurements. The
LAI devices are assembled and sealed into 100 mil
ceramic leaded packages for the power burn-in. Strict
adherence to JANC requirements calls for a sample of
22 per inspection lot, with an accept/reject limit of 22/0
(no failures allowed). This corresponds to a Lot
Tolerance Percent Defective (LTPD) of =10; the FSS
screening uses a sample size of 20 total, with 2 failures
allowed (20/2). The equivalent LTPD level is
approximately =25. The less stringent LTPD is justified
by the omission of High-Temperature Reverse Bias
(HTRB) screening prior to the power burn-in, which
would serve to remove infant mortality devices. The
use of microstrip test circuits for 10 of the sample
devices is done to minimize RF performance degradation
due to package parasitics.
For the Sorted Military Grade, Group A and LAI
testing is done on each wafer. For Commercial/Military
Grade, this screening is done on a run basis; a
fabrication run is defined as a group of 6-10 wafers that
are fabricated and processed simultaneously as a group.
Therefore as a minimum, each wafer run of 6-10 wafers
will have at least one wafer submitted for Group A and
LAI testing; devices purchased under the C/MG are not
necessarily from a wafer that has been screened, but the
purchaser can request devices from the screened wafer
in a given lot for a nominal surcharge. Devices
purchased to the High-Reliability Grade are subjected to
a more rigorous screening procedure per MIL-19500
JANS level. The various grades and the associated test
and inspection methods are summarized below:
DISCRETE DEVICE GRADES AND SCREENING PROCEDURES
GRADE
GROUP A
TESTING LAI TESTING
SHIPMENT METHOD
100% DC DATA
ON DISKETTE
VISUAL
INSPECTION
METHOD
FILM & RING WAFFLE OR GEL
PACKED
C/MG
COMMERCIAL
PER EACH
RUN
PER EACH
RUN
ONLY NOT AVAILABLE NOT AVAILABLE SAMPLE BASIS
C/MG
MILITARY UPGRADE
EACH
WAFER
EACH WAFER ONLY NOT AVAILABLE AVAILABLE SAMPLE BASIS
VISUAL YIELD
PROVIDED
SMG EACH
WAFER
EACH WAFER N/A YES PROVIDED 100% BASIS
HI-REL JANS JANS N/A YES PROVIDED 100% BASIS
NOTES:
1). Minimum order quantity for C/MG option is 1/4 wafer; approximate quantities available from an authorized FSS Sales
Representative or from the Foundry.
2). Hi-Rel screening per customer Source Control Drawing.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 44
WAFER FABRICATION
INITIAL VISUAL INSPECTION
MIL-750 METHOD 2070, 2072
SAMPLE BASIS: 35 DIE
PER WAFER
PCM TESTING
STABILIZATION BAKE
MIL-750 METHOD 1032
200C FOR 24 HRS
100% DC TESTING
GROUP A, SUBGROUP 1
SCRIBE & BREAK
SMALL LOT BUILD
35 MIN. PACKAGED DEVICES
DIE ATTACH, LEAD BOND
AND SEAL
INTERNAL VISUAL INSPECTION
MIL-750 METHOD 2071
GROUP B
SUBGROUP 1
SEM INSPECTION
MIL-750 METHOD 2077
BOND PULL TEST
MIL-750 METHOD 2037
3 DEVICES MIN., ALL LEADS
DIE SHEAR TEST
MIL-750 METHOD 2017
3 DEVICES MIN.
LID SEAL
STABILIZATION BAKE
175C FOR 24 HRS
DC PARAMETRIC SCREEN
GROUP A, SUBGROUP 1
SMALL LOT INSPECTION
QCI / LOT QUALIFICATION
DC TESTED DIE
FOR VISUAL INSPECTION
AND SHIPMENT PREP
FILTRONIC SOLID STATE
MIL-19500J JANS SCREENING SEQUENCE
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 45
PRE-BURN-IN
DC PARAMETRIC TESTING
PRE-CONDITIONING
DC POWER BURN-IN
MIL-750 METHOD 1039
T
CH
= 150C FOR 160 HRS
POST-BURN-IN
DC PARAMETRIC TESTING
PDA DETERMINATION
GROUP B
SUBGROUP 5
ACCELERATED LIFE TEST
MIL-750 METHOD 1027
5 DEV. / 0 REJECTS
PRE-BURN-IN
PARAMETRIC TESTING
DC POWER BURN-IN
T
CH
= 225C FOR 240 HRS
POST-BURN-IN
PARAMETRIC TESTING
DELTA CALCULATIONS
GROUP B
SUBGROUP 2
ACCELERATED LIFE TEST
MIL-750 METHOD 1027
5 DEV. / 0 REJECTS
PRE-BURN-IN
PARAMETRIC TESTING
DC POWER BURN-IN
T
CH
= 225C FOR 240 HRS
POST-BURN-IN
PARAMETRIC TESTING
DELTA CALCULATIONS
GROUP B
SUBGROUP 3
OPERATING LIFE TEST
MIL-750 METHOD 1026
8 DEV. / 0 REJECTS
PRE-BURN-IN
PARAMETRIC TESTING
DC POWER BURN-IN
T
CH
= 150C FOR 1000 HRS
POST-BURN-IN
PARAMETRIC TESTING
DELTA CALCULATIONS
GROUP A
SUBGROUP 2
RF TESTS
10 DEV. / 0 REJECTS
(OPTIONALLY DONE
ON CARRIER-MOUNTED
DEVICES)
100% VISUAL
INSPECTION
QA CERTIFICATION
PREPARATION
FOR SHIPMENT
SHIPMENT CSI
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 46
13. DISCRETE DEVICE UNIFORMITY
The uniformity of FSSs discrete PHEMT and
MESFET devices depends fundamentally on the
materials and processing technology utilized in the
manufacturing process. In addition to the Parametric
Screening and QCI testing as outlined in Sec. 12, typical
device uniformity data is presented below, using the LP
7612 DHPHEMT as the example. Uniformity is
presented at three levels: wafer uniformity, same-lot
wafer-to-wafer uniformity, and lot-to-lot uniformity. The
DC parametrics given are as measured during the 100%
screening, while the RF data presented was taken from a
RF-probeable version of the LP 7612. This modified
7612 device was directly measured on-wafer using
Cascade Microtech GSG coplanar probes. While the
S-data of this modified 7612 is not identical to the
production version, the data does represent the process
and material variation across a wafer.
TYPICAL 100% DC PARAMETRIC TEST DATA
LP 7612 LOT: 3059 WAFER: #4 TEST DATE: 4/30/96
TOTAL DIE TESTED: 21566 TOTAL PASSED DEVICES: 14032
PARAMETER UNITS MEAN STD.DEV.

LIMITS
UP/LOW
C
PK
Drain-Source Current, I
DSS
mA 70.7 6.6 40/85 0.72
Pinch-Off Voltage, V
P
V -0.84 0.19 -0.25/-1.50 1.06
Transconductance at I
DSS
, G
M
mS 67.6 21.5 50/--- 0.27
Transconductance at 50% V
P
mS 89.9 8.5 60/--- 1.17
Gate-Drain Breakdown, BV
GD
V -11.5 1.02 -8/--- 1.15
Gate-Source Breakdown, BV
GS
V -10.9 1.70 -6/--- 0.98
Leakage Current, I
GSO A 0.53 0.56 ---/10 0.30
TYPICAL RF UNIFORMITY: WAFER BASIS
LP 7612 LOT: 3051 WAFER: #3
10 SITES ACROSS WAFER V
DS
= 5V I
DS
= 50%I
DSS
PARAMETER FREQ
(GHz)
MAGNITUDE PHASE
MEAN MEAN
S
11
5
15
25
0.922
0.645
0.616
0.005
0.002
0.010
-60
-126
-149
3
3
3
S
21
5
15
25
4.73
2.27
1.49
0.15
0.04
0.07
135
80
57
2
3
3
S
12
5
15
25
0.048
0.068
0.036
0.005
0.009
0.007
59
6
3
2
2
2
S
22
5
15
25
0.755
0.564
0.572
0.018
0.030
0.068
-26
-55
-68
2
4
4
Maximum
Available
Gain (dB)
5
15
25
19.9
11.7
7.4
0.4
0.4
0.1
--- ---
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 47
TYPICAL RF UNIFORMITY: LOT BASIS
LP 7612 LOT: 3051 WAFERS #3, 4, 5, 6
ONE SITE AT RANDOM PER WAFER
V
DS
= 5V I
DS
= 50%I
DSS
PARAMETER FREQ
(GHz).
3 4 5 6
MAG. ANG. MAG. ANG. MAG. ANG. MAG. ANG.
S
11
5
15
25
0.929
0.641
0.599
-55
-120
-144
0.913
0.646
0.633
-65
-133
-157
0.913
0.639
0.617
-62
-129
-152
0.914
0.639
0.626
-65
-133
-157
S
21
5
15
25
4.88
2.49
1.63
138
84
62
4.82
2.25
1.45
132
77
52
4.97
2.38
1.55
134
81
59
4.90
2.28
1.48
131
76
51
S
12
5
15
25
0.054
0.080
0.054
60
9
1
0.044
0.057
0.024
58
3
10
0.064
0.088
0.062
56
7
0
0.046
0.061
0.027
57
2
5
S
22
5
15
25
0.719
0.512
0.503
-29
-62
-74
0.767
0.589
0.610
-24
-51
-64
0.731
0.508
0.509
-31
-61
-73
0.770
0.576
0.594
-26
-53
-67
Maximum
Available
Gain (dB)
5
15
25
19.6*
12.5
7.6
---
20.4*
11.5
7.6
---
18.9*
12.3
7.5
---
20.3*
11.4
7.5
---
NOTE: Maximum Available Gain with * indicates Maximum Stable Gain, since Stability Factor k < 1.0.
Lot-to-Lot Uniformity:
All lots are screened as outlined in Sec. 12, and
must meet all parametric test specifications. In this way,
minimum device performance is assured as detailed in
the appropriate Datasheet. Due to varying user
requirements, lots (groups of 6-10 wafers) are
occasionally targeted to specific I
DSS
ranges. This
targeting accounts for much of the lot-to-lot variation, but
comparison of different lots with similiar I
DSS
values will
exhibit good uniformity, on the order of same-lot wafer-
to-wafer uniformity. Users are encouraged to obtain
samples from a specific lot in order to verify performance
in a specific circuit or application; the quantity of
available die from a particular wafer or wafer lot is
available from the Foundry.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 48
14. DEVICE RELIABILITY
A summary of reliability investigations that have
been conducted on FSSs MESFETs, PHEMTs, and
MMICs is included in Appendix A. For MESFETs, the
measured MTTF is 1.0 x 10
8
hrs. at a channel
temperature of 120C, with an Activation Energy of 1.52
eV, and An Instantaneous Failure Rate of less than 10
FITs. For PHEMT devices, in addition to the work
summarized in the Appendix, recent work has shown
that the MTTF for DHPEMTs exceeds 1.2 x 10
7
hrs. at
T
CH
= 120C, based on an accelerated burn-in of
samples at 225C. These samples have accumulated
1,045 hrs. with no failures.
Filtronic
Solid State
Discrete FET / PHEMT Applications Notes 49
APPENDIX A
Filtronic
Solid State
Device and Process Reliability 50
Device and Process Reliability
InGaAs / AlGaAs PHEMT Devices
Revision B
January 1998
Filtronic
Solid State
Device and Process Reliability 51
Scope
This report presents a current assessment of the reliability of InGaAs/AlGaAs Pseudomorphic High Electron
Mobility Transistor (PHEMT) discrete and MMICs devices, as presently manufactured at Filtronic Solid State (FSS). GaAs
MESFET reliability results from earlier research conducted at FSS is included for completeness. The report concludes
with a summary of work in progress.
Background
The reliability of semiconductor devices can be modeled by the "log-normal" distribution, which is a probability
distribution function described by a shape parameter and a median lifetime, as follows:
{ }
p t
t
n t t
m
( ) exp
( / )

'

1
2
2
2
2

where = shape parameter, t = time, and t

m
= median lifetime. The interpretation of this function in the context of device
reliability is that integrating p(t) from zero to some time t
f
gives the probability that a given device has failed. Another way
to interpret this function is that the area under the curve p(t) from zero to the median lifetime t
m
is equal to 0.5, indicating
that there is a 50% chance that a device will have failed. The function is normalized such that the total area under the
curve is equal to one. This failure probability distribution assumes one dominant failure mechanism, with no early or
freak failures.
The median lifetime of a population of devices is closely related to the Mean-Time-to-Failure (MTTF), and
generally the two quantities are interchangeable. The MTTF is one of the primary parameters that must be determined for
a given device or process, and this is generally done by exposing a sample of devices to accelerated life testing at
elevated temperatures. The MTTF is determined by the definition of a device "failure," which in turn may be affected by a
number of degradation or failure mechanisms. One generally attempts to identify a single dominant failure mechanism,
and MTTF at some elevated temperature is assumed to follow the Arrhenius relationship:
AF
E
k T T
A
o A

_
,

'

exp
1 1
where AF = Arrhenius Acceleration Factor, E
A
= Activation Energy, k = 8.62 x 10
-5
eV/ K (Boltzmann constant), T
O
=
standard operating temperature, and T
A
= acceleration temperature. The Activation Energy (usually expressed in electron
volts, eV) characterizes the degradation process, and clearly should be as large as possible for reliable device operation at
elevated temperatures. For example, assuming E
A
= 1 eV, the acceleration factor resulting from device operation at
250C, compared to operation at 120C is AF = 1,537, meaning that a MTTF of 10
6
hours will be reduced to 651 hours at
the elevated temperature.
Another commonly used assessment in reliability analysis is the Instantaneous Failure Rate (IFR), which for a log-
normal distribution is given by:
1
( ) { }
( )
IFR
n t t
t efrc n t t
m
m

'

'

2
1
2
1
2
2
2
exp /
/

where efrc denotes the complementary error function. The IFR is usually multiplied by 10
9
, and the units of "FITs" are
commonly used, 1 FIT meaning one failure in 10
9
hours of operation. In expanded form:
1
H. Fukui, et. al., Reliability of Power GaAs Field-Effect Transistors, IEEE Trans. on Elec. Devices, Vol. ED-29, No. 3, March 1982.
Filtronic
Solid State
Device and Process Reliability 52
( ) { }
( )
IFR
n t t
t e dt
where z n t t
m
t
z
m

'

'

2
1
2
1
2
1
2
2
0
2
exp /
: /

To completely characterize the distribution, one must determine the shape factor and the median lifetime (or
MTTF) at a given temperature, and the Acceleration Factor is used to predict the MTTF at some other temperature. The
shape factor is taken to be invariant with temperature; it expresses the variation in time of device failures as the sample
ages past the median lifetime. Ideally there are no device failures until the median lifetime is reached, at which time most
of the devices fail at essentially the same time. For component and system lifetimes t
s
such that: t
s
<< t
m
, the average IFR
1/MTTF.
In the case of MESFET and PHEMT devices, the integrity of the Schottky contact formed by the Gate electrode is
of critical importance to reliable device operation. Changes in the metal-semiconductor barrier height will affect all other
channel parameters; therefore, the temperature that is substituted into the Arrhenius formula is the average channel
temperature, determined by the following:
T P P P
CH IN DC J OUT
+
where: T
CH
= Channel temperature, P
IN
= RF input power, P
DC
= DC power dissipated in device,
J
= channel-to-heatsink
thermal resistivity, and P
OUT
= RF power delivered to a load. The channel region for these devices is defined as the region
extending from the Drain contact to the Source contact, along the total periphery of the Gate, if the device is a multi-finger
or interdigitated topology. In the case of FSS devices, the thermal resistivity is measured by direct-contact nematic liquid-
crystal thermography. This method allows near-optical resolution, and features less than one micron can be imaged.
MESFET Device Structure and Reliability Assessment
The MESFET structure used at FSS is a classical recessed, offset gate structure, as shown below:
The semiconductor structure shown is grown by Molecular Beam Epitaxy, with the gate structure defined either
photolithographically or by direct-write electron-beam techniques. The device is passivated with a 2000A layer of silicon
nitride (Si
3
N
4
). The Gate metallization system in a refractory Ti/Pt/Au structure, with additional overplated gold, and the
ohmic contacts are alloyed AuGe/Ni/Au with overplated gold; both the Gate and ohmic contacts are industry-standard
technologies.
AuGe / Ni / Au Alloyed Contacts
N+ GaAs Active Layer
N- Buffer Layer
Drain
Contact
Source
Contact
Ti / Pt / Au Recessed Gate
N++ Contact Layer
GaAs MESFET STRUCTURE
Filtronic
Solid State
Device and Process Reliability 53
Samples of 0.5 x 285 (Gate length x width) m discrete MESFETs have been evaluated using both high
temperature storage (non-operating), and elevated temperature DC operating lifetest over the last several years. The
primary failure mode was a decrease in Saturated Drain-Source current (I
DSS
) and Pinch-off voltage (V
P
); a device failure
was defined to be a change of more than 20% from the initial value. No significant change in transconductance (g
M
) was
observed, at least when measured at zero Gate-Source bias (V
GS
). Gate-Source breakdown voltage (BV
GS
) decreased
initially, but then stabilized throughout the study. For the operating lifetest, a failure was defined as a change of more than
t20% in DC bias current I
DS
.
The results from both types of tests were similar, indicating that the dominant failure mechanism was independent
of electric field strength or current density. The failure data from both types of tests was combined to determine an
activation energy of 1.52 eV, with a projected median lifetime (or MTTF) of 1.0 x 10
8
hours at a channel temperature of
120C. The data showed a dispersion (shape factor) of = 0.49, with a projected Instantaneous Failure Rate (IFR) of
less than 10 FITs at the 120C channel temperature.
The probable degradation mechanism was diffusion of Gate metal into the active layer, commonly known as "gate
sinking." Elemental Au, in particular, acts as an acceptor impurity in GaAs, with a ionization energy of 0.09 eV (measured
above the valence band). The diffusion of metal into the channel can reduce the effective channel thickness, consistent
with a reduction of I
DSS
and V
P
. The stability of the transconductance at V
GS
= 0V indicated that neither the Gate-Source
parasitic resistance nor the contact resistance had degraded. This finding demonstrated excellent stability of the ohmic
contacts at high temperatures. Transconductance stability at bias conditions other than V
GS
= 0V was not characterized,
nor were any RF parameters measured. Initial changes in breakdown voltage were related to changes in surface defect
density (trapping sites); this is an example of an annealing effect, and does not affect long-term reliability.
MESFET MMIC Reliability
A 10-piece sample of 0.5 m gate length MESFET-based MMICs was exposed to a step-stress test at baseplate
temperatures of 125, 175, and 225C for 3600 hours at each temperature. No failures were noted during the 125 or 175C
trials, and 2 out of 10 devices failed after 2500 hours during the 225C trial, which corresponds to a channel temperature
of approximately 245C. Thus the MTTF at 245C is at least 2500 hours, and given an acceleration factor of AF = 43,692,
the projected MTTF at a channel temperature of 120C would be at least 1.1 x 10
8
hours, which is comparable to the result
for discrete MESFETs, assuming a comparable E
A
.
FSS MMICs also incorporate TaN thin-film deposited resistors and Si
3
N
4
metal-insulator-metal (MIM) capacitors,
which have been exposed to high temperature storage at 250C for 1000 hours. Observed changes in sheet resistance
and capacitance per unit area were both less than 3%. For a reliability estimate, taking 10% change as the definition of a
failure, the MTTF at 250C should then be at least 3000 hours, and the projected MTTF at 120C would then be 1.8 x 10
8
hours, although the activation energy for these two components was not verified.
Filtronic
Solid State
Device and Process Reliability 54
PHEMT Device Structure
The PHEMT structure used at FSS differs somewhat from the MESFET structure, as shown below:
The PHEMT device features a slimier Gate structure as the MESFET (i.e., the refractory Ti/Pt/Au system), but in
this device the Schottky contact is formed with AlGaAs (the Al mole fraction is <0.3), rather than doped GaAs. For
reduced Gate resistance, the a mushroom structure is formed by a direct-write electron-beam lithography process; each
Gate section measures 0.25m at its base. The use of a wider bandgap, less heavily doped contact material provides for
more Gate stability at high temperatures over long periods of time. By design, the AlGaAs layer is fully depleted of carriers
at zero applied Gate bias, and Drain-Source current flows in the 2-dimensional electron gas formed at the
AlGaAs/InGaAs heterojunction. The Source and Drain ohmic contacts are formed with the identical AuGe/Ni/Au ohmic
metallization system as used in the MESFET. All metallization systems are formed by an evaporation process, with
overplated Au; the devices are passivated as with the MESFETs.
The structure shown above is a Single Heterojunction PHEMT (SHPHEMT), which is a low-noise, low- power
dissipation design. FSS power PHEMT devices utilize a Double Heterojunction PHEMT structure (DHPHEMT), which
features two AlGaAs/InGaAs heterojunctions, one on each side of the InGaAs channel layer. The doping levels, mole
fractions, and layer thicknesses are based on proprietary designs developed by FSS to provide superior current and power
density performance.
AlGaAs / GaAs Superlattice
Undoped GaAs Buffer
InGaAs Channel Layer
N+ AlGaAs Layer (5 x 10
17
cm
-3
)
N++ GaAs Contact Layer
Drain
Contact
Source
Contact
Ti / Pt / Au Mushroom Gate
PHEMT STRUCTURE
Undoped AlGaAs Spacer
Heterojunction
Filtronic
Solid State
Device and Process Reliability 55
Discrete PHEMT Device Reliability
Reliability Study Test Device:
The device selected for the baseline PHEMT reliability study was a discrete DHPHEMT device, the LP7612, which
is a 0.25 x 200 m, -gate (non-interdigitated) design. This device features the following nominal performance:
RF Output Power at 1dB compression:
V
DS
= 5V, I
DS
= 50% I
DSS
, f = 18 GHz +21 dBm
RF Gain at 1 dB compression:
V
DS
= 5V, I
DS
= 50% I
DSS
, f = 18 GHz 8.5 dB
Minimum Noise Figure
V
DS
= 2V, I
DS
= 33% I
DSS
, f = 18 GHz 1.25 dB
Saturated Drain-Source current, I
DSS
: 65 mA
Pinch-Off Voltage at I
DS
= 1 mA, VP: -0.75 V
Gate-Drain Breakdown Voltage
at I
GD
= 1 mA, BV
GD
: -9 V
Gate-Source Leakage current
at VGS = -5V, I
GSO
: 1 A
The test devices were assembled into hermetically-sealed, ceramic packages, the P-70 stripline package, thereby allowing
insertion into test fixtures for characterization and high-temperature burn-in.
Experimental Protocol:
To establish the basic reliability parameters, a discrete DH-PHEMT wafer was randomly selected from FSSs
standard production material, and subjected to the usual lot screening procedures. The Lot Acceptance Inspection and
Quality Conformance Inspection screening procedures are detailed in FSSs Applications Notes, Discrete FET/PHEMT
Devices, Rev. A, Nov. 1996. A random group of 100 LP7612 devices was taken from this wafer, and subjected to the
following screening:
100% DC Parametric Testing (Go / No Go)
Visual Inspection
Die Attach into P-70 ceramic packages
Wire Bond
Lid Seal
Stabilization Bake (200C for 24 hrs, non-operating)
Pre Burn-In DC Test
DC Power Burn-In (T
CH
= 175C for 168 hrs)
Post Burn-In DC Test
Post Burn-In RF Test (S
21
at 12 GHz)
The primary goal of this effort was to determine the extrapolated MTTF at a 150C (channel temperature), based
on the assumption that the Arrhenius equation models the dominant failure mechanism. Randomly selected groups of the
packaged LP7612 devices were subjected to high-temperature DC power burn-in, at channel temperatures of 290, 275,
268, and 260C. Channel temperature was achieved by a combination of baseplate temperature and self-heating in the
devices. The LP7612 thermal resistivity had been previously characterized by use of direct-contact liquid crystal
thermography. The typical value is 300-310 C/W (at V
DS
= 3.0V) at room temperature, and is assumed to rise to
approximately 330C/W at the temperatures used for this experiment. (The thermal conductivity of GaAs decreases as a
function of temperature due to increased phonon scattering.)
Filtronic
Solid State
Device and Process Reliability 56
Each temperature group was continuously monitored during the burn-in, and periodically tested at room
temperature to determine if a failure had occurred. A failure was declared if a device exhibited any change in Saturated
Drain-Source current (I
DSS
), DC transconductance (g
M
), or pinch-off voltage (V
P
) greater than 15%, compared to the initial
values. Also monitored were: Gate-Drain and Gate-Source breakdown voltages (BV
GD
, BV
GS
), leakage current (I
GSO
) and
RF insertion gain at 12 GHz (S
21
). Bias conditions used for the high temperature burn-in were: V
DS
= 3.0V, I
DS
= 30 t 5
mA.
High-Temperature Burn-In Test System:
This test station uses three independent, proportionally-controlled hotplates, each with 10 test positions. All 30
test positions are independently controlled by a DC bias system under the overall control of a computer. Custom software
allows the setting of each test position to a desired drain-source voltage and operating current. This software allows for
automatic polling of all test positions at user-selected intervals during the burn-in. Thus a complete record of each
devices DC characteristics (I
DSS
, g
M
, V
P
, and I
GSO
) at temperature was kept, although only room temperature DC test data
was used for failure determination. The test devices were mounted with biasing circuits that served to suppress low-
frequency oscillations that can occur with high transconductance PHEMTs.
Results:
At the onset of the study, the failure criteria that were established to be as follows:
I
DSS
: > t 15%
g
M
: > t 15%
These criteria were selected based on a typical application of this device, as a small-signal gain element. Failures were
declared when either of these parameters had degraded or changed by more than the stated amount, compared to the
initial (zero time), room temperature values. As discussed previously, all other DC parameters were monitored and
measured during the course of the burn-in, although they were not used for failure declaration. During the course of the
experiment, it was discovered that the transconductance showed essentially little or no degradation, so this parameter was
not a factor. The following tables present the cumulative failures as a function of time for each experimental group:
Group #1: T
CH
= 290C V
DS
= 3.0V I
DS
= 40mA
Baseplate Temp. = 240C Number of Devices: 8
TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)
63 2 25
126 1 38
165 1 50
174 1 63
262 3 100
Group #2: T
CH
= 275C V
DS
= 3.0V I
DS
= 35mA
Baseplate Temp. = 240C Number of Devices: 18
TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)
195 6 33
261 1 39
307 1 44
349 1 50
424 1 56
465 2 67
727 3 83
Filtronic
Solid State
Device and Process Reliability 57
Group #3: T
CH
= 268C V
DS
= 3.0V I
DS
= 25mA
Baseplate Temp. = 240C Number of Devices: 8
TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)
769 2 25
1286 1 38
1562 2 63
Group #4: T
CH
= 260C V
DS
= 3.0V I
DS
= 25mA
Baseplate Temp. = 235C Number of Devices: 11
TIME (hrs.) FAILURES CUMULATIVE FAILURES (%)
359 1 9
656 1 18
664 1 27
1005 2 45
1013 1 55
1531 1 64
1800 1 73
Analysis:
Initial estimates of MTTF and shape factor for each group were made by plotting cumulative failures on log-
probability paper, and by graphically determining the best linear fit. This method gave the following results:
GROUP MTTF (hrs) SHAPE FACTOR ()
T
CH
= 290C 150 0.4
T
CH
= 275C 330 1.0
T
CH
= 268C 1350 0.7
T
CH
= 260C 1150 0.8
For a refinement of the MTTF estimates from this graphical method, each groups results were fitted to the IFR relationship
as given above, and this analysis is presented in the following series of graphs. The comparison between the theoretical
Instantaneous Failure Rate behavior and the actual experimental results serves several purposes: first, the IFR
relationship as presented assumes a single failure mechanism (i.e., no early failures), second, the graphically fitted
MTTF can be compared to the exact log-normal expression, and lastly the shape factor can be validated.
Filtronic
Solid State
Device and Process Reliability 58
GROUP #1 T
CH
= 290C FITTED IFR
IFR, MTTF=130 HR, SIGMA=0.76
0
0.001
0.002
0.003
0.004
0.005
0.006
0.007
0.008
0.009
25 50 75 100 125 150 175 200 225
TIME (HR)
I
F
R

(
H
R
)
GROUP #1 T
CH
= 290C AVERAGE FAILURE RATE
AFR
0
0.002
0.004
0.006
0.008
0.01
0.012
0.014
0.016
63 126 165 174 262
TIME (HR)
A
F
R

(
H
R
)
The peak failure rates are in rough agreement, 0.008 vs. 0.014, but the average rate peaks at 174 hrs. vs. the IFR peak at
115 hrs. No significant early failures are apparent.
Filtronic
Solid State
Device and Process Reliability 59
GROUP #2 T
CH
= 275C FITTED IFR
IFR, MTTF=350 HR, SIGMA=0.99
0
0.0005
0.001
0.0015
0.002
0.0025
0.003
25 125 225 325 425 525 625 725 825
TIME (HR)
I
F
R
,

(
H
R
)
GROUP #2 T
CH
= 275C AVERAGE FAILURE RATE
AFR
0
0.0002
0.0004
0.0006
0.0008
0.001
0.0012
0.0014
0.0016
0.0018
195 261 307 349 443 727
TIME (HR)
A
F
R
The IFR peak failure rate is significantly higher than the average rate, 0.0025 vs. 0.0014, but this group may have included
some early failures. The first monitoring interval at 195 hrs. revealed 6 failed devices, and it is likely that an earlier
monitoring time would have resolved the high average rate. The peak rates are at 225 vs. 349 hrs.
Filtronic
Solid State
Device and Process Reliability 60
GROUP #3 T
CH
= 268C FITTED IFR
IFR, MTTF=1350 HRS, SIGMA=0.72
0
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
10 250 500 750 1000 1250 1500 1750 2000
TIME (HR)
I
F
R

(
H
R
)
GROUP #3 T
CH
= 268C AVERAGE FAILURE RATE
AFR
0
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
769 1286 1562
TIME (HR)
A
F
R

(
H
R
)
The peak average failure rate compares well with the peak IFR, 0.0008 vs. 0.0009, with peak rates at 1250 vs. 1500 hrs.;
no average failure rate data was available after 1562 hrs.
Filtronic
Solid State
Device and Process Reliability 61
GROUP #4 T
CH
= 260C FITTED IFR
IFR, MTTF=1250, SIGMA=0.80
0
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
0.0009
5 250 500 750 1000 1250 1500 1750 1800
TIME (HR)
I
F
R

(
H
R
)
GROUP #4 T
CH
= 260C AVERAGE FAILURE RATE
AFR, TCH=260C
0
0.0001
0.0002
0.0003
0.0004
0.0005
0.0006
0.0007
0.0008
359 660 1009 1531 1800
TIME (HR)
A
F
R
The IFR and average failure rate plots are in good agreement, both in terms of peak rates, and peak rate time in hours.
No early failures were apparent.
Filtronic
Solid State
Device and Process Reliability 62
FILTRONIC SOLID STATE RELIABILITY
STUDY
LP7612 DISCRETE DHPHEMT ARRHENIUS PLOT
332
3.0E+08
150
1350
1150
1.0E+00
1.0E+01
1.0E+02
1.0E+03
1.0E+04
1.0E+05
1.0E+06
1.0E+07
1.0E+08
1.0E+09
1.0E+10
1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6
1/T ( x 10
-3
K
-1
)
MT
TF
(hr
s)
2.14 eV
290C
275C
268C
260C
150C
DC POWER BURN-IN
BIAS: V
DS
=3V I
DS
=35mA
DEVICE HOURS: >45,000
E
A
= 2.14 eV (BEST FIT)
EXTRAPOLATED MTTF
AT T
CH
= 150C
FIT RATE = 3.3
Filtronic
Solid State
Device and Process Reliability 63
MTTF Extrapolation and E
A
Estimate:
A least-squares linear fit to the results of the four experimental results yields the Arrhenius plot shown on the
preceding page, giving an extrapolated MTTF at T
CH
= 150C of 3.0 x 10
8
hrs, with and Activation Energy estimate of 2.14
eV. This MTTF corresponds to a 3.3 FITs average failure or hazard rate.
The Characteristics of PHEMT Aging:
The PHEMT device shows exceptional stability at high temperatures, especially with regard to transconductance
and RF power gain (S
21
). The majority of the experimental devices showed little or no degradation in g
M
, and typically less
than 0.5 dB change in Insertion Gain (S
21
), which was measured at 12 GHz. It may be inferred from the S
21
measurements that the g
M
vs. V
GS
characteristic (transfer curve) is stable during aging. If used in a self-biased amplifier
circuit (DC-grounded Gate, DC-floated Source), the additional stabilization of the operating current from the bias resistors
will result in excellent bias point stability. Typical aging effects are shown below on one of the devices from the 275C
group:
T
CH
= 275C, S/N 9
0
10
20
30
40
50
60
70
80
90
100
0 131 195 261 349 465
TIME (hrs)
GM (mS)
IDSS (mA)
VP (mV)
BVGD (V)
BVGS (V)
IGSO (uA)
This particular device exhibited +0.3 dB of change in S
21
over the course of the burn-in, implying stability of the g
M
at the
nominal RF bias point of I
DS
= 50%I
DSS
. Most of the experimental devices in the four groups showed an increase in S
21
over the duration of the burn-in, typically 0.2 to 0.5 dB (despite significant degradation of the package leads). This g
M
stability can be related to the PHEMTs transconductance expression:
g
v Z
d d
M
sat s
i

where v
sat
= saturated carrier velocity, Z = Gate width,
S
= semiconductor dielectric constant, d+d
i
= AlGaAs layer
thickness. The AlGaAs layer thickness is fixed at the time of the epitaxial growth, and to first order, does not change with
device aging. By contrast, the MESFET expression contains the depletion layer depth as follows:
( )
g
v Z
h
where h
V x V V
q N
M
sat s
s G bi
D

+ +

:
( ) 2
Filtronic
Solid State
Device and Process Reliability 64
where h = depletion depth, V(x) = potential along channel, V
G
= applied Gate voltage, V
bi
= Schottky contact built-in
voltage, q = electron charge, and N
D
= active layer doping. The gate sinking mechanism can cause localized
compensation of the MESFETs active layer doping, thereby altering the N
D
term. The MESFET is sensitive to any
changes in the depletion layer depth, whatever the cause, whereas the PHEMT fundamentally is less sensitive.
Both devices, however, can exhibit changes in IDSS as channel parameters change, as seen in the following
expressions:
( )
PHEMT I
v Z V
d d
MESFET I q v Z a h N
DSS
sat s P
i
DSS sat bi D
: :
+

where: V
P
= Pinch-Off voltage, a = active layer (channel) depth, and h
bi
= built-in (zero bias) depletion depth. For the
PHEMT, if the pinch-off voltage is dependent on the Schottky contact built-in voltage (and therefore to the barrier height),
while the MESFET expression contains dependencies on both the contact properties as well as the active layer doping.
(Note that the I
DSS
of the 275C sample PHEMT tracks V
P
closely.)
Hydrogen Sensitivity
FSS LP7612 discretes have been studied as to their sensitivity to molecular hydrogen (H
2
), a potential concern for
hermetically sealed long-duration space flight applications. Amplifiers and linearizers built with LP7612s were exposed to
various hydrogen concentrations (up to 4%), at elevated temperatures for times exceeding 2,000 hrs. These experiments
demonstrated that, with suitable circuit topologies (e.g., self-biased), components built with FSS devices could perform
acceptably over a mission duration of 15 years or more.
S-Level Qualification of PHEMTs
FSS LP7612 PHEMT devices have been repeatedly qualified to MIL-STD-19500 JANS grade, for use in space
flight hardware. LP7612 discretes are presently in-flight on a number of telecommunications satellites. Key elements of
this qualification procedure included a 240 hour DC operating high-temperature burn-in, and a 1000 hour operating life
test. Failures were defined as devices exhibiting changes greater t15% (1000 hour life test) or t20% (240 hour burn-in) in
I
DSS
, g
M
, or V
P
, and t0.5 dB change in the power gain (S
21
) at 12 GHz. A separate limit of t100% or 1 A (whichever was
greater) was imposed for the reverse leakage current (I
GSS
). Samples of the wafer lot under evaluation must complete both
the 240 hour burn-in, at a channel temperature of 225C, and a 1000 hour life test at a channel temperature of 150C; the
sampling method is based on LTPD (Lot Tolerance Percent Defective) levels of 30% and 50%.
PHEMT MMIC Reliability
MMICs based on the DHPHEMT active device technology are currently undergoing reliability testing at FSS,
following the discrete PHEMT results. The LMA411, a two-stage, self-biased, low noise MMIC, has demonstrated
exceptional stability at a 275C channel temperature, with a MTTF exceeding 800 hrs. This channel temperature was
achieved with a 240C baseplate temperature in addition to self-heating. Operating current changes were less than 5%,
and the small-signal gain degraded less than 0.3dB for all test devices. The self-biased circuit topology is resistant to
changes in I
DSS
and V
P
, so these results are consistent with the discrete results. All of the test MMICs suffered severe
physical deterioration due to the extremely high baseplate temperature; the testing was discontinued after it became
apparent that the package and off-chip components could not withstand the test conditions.
Filtronic
Solid State
Device and Process Reliability 65
Fabrication Process Stability
All FSS discrete and MMIC devices are fabricated by essentially identical processes. The epitaxial specifications
and evaluation criteria, fabrication processes and test methods, and DC/RF test specifications and test methods are fully
documented. Statistical Process Control (SPC) methods are utilized to monitor the fabrication processes, with key
parameters continuously tracked on trend charts. The Division is quality certified to ISO 9001 standards. All discrete and
MMIC wafers and wafer lots are evaluated and screened by a tailored MIL-19500 JANC screening procedure, as detailed
in FSSs Applications Notes, Discrete FET/PHEMT Devices, Rev. A, November 1986.
Current Reliability Characterization Effort:
FSS is continuing its assessment of the reliability of its devices, and the following experiments are planned:
Accumulation of additional LP7612 high-temperature Arrhenius data
Reliability of large gate periphery discrete devices
Effects of RF drive (to 1dB compression levels) on reliability
Verification of degradation mechanisms by microscopic analysis (e.g., Auger and SIMS)
Effects of high RF power level exposure, pulsed and CW, to 5W levels
Prepared By:
Michael Jon Bailey
Product Engineering Manager
Reviewed By:
Bill Ireton
Manager of Semiconductor Operations