Tao Cheng Dept.

of Information Technology, UTU 5/29/2008

ETT_3047 RF ANALOG IC DESIGN PROJECT







CONTENT
1. PROJECT DESCRIPTION.......................................................................................................2
2. SPECIFICATIONS AND PROCESS PARAMETERS............................................................2
3. LNA PARAMETERS DESIGN..................................................................................................3
3.1 LNA Architecture ..............................................................................................................3
3.2 Short-Channel Effects For MOS Transistors .................................................................3
3.2.1 Mobility Degradation With Vertical Field................................................................3
3.2.2 Velocity Saturation...................................................................................................4
3.3 Input/Output Impedance Matching ................................................................................4
3.4 Equivalent Transconductance of LNA............................................................................5
3.5 Voltage Gain of LNA.........................................................................................................6
3.6 Noise Analysis ....................................................................................................................6
3.6.1 Calculation of output noise due to i
ng1
......................................................................6
3.6.2 Calculation of output noise due to i
nd1
......................................................................8
3.6.3 Noise Figure Calculation..........................................................................................8
3.7 Devices Size Selection........................................................................................................9
4. SIMULATION RESULTS........................................................................................................ 11
5. REFERENCES..........................................................................................................................13
6. APPENDIX A: MATLAB CODE.............................................................................................14















Tao Cheng Dept. of Information Technology, UTU 5/29/2008
1. PROJECT DESCRIPTION
This project is to design a classic Narrow Band Cascode Low Noise Amplifier (LNA) with Inductive
Source Degeneration based on publication [5].
2. SPECIFICATIONS AND PROCESS PARAMETERS
Table 2.1 LNA Design Specifications
SPECS DESCRIPTION VALUES
f0 (GHz) Operation Frequency 2
Av (dB) Voltage Gain 20
S11 (dB) S11 -10
NF (dB) Noise Figure 4
IIP3 (dBm) Input 3
rd
Intercept Point -10
P1dB (dBm) Input 1-dB Compression Poin 0
Pdiss (mW) Power Dissipation < 10
Vdd (V) Power Supply 1.2
C2 (fF) Capacitive Loading 20
Technology 0.13um CMOS
Table 2.2 Process Parameters
PARAMETERS DESCRIPTIONS VALUES
V
thn
Threshold voltage 0.36 (V)

n
Mobility of carrier 0.0311 (m
2
/v/s)
v
sat
Saturation velocity of carrier 1e5 (m/s)
t
ox
Thickness of oxide 2.5e-9 (m)
mobility Degradation factor by vertical fields (10
-7
/t
ox
) 40 (V
-1
)
















Tao Cheng Dept. of Information Technology, UTU 5/29/2008
3. LNA PARAMETERS DESIGN
3.1 LNA Architecture
Vo
L3
L2
C1
Rs=50
Vi
M2
M1
L1
R3
C3
C2 L4

Fig 3.1 LNA Architecture with Source Degenerative Inductor
Fig 3.1 shows the circuit of the designated LNA. For simplicity, bias circuit is not shown here. M
1
and
M
2
in the figure form a cascode structure to reduce the output signal feed-through to the input due to
gate-drain capacitance of M
1
.
1 1 m gs
g v
2 2 m gs
g v
2 gs
v
1 gs
v
2 2 mb gs
g v
1 L
v
1 1 mb L
g v

Fig 3.2 Small Signal Equivalent Circuit of LNA
C
1
is input coupling capacitors. C
2
is capacitive loading. L
1
, L
2
and C
gs1
form an input impedance
matching network to realize maximum power delivery at resonance. Output type- matching network
consists of L
3
, C
3
and L
4
. In practice, C
3
may need to be tunable to compensate parasitic effects. A
relatively complete small signal equivalent model of Fig 3.1 is provided by Fig 3.2. R
2
is the total
series parasitic resistance of L
2
and M
1
gate which is neglected in the following analysis.
3.2 Short-Channel Effects For MOS Transistors
There are two kinds of important short-channel effects which should be mentioned here in order to
validate our later analysis: mobility degradation with vertical field and velocity saturation.
3.2.1 Mobility Degradation With Vertical Field
Small-geometry devices experience significant mobility degradation due to the high vertical electric
field because large gate-source voltage confines the charge carriers to a narrow region below the
oxide-silicon interface leading to more carriers scattering and hence lowering the mobility. An
empirical equation modeling this effect is [1]:
Tao Cheng Dept. of Information Technology, UTU 5/29/2008

( )
0
1
eff
gs th
V V

=
+
, (
7
10
ox
t

= ) (3.01)
In which is a fitting parameter [2]. Thus, in linear region of MOS transistor, the drain-source current
should be modified as:

( )
( )
( )
0 2
1
2
1
ox
ds gs th ds ds
gs th
C W L
I V V V V
V V

=

+
(3.02)
The drain-source conductance at the point of V
ds
=0 is:

( )( )
( )
0
0 0
1
ds
ox gs th
ds
d V
ds gs th
C W L V V
I
g
V
V V

=

= =
+
(3.03)
3.2.2 Velocity Saturation
The mobility of carriers also will degrade when lateral electric field approaches a sufficiently high level
because the velocity of carriers is going to saturate under this condition [1]. A compact and versatile
equation developed to represent the saturation drain-source current considering the effects of large
vertical and lateral electric fields is given by:

( )
( )
2
0
0
1
2
1
2
gs th
ds ox
gs th
sat
V V
W
I C
L
V V
v L

=

+ +


(3.04)
Where v
sat
is the saturation velocity of carriers. The degradation of mobility with both lateral and
vertical electric fields are represented by parameters and u
0
/(2v
sat
L).
3.3 Input/Output Impedance Matching
The circuit of input impedance calculation is shown in Fig 3.3(a) in which the total series parasitic
resistance of L
2
and M
1
gate is neglected to simplify the analysis. According to KVL, we have:
( )
1 2 1 2 1 1 1
1
1
x gs L L x x m gs
gs
v v v v i sL i g v sL
sC

= + + = + + +



( )
1
1 2 1
1 1
1
x m
i
x gs gs
v g
Z s L L L
i sC C
= = + + + (3.05)
In order to maximize the power transfer at resonant frequency, the real part of Z
i
must be equal to R
s

and the imaginary part must be equal to zero, which gives:

( )
( ) ( )
( )
1
1 1 1 1
1
2
0 1 2 0
0 1 1 2 1
Re
1 1
Im 0
m
i s m gs s
gs
i
gs gs
g
Z L R g L C R
C
Z L L
C L L C

= = =

= + = =

(3.06)
The input quality factor Q
i
is:
Tao Cheng Dept. of Information Technology, UTU 5/29/2008

( )
0 1 2
0
1 1
0
1 1
2 2
i
gs s s
m
gs s
gs
L L
Q
C R R
g L
C R
C

+
= = =

+


(3.07)
1 1 m gs
g v
2 2 m gs
g v
2 gs
v
1 gs
v
1 1 m gs
g v
2 2 m gs
g v
2 gs
v
1 gs
v

(a) Zi Calculation (b) G
m
Calculation
Fig 3.3 Equivalent Circuit for Input Impedance Z
i
and Transconductance Gm Calculation
At the output port, L
3
,C
3
and L
4
forms an output matching network when circuit is resonating, their
sizes are calculated with the help of CAD tool RFSIM99 [7].
3.4 Equivalent Transconductance of LNA
The circuit of equivalent transconductance calculation is shown in Fig 3.3(b), to evaluate equivalent
transconductance G
m
, the following equation can be given:

( ) ( )
1 1
1 1 2 1 1 1 1 1 1
y m gs
i gs gs s gs m gs gs gs
i g v
v sC v R sL v sL g v sC v
=

= + + + +

( ) ( )
( ) ( )
1
2
1 1 1 1 1 2
1
y
m
m
i m s gs gs
i
g
G j j
v
j g L R C C L L


= =
+ + +
(3.09)
Noting (3.06) and (3.07), G
m
at resonant frequency is then got by plugging the two equations into the
(3.09):
( )
1
,0 0 1
0 1 0 0 1
1
2 2 4
m T
m m m i
s gs s
g f
G G j g Q
R C f R f L

= = = = (3.10)
0.2
0.4
0.6
0.8
1 0
0.2
0.4
0.6
0.8
0
100
200
300
400
Vgs-Vth (V)
Cut-off Frequency .vs. Vgs-Vth
L (um)
f
T

(
G
H
z
)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
-0.05
0
0.05
0.1
0.15
0.2
Vgs-Vth (V)
A
f
=
f
0
/
f
t
Af .vs. Vgs-Vth


0
=0

Fig 3.4 f
T
.vs. V
gs
-V
th
Determined By (3.11) Fig 3.5
f
.vs. V
gs
-V
th

Tao Cheng Dept. of Information Technology, UTU 5/29/2008
Where f
T
g
m1
/(2C
gs1
) is the cut-off frequency of NMOS transistors. Since C
gs1
(2/3)WLC
ox
,
g
m1
=u
n
C
ox
(W/L)(V
gs
-V
th
), so f
T
is given by (3.11) and its relation with L & V
gs
-V
th
is shown in Fig 3.4:

( )
( )
2
3
440 (GHz)
4
n gs th
T gs th
V V
f V V
L

(3.11)
3.5 Voltage Gain of LNA
The voltage gain is given by:
( ) ( )
3 3
3 1 3
0
20log 20log 20log 20log
2 2
T
v m m i
s f s
f R R
A G R g Q R
f R R


= = = =




(3.12)
In which
f
=f
0
/f
T
. The variation of
f
with overdrive voltage is shown in Fig 3.5. Given the spec. of
20dB voltage gain, we have:

3
20log 20
2
v
f s
R
A
R

=



3
20 1000
f s f
R R = (3.13)
From Fig 3.5 we can see that minimum
f
is about 0.06 and 0.01 at 0 and =0 respectively, so
minimum R
3
should be larger than 60 and 10.
3.6 Noise Analysis
Fig 3.6 shows the key noise sources [3][4] for the simplified small signal equivalent circuit given by
Fig 3.2 in which i
ng1
is gate induced noise current, i
nd1
is channel noise current of M
1
including thermal
and flicker noise and i
no,LNA
is the total equivalent output noise current due to i
ng1
and i
nd1
. The noise
caused by cascode transistor M
2
can be neglected [1].
1 1 m gs
g v
1 gs
v
2
ns
v
2
1 ng
i
2
1 nd
i
1 L
v
1 1 m gs
g v
1 gs
v
2
ns
v
2
, no LNA
i
1 L
v

Fig 3.6 Noise Model of LNA
The values of i
ng1
and i
nd1
are given by:

2 2
1 2
1
0
4 4
5
gs
ng g
d
C
i kT g kT
g

= = ,
2
1 0
4
nd d
i kT g = (3.14)
Where typically =2=6. g
d0
, the drain-source resistance of M
1
at V
ds
=0, is given by (3.03) and g
m1
, the
transconductance of M
1
, is determined by the derivative of I
ds
with V
gs
in (3.04). Fig 3.7 shows the
relation between V
gs
-V
th
and g
m1
, g
d0
and the ratio
g
of g
m1
and g
d0
with and without consideration of .
3.6.1 Calculation of output noise due to i
ng1

In order to get i
ng1
induced output noise, we should firstly calculate Z
gs1
. The circuit for Z
gs1
calculation
is shown in Fig 3.8(a). We have:
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
2
4
6
8
10
12
14
16
Vgs-Vth (V)
g
m
1

(
m
S
)
gm1 & gd0 .VS. Vgs-Vth (0)


gm1
gd0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
Vgs-Vth (V)

g
=
g
m
1
/
g
d
0
g .VS. Vgs-Vth (0)

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
100
200
300
400
500
600
Vgs-Vth (V)
g
d
0

&

g
m
1

(
m
S
)
gm1 & gd0 .VS. Vgs-Vth (=0)


gm1
gd0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
Vgs-Vth (V)

g
=
g
m
1
/
g
d
0
g .VS. Vgs-Vth (=0)

Fig 3.7 V
gs
-V
th
.vs. g
m1
, g
d0
and V
gs
-V
th
.vs.
g
(W=200um, L=0.13um, )
1 1 1
1 1
1
2 1
x L gs x m x
x L L
m x
s
i v sC v g v
v v v
g v
sL R sL
+ = +

+
+ =

( )
( )
( ) ( )
1 2
2
1 2 1 1 1 1
1
s x
x gs m s gs
R j L L v
j
i
L L C j g L R C

+ +
=
+ + +
(3.15)
At resonant frequency point, plug the result of (3.06) and (3.07) into the above equation:
( ) ( )
1 0
2
x
gs s i i
x
v
Z j R Q Q j
i
= =
2
1
1 4
gs s i i
Z R Q Q = + (3.16)
Then:

, 1 1 1 1 1 1 no g m gs ng g ng
i g Z i i = = (3.17)
In which

1 1 1 g m gs
g Z =
2
1 1 1 1
1 4
g m gs m s i i
g Z g R Q Q = = + (3.18)
Cgs1
L1
1 1 m gs
g v
1 gs
v
L2
Rs=50
Zgs1
1 L
v
Vx
Ix
Cgs1
L1
1 1 m gs
g v
1 gs
v
L2
Rs=50
1 L
v
2
1 nd
i
2
, 1 no d
i

Fig 3.8 i
no,tot
Calculation (a) Circuit for Z
gs1
Calculation (b) Circuit for i
no,d1
Calculation
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
3.6.2 Calculation of output noise due to i
nd1

The circuit for i
no,d1
Calculation is shown in Fig 3.8(b). We have:

( )
( )
( )
( )
1
1 1
1 , 1 1 2 1
1
2 1
, 1 1 1 1
||
gs
gs no d s gs
s gs
no d m gs nd
sC
v i sL R sL sC
R sL sC
i g v i

= + +

+ +

= +

( )
( )
( ) ( )
2
1 2 1 1 , 1
2
1
1 2 1 1 1 1
1
1
gs s gs no d
nd
gs m s gs
L L C j R C i
j
i L L C j g L R C

+ +
=
+ + +
(3.19)
At resonant frequency point, plug the result of (3.06) and (3.07) to the above equation and we can get:
( )
1 , 1
1 0
1 1 1 1
1
2
s gs no d
d
nd m s gs
R C i
j
i g L R C
= = =
+

1
1
2
d
= (3.20)
Then the expression of i
no,tot
is:
{ }
2 * * * * 2 2 2 2 * *
, 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2Re
no LNA g ng d nd g ng d nd g ng d nd ng nd d g
i i i i i i i i i


= + + = + +



{ }
2 2
1 1 2 2 2 2 2 2 * 2 2 2
1 1 1 1 1 1 1 1 1 1 1 1 1
2 2
1 1
2Re 2Re
ng ng
g ng d nd ng nd g d nd d g d g
nd nd
i i
i i c i i i c
i i



= + + = + +





( )
2 2 2 2
0 1 0 1 2 2 2 2 2 2
1 1 1 1 1 1
2 2
0 0
1 4 2Re
5 5
gs gs
nd d m s i i d m gs
d d
C C
i g R Q Q j c g Z
g g





= + + +



( )
2 2
2 2 1 1
1 1 1 0 1
2
0 0
1 4
2 Re 1 2
5 4 5
m i m
nd d d gs s i i
d d
g Q g
i C R Q c j Q
g g




+
= + +





( )
2 2 2 2
1 1 1
1
1 4
4
nd d i d
i Q c

= + +


(3.21)
In which

*
1 1
2 2
1 1
1
2
ng nd
ng nd
i i
c j
i i

,
2
2
2 1
2
0
5 5
g
m
d
g
g

= = (3.22)
3.6.3 Noise Figure Calculation
The output noise due to input source is:

2 2 2 2 2
, 1
4
no src m ns m i s
i G v g Q kTR = = (3.23)
The noise factor of the designated LNA is:

( )
2 2 2
2
1 1 0
,
2 2
2
1
,
1
1 4 4
4
1 1
4
d i d d
no LNA
m i s
no src
Q c kT g
i
F
g Q kTR
i


+ +


= + = +

( )
2 2 2 0
1 1
1 1
1 1
1 1 4
4
d
d i d
m i s i m
g
Q c
g Q R Q g

= + + +



Tao Cheng Dept. of Information Technology, UTU 5/29/2008

( )
2 2 2
1 1
,0
1
1 1 4
4
d i d
m s g i
Q c
G R Q

= + + +




( )
2 2 2 0
1 1
1
1 1 4
4
d i d
g i T
f
Q c
Q f

= + + +




( )
2 2 2
1
1 0.5 1 4 0.5
4
f
i
g i
Q c
Q

= + + +




( )
2 2
1 1 2 1 4
4
f
i
g i
c Q
Q

= + + +

(3.24)
In which
f
=f
0
/f
T
. For short-channel devices, typically is equal to 2~3 depending on bias condition [6]
and =2. In this design, we set =3, =6, so (3.19) changes to:

( )
2 2
6
1 1 2 0.4 0.5 0.4 1 4
4
f
g g i
g i
F Q
Q

= + + +



( )
2 2
1 1.5 1 0.4 0.4 1 4
f
g g i
g i
Q
Q

= + + +

(3.25)
Fig 3.9 and Fig 3.10 shows the relation of power dissipation and noise figure and overdrive voltage.
0 0.05 0.1 0.15 0.2 0.25 0.3
0
5
10
15
20
25
30
Vgs-Vth (V)
P
d
i
s
s

(
m
W
)
Pdiss .vs. Vgs-Vth


W=50um
W=100um
W=150um
W=200um

0 0.05 0.1 0.15 0.2 0.25 0.3
0
1
2
3
4
5
6
Vgs-Vth (V)
N
F

(
d
B
)
NF .vs. Vgs-Vth


W=50um
W=100um
W=150um
W=200um

Fig 3.9 Pdiss .vs. V
gs
-V
th
Fig 3.10 NF .vs. V
gs
-V
th

3.7 Devices Size Selection
According to the specifications and the above analysis, we can calculate the detailed devices
parameters. First, we select (W
1
/L
1
)=(W
2
/L
2
)=200m/0.13m (channel width can not be too small,
otherwise the L
2
in input matching network might be too large to be integrated), (V
gs
-V
th
)=0.1V, so
g
m1
55mS, C
gs1
240fF.
From (3.06), L
1
=R
s
C
gs1
/g
m1
0.22nH, L
2
=[(2f
0
)
2
C
gs1
]
-1
-L
1
26.2nH. From Fig (3.5),
f
0.01, so R
3

must be larger than 10 according to (3.13). Here we set R
3
=180. As for L
3
, C
3
and L
4
, using
RFSIM99, the calculated results are L
3
=2.87nH, C
3
=1.53pF and L
4
=1.6nH under the bandwidth of
400MHz. The following Table 3.1 summaries the result of our design parameters.

Tao Cheng Dept. of Information Technology, UTU 5/29/2008
Table 3.1 Design Parameters
W1/L1 200 m/0.13 m Vgs-Vth 100 mV
W2/L2 200 m/0.13 m Ibias 0.13 mA
L1 0.22 nH C1 10 pF
L2 26.2 nH C2 20 fF
L3 2.87 nH C3 1.5 pF
L4 1.60 nH R3 180





































Tao Cheng Dept. of Information Technology, UTU 5/29/2008
4. SIMULATION RESULTS
This section gives the complete schematic and simulated results of designated LNA under typical
corner. Table 4.1 and 4.2 summarize the final simulated device sizes and performance.

Fig 4.1 Schematic of Source Degenerated LNA


Tao Cheng Dept. of Information Technology, UTU 5/29/2008

Fig 4.2 Waveform of S-parameters, Voltage Gain, Noise Figure IP3 and P1dB

Fig 4.3 Transient Waveform of LNA
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
Table 4.1 Device Sizes
W1/L1 25*8 m/0.13 m W0/L0 8 m/0.13 m
W2/L2 25*8 m/0.13 m W4/L4 8 m/0.13 m
Vgs-Vth 90 mV Ibias 0.24 mA
L1 0.30 nH C1 10 pF
L2 16.9 nH C2 20 fF
L3 2.40 nH C3 1.53 pF
L4 1.60 nH R3 180
Table 4.2 Simulated Performace
S11/S22/S21/S12 -22/-22/23/-35 dB Gain 28 dB
IIP3/OIP3 -13.2/9.9 dBm NF 0.12 dB
Input/Output P1dB -26.38/-4.34 dBm Pdiss <9.5 mW















5. REFERENCES
[1] B. Razavi, Design of Analog CMOS Integrated Circuits, Singapore: McGraw Hill, 2001.
[2] C. G. Sodini, P. K. Ko and J. L. Moll, The Effect of High Fields on MOS Device and Circuit
Performance, IEEE Tran. On Electron Devices, Vol.31, pp.1386-1393, Oct.1984.
[3] J. S. Goo, High Frequency Noise in CMOS Low Noise Amplifiers, PhD Thesis, Stanford
University, Aug.2001.
[4] T. Sepke, Investigation of Noise Sources in Scaled CMOS Field-Effect Transistors, MS Thesis,
MIT, Jun.2002.
[5] D. K. Shaeffer, T. H. Lee, A 1.5-V, 1.5-Ghz CMOS Low Noise Amplifier, IEEE JSSC, Vol.32,
No.5, May 1997.
[6] A. A. Abidi, High-Frequency Noise Measurements on FETs with Small Dimensions, IEEE
Transactions on Electron Devices, Vol.ED-33, No.11, Nov. 1986.
[7] RFSIM99, http://www.rfglobalnet.com/
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
6. APPENDIX A: MATLAB CODE
%function ett3047_prj
%-----------------------------------------------------------------------------
%[DESCRIPTION]
% This program implements the following main functions:
% 1)Plot the gm1,gd0 and gm0/gd0 .vs. (vgs-vth)
% 2)Plot f0/ft .vs. (vgs-vth)
% 3)Plot NF .vs. (vgs-vth)
% 4)Plot Pdiss .vs. (vgs-vth)
%
%[USAGE]
% ett3047_prj
%
%[AUTHOR]
% Tao Cheng
%[DATE]
% 2008.05.30
%-----------------------------------------------------------------------------
%clear all;
%clc;
% Channel Width & Length of NMOS Transistor
W=200e-6;
L=0.13e-6;
% Threshold Voltage of NMOS Transistor
Vth=0.36;
% Supply Voltage
Vdd=1.2;
% Mobility of Long-Channel NMOS Transistor
U0=0.0311;
% Gate-Oxide Thickness
Tox=2.5e-9;
% Gate-Oxide Capacitance
Cox=3.9*8.85e-12/Tox; % Cox=0.0138F/(m*m)
% Gate-Source and Gate-Drain Capacitance for Saturated NMOS Transistor
Cgs=(2/3)*W*L*Cox; % Cgs=240fF
% Impedance of Input Voltage Source
Rs=50;
% Load Impedance
R3=75;
% Operation Frequency of LNA
f0=2e9;
% A Fitting Parameter For Degradation of Mobility By Vertical Fields
Thita=1e-7/Tox;
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
% Saturation Velocity of Carriers For Degradation of Mobility By Lateral Fields
Vsat=1e5;
% Effects of Combination "Thita" & "Vsat"
Thita0=Thita+U0/(2*Vsat*L); % "Thita" is considered
Thita1=U0/(2*Vsat*L); % "Thita" is not considered
% Setup the Range of Gate-Source Voltage
Vgs=[Vth:0.01:Vdd];

% The Drain-Source Current Considering Mobility Degradation Effects (mA)

Id0=inline('1e3*0.5*U0*Cox*(W/L)*(Vgs-Vth).^2./(1+Thita0*(Vgs-Vth))','Vgs','Vth','U0',
'Cox','W','L','Thita0');

Id1=inline('1e3*0.5*U0*Cox*(W/L)*(Vgs-Vth).^2./(1+Thita1*(Vgs-Vth))','Vgs','Vth','U0',
'Cox','W','L','Thita1');
% Transconductance of NMOS Transistor
gm0=diff(Id0([Vgs,1.21],Vth,U0,Cox,W,L,Thita0))/0.01;
gm1=diff(Id1([Vgs,1.21],Vth,U0,Cox,W,L,Thita1))/0.01;
% Drain-Source Conductance at Vds=0
gd0=1e3*U0*Cox*(W/L)*(Vgs-Vth)./(1+Thita0*(Vgs-Vth)); % "Thita" is considered
gd1=1e3*U0*Cox*(W/L)*(Vgs-Vth); % "Thita" is not considered
% Ratio of "gm0" and "gd0"
Ag0=gm0./gd0; % "Thita" is considered
Ag1=gm1./gd1; % "Thita" is not considered
% Cut-off Frequency of NMOS Transistor
ft0=1e-3*gm0/Cgs; % "Thita" is considered
ft1=1e-3*gm1/Cgs; % "Thita" is not considered

% Ratio of "f0" and "ft"
Af0=f0./ft0; % "Thita" is considered
Af1=f0./ft1; % "Thita" is not considered
% Input Quality Factor of LNA
Qi=1/(4*pi*f0*Cgs*Rs);
% Input Quality Factor of LNA .vs. W
W1=1e-6*[30:10:200];
Cgs1=(2/3)*W1*L*Cox;
Qi1=1./(4*pi*f0*Cgs1*Rs);
% Equivalent Transconductance Gm of LNA
Gm0=gm0*Qi; % "Thita" is considered
Gm1=gm1*Qi; % "Thita" is not considered

% Voltage Gain Av
Av0=20*log10(Gm0*R3/1e3); % "Thita" is considered
Av1=20*log10(Gm1*R3/1e3); % "Thita" is not considered
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
% Noise Factor and Noise Figure of LNA
F0=1+1.5*Af0./(Ag0.*Qi).*(1-sqrt(0.4).*Ag0+0.4*Ag0.^2.*(1+4*Qi.^2)); % "Thita" is
considered
F1=1+1.5*Af1./(Ag1.*Qi).*(1-sqrt(0.4).*Ag1+0.4*Ag1.^2.*(1+4*Qi.^2)); % "Thita" is not
considered
NF0=10*log10(F0); % "Thita" is considered
NF1=10*log10(F1); % "Thita" is not considered
% Power Dissipasion
Pdiss0=Vdd*Id0(Vgs,Vth,U0,Cox,W,L,Thita0); % "Thita" is considered
Pdiss1=Vdd*Id1(Vgs,Vth,U0,Cox,W,L,Thita1); % "Thita" is not considered

% Plot Curves
%--------------------------------------------------------------------------
% Plot gm0,gd0,Ag0;gm1,gd1,Ag1;
%figure(1);
%subplot(2,2,1);
%plot(Vgs-Vth,gm0,'r',Vgs-Vth,gd0,'b');grid on;
%xlim([0 0.8]);%ylim([-50 300]);
%xlabel('Vgs-Vth (V)');ylabel('gm1 (mS)');
%subplot(2,2,2);
%plot(Vgs-Vth,Ag0,'b');grid on;
%xlim([0 0.8]);%ylim([0.4 1.1]);
%xlabel('Vgs-Vth (V)');ylabel('Ag');
%subplot(2,2,3);
%plot(Vgs-Vth,gm1,'r',Vgs-Vth,gd1,'b');grid on;
%xlim([0 0.8]);%ylim([-50 300]);
%xlabel('Vgs-Vth (V)');ylabel('gm1 (mS)');
%subplot(2,2,4);
%plot(Vgs-Vth,Ag1,'b');grid on;
%xlabel('Vgs-Vth (V)');ylabel('Ag');
%xlim([0 0.8]);%ylim([-50 300]);

%figure(1);
%plot(Vgs-Vth,gm0,'r',Vgs-Vth,gd0,'b');grid on;
%xlim([0 0.8]);%ylim([-50 300]);
%xlabel('Vgs-Vth (V)');ylabel('gm1 (mS)');
%title('gm1 & gd0 .VS. Vgs-Vth (0)');
%figure(2);
%plot(Vgs-Vth,Ag0,'b');grid on;
%xlim([0 0.8]);%ylim([0.4 1.1]);
%xlabel('Vgs-Vth (V)');ylabel('Ag');
%title('Ag0 .VS. Vgs-Vth (0)');
%figure(3);
%plot(Vgs-Vth,gm1,'r',Vgs-Vth,gd1,'b');grid on;
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
%xlim([0 0.8]);%ylim([-50 300]);
%xlabel('Vgs-Vth (V)');ylabel('gm1 (mS)');
%title('gm1 & gd0 .VS. Vgs-Vth (=0)');
%figure(4);
%plot(Vgs-Vth,Ag1,'b');grid on;
%xlabel('Vgs-Vth (V)');ylabel('Ag');
%xlim([0 0.8]);%ylim([-50 300]);
%title('Ag0 .VS. Vgs-Vth (=0)');
%--------------------------------------------------------------------------
% Plot Af;
%figure(2);
%plot(Vgs-Vth,Af0,'b',Vgs-Vth,Af1,'r');grid on;xlim([0 0.8]);ylim([-0.05 0.2]);
%xlabel('Vgs-Vth (V)');ylabel('Af=f0/ft');
%title('Af .vs. Vgs-Vth');

%figure(2);
%plot(Vgs-Vth,Af0,'b');grid on;xlim([0 0.8]);%ylim([0.04 0.2]);
%xlabel('Vgs-Vth (V)');ylabel('Af=f0/ft');
%title('Af .vs. Vgs-Vth (=0)');
%figure(3);
%plot(Vgs-Vth,Af1,'b');grid on;xlim([0 0.8]);%ylim([0.04 0.2]);
%xlabel('Vgs-Vth (V)');ylabel('Af=f0/ft');
%title('Af .vs. Vgs-Vth (0)');
%--------------------------------------------------------------------------
% Plot ft;
%figure(3);
%[L2,Vgs2]=meshgrid(1e-6*[0.13:0.05:1],[Vth:0.05:Vdd]);
%Cgs2=(2/3)*W*L2*Cox;
%gm2=U0*Cox*(W./L2).*(Vgs2-Vth);
%ft2=gm2./(2*pi*Cgs2);
%surf(L2*1e6,Vgs2-Vth,ft2/1e9);xlim([0.1 1]);ylim([0 0.8]);
%--------------------------------------------------------------------------
% Plot Qi;
%figure(4);
%plot(W1*1e6,Qi1,'b');hold off;grid on;
%xlabel('W (um)');ylabel('Qi');xlim([30 200]);
%title('Qi .vs. W');
%--------------------------------------------------------------------------
% Plot Av;
%figure(5);
%plot(Vgs-Vth,Av1,'b');hold on;grid on;
%xlabel('Vgs-Vth (V)');ylabel('Av (dB)');xlim([0 0.8]);
%title('Av .vs. Vgs-Vth');
%--------------------------------------------------------------------------
Tao Cheng Dept. of Information Technology, UTU 5/29/2008
% Plot Pdiss;
%figure(6);
%plot(Vgs-Vth,Pdiss1,'r');hold on;grid on;xlim([0 0.3]);%ylim([0 8]);
%xlabel('Vgs-Vth (V)');ylabel('Pdiss (mW)');
%title('Pdiss .vs. Vgs-Vth');
%--------------------------------------------------------------------------
% Plot NF;
%figure(7);
%plot(Vgs-Vth,NF1,'r');hold on;grid on;xlim([0 0.3]);%ylim([1 7]);
%xlabel('Vgs-Vth (V)');ylabel('NF (dB)');
%title('NF .vs. Vgs-Vth');