Chapter 4

UEEA2223/UEEG4223
Integrated Circuit Design


IC Fabrication,
Layout and
Simulation










































































Prepared by
Dr. Lim Soo King
15 Jan 2011.

- i -
Chapter 4............................................................................................97
IC Fabrication, Layout, and Simulation.........................................97
4.0 Introduction..............................................................................................97
4.1 Types of Rules...........................................................................................97
4.2 SCMOS Design Rule Sets ........................................................................99
4.2.1 n-well.................................................................................................................. 100
4.2.2 n-diff and p-diff................................................................................................. 100
4.2.3 Polysilicon (Poly 1) ........................................................................................... 101
4.2.4 Polysilicon (Poly 2) ........................................................................................... 102
4.2.5 Option................................................................................................................ 102
4.2.6 Contact .............................................................................................................. 102
4.2.7 Metal1................................................................................................................ 103
4.2.8 Via1.................................................................................................................... 103
4.2.9 Metal2................................................................................................................ 104
4.2.10 Via2.................................................................................................................. 104
4.2.11 Metal3.............................................................................................................. 105
4.2.12 Via3.................................................................................................................. 105
4.2.13 Metal4.............................................................................................................. 105
4.2.14 Via4.................................................................................................................. 106
4.2.15 Metal5.............................................................................................................. 106
4.2.16 Via5.................................................................................................................. 107
4.2.17 Metal6.............................................................................................................. 107
4.2.18 Pad ................................................................................................................... 107
4.3 CMOS Circuit Layout ...........................................................................108
4.4 Layout Concepts and Methods .............................................................108
4.5 Using Schematic Capture and Layout Software.................................113
4.5.1 Schematic Capture ........................................................................................... 113
4.5.2 Layout................................................................................................................ 116
4.5.3 Drawing Layout of Logic Gates and Combinational Circuit ....................... 121
4.6 Parasitic Components of MOS Transistor ..........................................123
4.6.1 Parasitic Resistance.......................................................................................... 123
4.6.2 Parasitic Capacitance....................................................................................... 124
4.6.3 Junction Leakage Current............................................................................... 129
4.7 Voltage Decay on an RC Ladder ..........................................................130
4.8 RC Model of Metal Interconnect and Poly Line.................................132
4.9 Electromigration and Latch-up............................................................133
4.10 Scaling Theory......................................................................................135
Exercises........................................................................................................136
Bibliography .................................................................................................138



- ii -

Figure 4.1: Examples of geometrical object polygon...................................................... 97
Figure 4.2: Example to illustrate minimum feature and spacing........................................ 98
Figure 4.3: Surround rule example..................................................................................... 99
Figure 4.4: Illustration of n-well design rules .................................................................. 100
Figure 4.5: Illustration of n-diff and p-diff design rules .................................................. 101
Figure 4.6: Illustration of polysilicon design rules........................................................... 101
Figure 4.7: Illustration of polysilicon (Poly 2) design rule .............................................. 102
Figure 4.8: Illustration of option design rule.................................................................... 102
Figure 4.9: Illustration of Contact design rule.................................................................. 103
Figure 4.10: Illustration of Metal1 design rule................................................................... 103
Figure 4.11: Illustration of Via1 design rule ...................................................................... 104
Figure 4.12: Illustration of Metal2 design rule................................................................... 104
Figure 4.13: Illustration of Via2 design rule ...................................................................... 104
Figure 4.14: Illustration of Metal3 design rule................................................................... 105
Figure 4.15: Illustration of Via3 design rule ...................................................................... 105
Figure 4.16: Illustration of Metal4 design rule................................................................... 106
Figure 4.17: Illustration of Via4 design rule ...................................................................... 106
Figure 4.18: Illustration of Metal5 design rule................................................................... 106
Figure 4.19: Illustration of Via5 design rule ...................................................................... 107
Figure 4.20: Illustration of Metal6 design rule................................................................... 107
Figure 4.21: Illustration of Pad design rule........................................................................ 108
Figure 4.22: Stick diagram for an inverter ......................................................................... 109
Figure 4.23: Stick diagram symbols for wires.................................................................... 109
Figure 4.24: Stick diagram for a two-input NAND gate.................................................... 110
Figure 4.25: Re-draw of stick diagram for a two-input NAND gate with vertical poly line
........................................................................................................................ 110
Figure 4.26: The Euler path of logic function logic function ) C B ( ) E D ( A + + ......... 111
Figure 4.27: The parallel-series p-MOS transistor network circuit.................................... 112
Figure 4.28: The layout of circuit shown in Fig. 4.27........................................................ 113
Figure 4.29: The manual page of schematic capture software ........................................... 114
Figure 4.30: The design of an inverter ............................................................................... 115
Figure 4.31: Timing diagram of an inverter ....................................................................... 115
Figure 4.32: The design of a 3-input NAND gate.............................................................. 116
Figure 4.33: Timing diagram of the 3-input NAND gate................................................... 116
Figure 4.34: The manual page of Microwind layout software ........................................... 117
Figure 4.25: Layout of a p-MOS transistor and an n-MOS transistor................................ 118
Figure 4.36: Layout of an inverter...................................................................................... 119
Figure 4.37: Simulation result of the layout of an inverter ................................................ 119
Figure 4.38: The transistor circuit of three series n-MOS transistors ................................ 120
Figure 4.39: The layout of three series n-MOS transistors ................................................ 120
Figure 4.40: The transistor circuit of three parallel connected p-MOS transistors ............ 121
Figure 4.41: The layout of three parallel connected p-MOS transistors ............................ 121
Figure 4.42: The transistor level design of combinational circuit output = ( ) C B A + .... 122
Figure 4.43: The layout of combinational circuit output = ( ) C B A + ............................. 122
Figure 4.44: The timing diagram of combinational circuit output = ( ) C B A + ............... 123
Figure 4.45: Capacitance of MOS transistor ...................................................................... 124
Figure 4.46: Gate-channel capacitance as the function of gate-source voltage ................. 125

- iii -
Figure 4.47: The linear time invariant model of a MOS transistor .................................... 125
Figure 4.48: (a) Drain/source structure of MOS transistor (b) bottom structure and (c) side-
wall structure.................................................................................................. 126
Figure 4.49: Drain of the MOS transistor under reverse biased condition......................... 129
Figure 4.50: An n-MOS transistor switching model .......................................................... 130
Figure 4.51: ac RC model of two series connected n-MOS transistors.............................. 131
Figure 4.52: (a) Lump element model and (b) Tree model of metal interconnect ............. 132
Figure 4.53: The phenomenon of electromigration and its effects..................................... 133
Figure 4.54: Illustration of parasitic components of CMOS device (a) device geometry and
(b) latch-up model.......................................................................................... 134
Figure 4.55: Refilled deep trench between p-well and n-well............................................ 134
Figure 4.56: Generalized scaling theory for MOS transistor ............................................. 136

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Chapter 4

IC Fabrication, Layout, and Simulation


4.0 Introduction

In this Chapter, we will discuss the design rules that are a set of specifications
that govern the layout of integrated circuit masking layout. It is the minimum
separation or thickness governing the components distance and width
requirements. This chapter presents a set of scalable CMOS design rules and the
guides for layout of the design.

The CMOS layout technique with the emphasis using stick diagram and the
concept of vertical layout approach are discussed. In the same section, the
electronic design automation EDA tools Microwind - is introduced with
specification design examples.

MOS transistor device RC model is introduced in the last section that
including the derivation of diffusion capacitance and resistance. The RC models
of metal interconnect and polysilicon gate are also including. The issues of
electromigration, CMOS latch-up, and scaling theory are the last to be
discussed.

4.1 Types of Rules

Integrated circuit layout deals with the design of geometrical objects on each
masking layer according to a set of rules. Geometrical object is referred to as
polygon that created by one or more rectangles as what is shown in Fig. 4.1.


Figure 4.1: Examples of geometrical object polygon

The design rules can be classified into four major types. They are:
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Minimum Feature This is the smallest side length of an object on the
layer. If the object is a line, then this specifies the minimum line width.
Minimum Spacing The minimum spacing rule governing how close two
polygons can be placed.
Surround A surround rule is used when a feature on one layer must be
embedded within a polygon on another layer.
Exact Size An exact size rule means that the feature can only have the
dimensions specified in the rule. Other sizes are not permitted.

Violation of the design rules of minimum feature specified in the above section
may lead broken or damage line. Placing two polygons too closed to each other
may lead to incomplete resolved feature leading to unwanted electrical
capacitance coupling between two features. In the long run operation of the
device that has design rule violation feature leads to functionality problem and
reliability issue.

Lets take the example illustrated in Fig. 4.2 to check the minimum feature
and minimum spacing rules. Of all the thickness specified in the example shown
in Fig. 4.2, thickness d and e do not meet the minimum thickness requirements
as specified by W. This is a design rule violation.


Figure 4.2: Example to illustrate minimum feature and spacing


Of all the spacing A, B, and C, spacing C does not meet the minimum as
specified as S. This is a design rule violation. In all layout software for
integrated circuit design, design rule check routine is readily available.

The surround rule is illustrated by an oxide contact cut for access to p-
diffusion as illustrated in Fig. 4.3.
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Figure 4.3: Surround rule example

The surrounding spacing S shown is the minimum spacing required for the
contact cut embedded on the p-diffusion layer. This is necessary to allow some
mask misalignments so that it is still fall within the boundary of the existing
layer in this case is the p-diffusion layer.

The exact size rule is usually applied to contact cut and vias. In this
example, the minimum size is D.

In the present time, there are three design rule sets, which are generic
scalable CMOS SCMOS, submicron rule and deep submicron. Generic SCMOS
is applicable to line width more than 1.0m. Submicron is typically used for
about 0.8m to 0.35m. Deep submicron rule is used for less than 0.35m.

In the SCMOS rules used here, all spacings are integer multiples of and
called lamba design rules. We shall study the rule set for a dual-poly, 6-metal,
n-well CMOS processes.

4.2 SCMOS Design Rule Sets

The typical set of design rule listed in this section is the generic SCMOS set,
which applicable to CMOS process of line width more than 1.0m. Since the
standard Microwind process is set at 0.12m technology, which is belong to
deep submicron technology. Student is encouraged to find out the design rule
set for this technology. The format of each design rule is listed as rule#
Description: Value. The value listed here is the minimum value.


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4.2.1 n-well

The n-well design rules are
r101 Minimum well size: 12
r102 Well-to-well spacing: 11
r103 Minimum surface are 144
2


The illustration is shown in Fig. 4.4.

Figure 4.4: Illustration of n-well design rules

4.2.2 n-diff and p-diff

n-diff and p-diff design rules are
r201 Minimum n
+
and p
+
diffusion width: 4
r202 Minimum spacing between two p
+
and n
+
diffusion: 4
r203 Extension over n-well after p
+
diffusion: 6
r204 Minimum spacing between n
+
diffusion and n-well: 6
r205 Border of well after n
+
bias : 2
r206 Minimum spacing between p
+
diffusion and n-well: 6
r210 Minimum surface: 24
2


The illustration is shown in Fig. 4.5.

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Figure 4.5: Illustration of n-diff and p-diff design rules


4.2.3 Polysilicon (Poly 1)

Polysilicon (Poly 1) design rules are
r301 Polysilicon width: 2
r302 Polysilicon gate on diffusion : 2
r303 Polysilicon gate on diffusion for high voltage FET: 4
r304 Between two poly boxes: 3
r305 Polysilicon versus other diffusion : 2
r306 Diffusion after polysilicon: 4
r307 Extra gate after diffusion: 2

The illustration is shown in Fig. 4.6.



Figure 4.6: Illustration of polysilicon design rules
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4.2.4 Polysilicon (Poly 2)

Polysilicon (Poly 2) design rules are
r311 Polysilicon width: 2
r312 Polysilicon gate extended beyond diffusion: 2

The illustration is shown in Fig. 4.7.


Figure 4.7: Illustration of polysilicon (Poly 2) design rule

4.2.5 Option

Option design rules are
ropt: 2
Border of option layer over diff n
+
and diff p
+
.

The illustration is shown in Fig. 4.8.

Figure 4.8: Illustration of option design rule

4.2.6 Contact

Contact design rules are
r401 Contact size: 2 x 2
r402 Spacing between two contact: 3
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r403 Contact to diffusion edge: 2
r404 Poly surround: 2
r405 Metal1 surround: 2
r406 Contact to poly gate: 3

The illustration is shown in Fig. 4.9.

Figure 4.9: Illustration of Contact design rule

4.2.7 Metal1

Metal1 design rules are
r501 Metal1 width: 3
r502 Between two metal1: 4
r510 Minimum surface: 32
2


The illustration is shown in Fig. 4.10.

Figure 4.10: Illustration of Metal1 design rule

4.2.8 Via1

Via1 design rules are
r601 Via1 size: 2 x 2
r602 Spacing between Via1 edge: 4
r603 Between Via1 and contact: 0
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r605 Extra Metal2 over Via1: 2

The illustration is shown in Fig. 4.11.

Figure 4.11: Illustration of Via1 design rule

4.2.9 Metal2

Metal2 design rules are
r701 Metal2 width: 3
r702 Between two metal2: 4
r710 Minimum surface: 32
2

The illustration is shown in Fig. 4.12.

Figure 4.12: Illustration of Metal2 design rule


4.2.10 Via2

Via2 design rules are
r801 Via1 size: 2 x 2
r802 Spacing between Via2 edge: 4
r804 Extra Metal2 over Via2: 2
r805 Extra Metal3 over Via2: 2

The illustration is shown in Fig. 4.13.

Figure 4.13: Illustration of Via2 design rule
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4.2.11 Metal3

Metal3 design rules are
r701 Metal3 width: 3
r702 Between two metal3: 4
r710 Minimum surface: 32
2


The illustration is shown in Fig. 4.14.

Figure 4.14: Illustration of Metal3 design rule

4.2.12 Via3

Via3 design rules are
ra01 Via3 size: 2 x 2
ra02 Spacing between Via3 edge: 4
ra04 Extra Metal3 over Via3: 2
ra05 Extra Metal4 over Via3: 2

The illustration is shown in Fig. 4.15.

Figure 4.15: Illustration of Via3 design rule

4.2.13 Metal4

Metal4 design rules are
rb01 Metal4 width: 3
rb02 Between two metal4: 4
rb10 Minimum surface: 32
2


The illustration is shown in Fig. 4.16.
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Figure 4.16: Illustration of Metal4 design rule

4.2.14 Via4

Via4 design rules are
rc01 Via4 size: 2 x 2
rc02 Spacing between Via4 edge: 4
rc04 Extra Metal4 over Via4: 2
rc05 Extra Metal5 over Via4: 2

The illustration is shown in Fig. 4.17.


Figure 4.17: Illustration of Via4 design rule

4.2.15 Metal5

Metal5 design rules are
rd01 Metal5 width: 8
rd02 Between two metal5: 8
rd10 Minimum surface: 100
2


The illustration is shown in Fig. 4.18.

Figure 4.18: Illustration of Metal5 design rule

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4.2.16 Via5

Via5 design rules are
re01 Via5 size: 5 x 5
re02 Spacing between Via5 edge: 5
re04 Extra Metal5 over Via5: 2
re05 Extra Metal6 over Via5: 2

The illustration is shown in Fig. 4.19.



Figure 4.19: Illustration of Via5 design rule

4.2.17 Metal6

Metal6 design rules are
rf01 Metal6 width: 8
rf02 Between two metal6: 15
rf10 Minimum surface: 300
2


The illustration is shown in Fig. 4.20.

Figure 4.20: Illustration of Metal6 design rule

4.2.18 Pad

Pad design rules are
rp01 Pad size: 100m x 100m
rp02 Spacing between Pads: 100m
rp03 Surround (passivation): 5m
rp04 Spacing between Pad and Active: 20m
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The illustration is shown in Fig. 4.21.

Figure 4.21: Illustration of Pad design rule


One does not require memorizing all this design rules. As you practice more,
you will naturally get use with the design rules. Moreover, any violation of the
rule can be checked by a click of button of the software.

4.3 CMOS Circuit Layout

In designing the layout of the CMOS circuit, horizontal or vertical approach can
be adopted. Power lines such as V
DD
and V
SS
can be placed in horizontal
manner. The components of the circuit are to be placed within the space
between the power lines. The poly gate line is placed vertically. The metal1 line
is placed horizontally. The metal2 line shall then be placed vertically. The
placing of metal line will be alternative horizontal and vertical approach to
avoid delay.

One can always begin by sketching the layout so that when drawing the
actual layout, the design rules are watched. One has to realize that drawing the
layout is actually a form of art. You may start the design with the smallest
dimension such as the poly, and then followed by the diffusion region and
contact. In this manner, you can cross check the design rule at any time and
adjust accordingly.

4.4 Layout Concepts and Methods

Upon designing the transistor level circuit, the next step is to make physical
layout of the circuit so that it can be converted into mask for final fabrication of
the circuit. The starting point of the layout is circuit schematic. The circuit
shows that connection between transistors. One approach is making used of the
stick diagram as illustrated in Fig. 4.22 for the layout of an inverter.

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Figure 4.22: Stick diagram for an inverter


One observation is that the V
DD
and V
SS
power lines are placed one on top and
one at the bottom. The input is placed at the left side of the circuit, whilst the
output is placed at the right side.

Stick diagram symbols for wire are shown in Fig. 4.23. The figure has
shown up to metal3. It can be extended to metal6 or metal7. One may use color
to draw the stick diagram. Usually red is used for poly, green for n-diffusion,
yellow for p-diffusion and shaded blue for metal. Illustrated in Fig. 4.24 is the
stick diagram for an NAND gate. One may also arrange the stick diagram such
that the poly formed the vertical line with input at the bottom of the circuit as
illustrated in Fig. 4.25 for the same NAND gate layout.



Figure 4.23: Stick diagram symbols for wires

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Figure 4.24: Stick diagram for a two-input NAND gate


Figure 4.25: Re-draw of stick diagram for a two-input NAND gate with vertical poly line

Drawing a large circuit using stick diagram usually would lead to spaghetti
layout. Thus, it is necessary to make use of hierarchical approach to organize
the stick diagram.

Drawing the complex logic circuit using stick diagram is equally complex
like the drawing a large circuit mentioned earlier. It is necessary to seek a
common path which termed as Euler path for simplifying the final stick
diagram to obtain optimization. Optimization means less propagation delay and
more efficient way of utilizing the silicon area in terms of having single piece of
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diffusion. Euler path is a path through all nodes in the graphical design such that
each edge is passed once and only once. Using the logic function
) C B ( ) E D ( A + + as an illustration, the most efficient path, the Euler path is
EDABC, which is shown in Fig. 4.26. An example of the path which is not
efficient is ADEBC.


Figure 4.26: The Euler path of logic function logic function ) C B ( ) E D ( A + +

Lets consider to draw the layout of series-parallel or parallel-series transistor
level circuit. The parallel-series p-MOS transistor network circuit is shown in
Fig. 4.27. The logic function of this circuit is Output = ( ) C B A + .

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Figure 4.27: The parallel-series p-MOS transistor network circuit

The layout of this network circuit is shown in Fig. 4.28. To do the layout, first
thing to is to identify the source and drain of the transistors and label them as
shown in Fig. 4.27. There are two parallel transistors A and B connected to a
series transistor C. One of the arrangements of layout is drain-source of
transistor A connected to source-drain of transistor B and then connected to
source-drain of transistor C. Source of transistor A and B shall then be
connected to V
DD
via metal 1, whilst the drains of transistor A and B, and source
of transistor C are connected together via metal 1. Drain of transistor C shall be
connected to output via metal 1. In this manner one may be see there is
minimum usage of metal. This shall mean the contribution of resistance and
capacitance of the metal to the delay time is at minimum.
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Figure 4.28: The layout of circuit shown in Fig. 4.27

4.5 Using Schematic Capture and Layout Software
There are countless of VLSI layout software available in the market. The price
to obtain this software ranges from free of charge to millions of dollar. Learner
can browse this website http://www.vlsitechnology.org/html/ic_software.html
for obtaining the information. For learning purpose, we shall choose Microwind
software. Light version of Microwind software, which is free of charge, can be
obtained from website http://www.microwind.org. This software package comes
with two parts, which the schematic capture software and layout software. The
schematic software Dsch.exe allows user to design logic circuit, which can
be combinational and sequential types using basic logic gates or p- and n-MOS
transistors. The layout software - Microwind.exe allows user to design layout
manually or draw layout automatically by importing a verilog file.

4.5.1 Schematic Capture
The manual page of the schematic capture software Dsch.exe is shown in Fig.
4.29. The manual contains functions, open file, save file, select, cut, copy,
move, rotate, add line, simulate, timing diagram, zoom in, zoom out, view
electrical list, move, symbol libraries, and working area. The symbol libraries
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consist of basic gate and input pad and output display. The symbol libraries
also consist of some advanced electrical components and sources. At the right
bottom of the display shows the default technology used. In this screen it shows
the default technology is 0.12m.


Figure 4.29: The manual page of schematic capture software

You can begin to design logic gate using p-MOS and n-MOS transistors. If we
are to design a CMOS inverter CMOS inverter as shown in Fig. 4.30, which has
logic function output = A , the logic function can be interpreted as a low
asserted high and high asserted low equation. This shall mean a p-MOS and an
n-MOS transistor are connected in series with input A and output taken from the
drains of the transistors. The source of p-MOS transistor is connected to V
DD

power line, whilst the source of n-MOS transistor is connected to V
SS
ground
line. To get the transistor, it is done by pressing the transistor and placing it into
the working area. To interconnect, it is done by add line function. The power
V
DD
and V
SS
ground can be connected in the similar manner i.e. pressing them
from the symbol libraries and placing them at the right place in the working area.
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Figure 4.30: The design of an inverter

Upon design, you can press the simulate key to simulate the functionality of
the inverter. The result of the simulation can be viewed by pressing the timing
diagram button, which is shown in Fig. 4.31. From the timing diagram, it
shows that the inverter is functioning correctly.



Figure 4.31: Timing diagram of an inverter

The logic function of a three input NAND is output = C B A . This equation is a
high asserted low equation, which can be used to design n-MOS transistor
network of the NAND gate. For designing the CMOS version of this NAND
gate, we need also a p-MOS network circuit, which is a low asserted high
network equation. This can be done by using DeMorgan theorem to convert
logic function output = C B A to output = C B A + + , which is a low asserted
high equation. The transistor level of a three input NAND gate is shown in Fig.
4.32. It is done by dragging the n-MOS and p-MOS transistors to the working
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area and inter-connected them and putting the V
DD
power line and V
SS
ground
line.


Figure 4.32: The design of a 3-input NAND gate

The result of simulation is shown from the timing diagram in Fig. 4.33. From
the timing diagram, it shows that the 3-input NAND gate is functionally
working.



Figure 4.33: Timing diagram of the 3-input NAND gate

4.5.2 Layout

The manual page of the layout Microwind.exe is shown in Fig. 4.34. The
manual contains the functions, open file, save file, select, cut, copy, move and
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stretch, simulate, timing diagram, zoom in, zoom out, view electrical node, 2D
view, 3D view, ruler, design rule check, palette function, and the working area.
The palette consists of basic n
+
and p
+
diffusion layers, polysilicon 1 and 2
layers, metal 1 to metal 6 layers, power sources, via connections, passive and
active components, and MOS transistor generator. At the right bottom of the
display shows the default technology used. In this screen it shows the default
technology is 0.12m.



Figure 4.34: The manual page of Microwind layout software

In the vertical approach layout, poly gate line is placed vertically, while power
line is placed horizontally. This approach will be adopted for the rest of design
mentioned in this text.

Lets proceed to design the layout of an inverter as shown in Fig. 4.30. One
of approaches is to use the MOS generator function in the palette. Upon
selecting MOS generator function, you can choose either n-MOS transistor, p-
MOS transistor, or double gate transistor. Since the inverter has one input, you
will choose one finger type. Beside these options, you may choose low leakge,
high speed or high voltage type. The layout is shown in Fig. 4.35. From the
colour illustration you will see that the p-MOS transistor is sitting inside an n-
well. The cross square pad is the via that connecting the semiconductor either
the p-diffusion or n-diffusion type to the first metal 1, which is in blue color.
The orange color bar is the polysilicon gate. The grid is used for ease for
drawing layout and there is a scale of 5 lamda, which equivalent to 0.30m
from a grid point to another grid point. You may choose zoom in or zoom
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out function to change the scale. Since the substrate material for CMOS VLSI
design is a (100) p-type semiconductor, thus, the black work area is a (100) p-
type substrate.


Figure 4.25: Layout of a p-MOS transistor and an n-MOS transistor

Upon designing or placing the transistors, the next step is to inter-connect them
according to the design and placing the power line horizontally, bias the p-
substrate and n-well, connect input source, and connect visible node for visible
observation. Figure 4.26 shows the layout after these layout steps. The layout
shows that the source of the p-MOS transistor is connected to power source V
DD

via metal 1, whilst the source of n-MOS transistor is connected to V
SS
ground
source via metal 1. The drains of both the transistors are connected together to
form the output. The p-substrate is biased with V
SS
source, whilst the n-well is
biased with V
DD
source. You may want recall the reason why the p-substrate
and n-well needed to be biased in this manner.
4 IC Fabrication, Layout, and Simulation

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Figure 4.36: Layout of an inverter

Upon design the layout of the inverter, you may want simulate to see if the
layout is functioning. This can be done by selecting simulation function button.
The result of the simulation is shown in Fig. 4.37, which is right as expected for
an inverter.



Figure 4.37: Simulation result of the layout of an inverter

Lets discuss how to design the layout of three series connected transistor as
shown in Fig. 4.38. You may begin with the MOS generator function and
follow by choosing n-MOS transistor with three fingers. You shall then remove
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the extra via contact and metal 1 using cut function. Figure 4.39 shows the
layout after connected the source of transistor C to V
SS
ground, bias the p-
substrate with V
SS
ground, and placing the input source to input A, B, and C.



Figure 4.38: The transistor circuit of three series n-MOS transistors



Figure 4.39: The layout of three series n-MOS transistors

Lets discuss how to design the layout of three parallel connected transistors as
shown in Fig. 4.40. You may begin with the MOS generator function and
4 IC Fabrication, Layout, and Simulation

- 121 -
follow by choosing p-MOS transistor with three fingers. Figure 4.41 shows the
layout after connecting the V
DD
power line, bias the n-well with V
DD
voltage,
and connecting all sources and drains of the transistors together via metal1.



Figure 4.40: The transistor circuit of three parallel connected p-MOS transistors



Figure 4.41: The layout of three parallel connected p-MOS transistors

4.5.3 Drawing Layout of Logic Gates and Combinational Circuit
Based on the knowledge of layout learnt from previous Section 4.5.2, following
the same procedure, the layout of any logic gates and combinational circuit can
be drawn. Taking for an example the transistor level circuit of the combinational
logic with logic function output = ( ) C B A + is designed and shown in Fig. 4.42.
Its layout is shown in Fig. 4.43. The simulation result is shown in Fig. 4.44.
4 IC Fabrication, Layout, and Simulation

- 122 -


Figure 4.42: The transistor level design of combinational circuit output = ( ) C B A +



Figure 4.43: The layout of combinational circuit output = ( ) C B A +
4 IC Fabrication, Layout, and Simulation

- 123 -


Figure 4.44: The timing diagram of combinational circuit output = ( ) C B A +

4.6 Parasitic Components of MOS Transistor

MOS transistor is normally used for switching and voltage gain. There are
number of parasitic components associated with the structure. It contains
parasitic resistance and capacitance that affects the circuit operation. These
components cannot be eliminated especially in high-speed device operation. We
shall discuss these two components in detail.

4.6.1 Parasitic Resistance

The resistance of MOS transistor is not linear as we can see from the output
characteristic of the MOS transistor, despite the fact, the term linear time-
invariant LTI is used to provide information about the drain to source flow.
Since the resistance is not linear, therefore, the resistance R
n
is depending on the
point where it is taken. Using n-MOS transistor as an example, the non linear
resistance is governed by R
n
=
DS
DS
dI
dV
, which is the reciprocal of conductance
shown in equation (2.35). i.e.
) V V ( W C
L
R
n t GS ox n
n

= . The saturation resistance
R
n
is obtained from equation
2
n t GS ox n
DS
n
) V V ( W C
LV 2
R

= . Since the digital
electronics works in linear region, therefore, the linear equation is used for
calculating the drain to source resistance R
n
or R
ds
. Since the logic voltage is
either V
DD
or V
SS
, the V
GS
voltage or V
SG
voltage is equal to V
DD
. Thus, turn-on
resistance R
n
is equal to

4 IC Fabrication, Layout, and Simulation

- 124 -

) V V ( W C
L
R
n t DD ox n
n

= (4.1)

and


( )
p t DD ox p
p
V V W C
L
R

= (4.2)

4.6.2 Parasitic Capacitance

MOSFET has a number of parasitic capacitances. They are shown in Fig. 4.45.
These capacitances are function of voltage and dimensions. C
DB
and C
SB
are
depletion capacitances due to pn junction of the MOS transistor. The other three
capacitance C
GS
, C
GD
, and C
GB
are related to MOS capacitance C
OX
=
OX
OX
d
WL
.

Figure 4.45: Capacitance of MOS transistor

In VLSI or semiconductor physics, MOS capacitance is usually expressed in
farad per unit area. By default C
OX
is equal to
OX
OX
d

. The gate to backward

capacitance C
GB
is equal to C
OX
WL. C
GB
is also equal to gate capacitance C
G
at
cut-off region when gate-to-source voltage is equal to zero.

Figure 4.46 illustrates the relationship of gate-channel capacitance with
respect to various gate-to-source voltage.
4 IC Fabrication, Layout, and Simulation

- 125 -

Figure 4.46: Gate-channel capacitance as the function of gate-source voltage

Based on the results, it shows that the capacitance C
GS
and C
GD
are
approximately equal to
G
C
3
2
at saturation region. For triode region, the
capacitance C
GS
and C
GD
are approximately equal to
G
C
2
1
and
G
C
2
1
respectively
at zero bias, which is
OX
C
2
1
. Please note the capacitance mentioned in this
paragraph has unit of farad.

Based on capacitance distribution of a MOS transistor shown in Fig. 4.45,
the linear time-invariant model of the n-MOS transistor shall be as shown in
Fig. 4.47.



Figure 4.47: The linear time invariant model of an n-MOS transistor

4 IC Fabrication, Layout, and Simulation

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Source and drain capacitance C
S
and C
D
are respectively equal to C
S
=C
GS
+C
SB

and C
D
=C
GD
+C
DB
. These capacitance values are used partially to determine the
switching times of the MOS transistor device.

In linear operation, which is the operation for digital device, C
GS
and C
GD

are equal to half of C
G
, which is WL C
2
1
OX
as illustrated in Fig. 4.46. The
depletion capacitance C
SB
and C
DB
are respectively equal to the sum of bottom
capacitance and sidewall capacitance of the drain or source of the device. They
are calculated by approach discussed in the following paragraph.

The drain or source structure of the MOS transistor is shown in Fig.
4.48(a). You can view the drain and source as a rectangular tray with a bottom
plate of side W by X and side wall of W by x
j
and X by x
j
. Its corresponding
bottom structure and side-wall structure are shown in Fig. 4.48(b) and Fig.
4.48(c) respectively.


Figure 4.48: (a) Drain/source structure of MOS transistor (b) bottom structure and (c) side-
wall structure

The capacitance C
n
of the source or drain of the n-MOS transistor is equal to the
sum of bottom capacitance C
bot
and the side wall capacitance C
sw
.

4 IC Fabrication, Layout, and Simulation

- 127 -
C
n
= C
bot
+ C
sw
(4.3)

The bottom capacitance C
bot
is equal to C
j
XW, where C
j
is the junction
capacitance per unit area, X is the length of the drain or source. C
n
is also equal
to C
DB
or C
SB
values.

The side wall capacitance C
sw
of W side is equal to

C
swL
= C
jsw
W (4.4)

where C
jsw
is junction capacitance per unit area multiplied by the thickness x
j
of
drain or source i.e. C
jsw
= C
j
x
j
. The total side wall is (2W+2X). Therefore, the
total side wall capacitance is C
sw
= C
jsw
(2W+2X) = C
jsw
P, where P is the
perimeter of the drain or source. The total capacitance of the drain or source C
n

is

C
n
= C
jbot
XW + C
jsw
(2W+2X) (4.5)

The capacitance shown in equation (4.5) is the zero voltage bias capacitance.
This is the value usually used to model the timing of the MOS transistor since
zero voltage bias has the maximum capacitance.

Junction capacitance at time is called depletion capacitance. The junction
capacitance C
j
of the n-type source or drain with the p-type substrate is based
on equation
2 / 1
R bi
A S
) V V ( 2
N q
C
(

=
j
. If we denote C
o
as the zero bias voltage
junction capacitance, which is
2 / 1
bi
A S
V 2
N q
(

, then junction capacitance
2 / 1
R bi
A S
) V V ( 2
N q
C
(

=
j
becomes


bi
R
o
2 / 1
bi
R
bi
A S
V
V
1
C
V
V
1
V 2
N q
C
+
=
(
(
(
(

=
j
(4.6)

where V
bi
=
|
|

\
|
2
i
D A
n
N N
ln
q
kT
and V
R
denotes as built-in potential and bias voltage
respectively. In general equation (4.6) can be written as
4 IC Fabrication, Layout, and Simulation

- 128 -

m
bi
R
om
V
V
1
C
C
|
|

\
|
+
=
j
(4.7)

where m denotes grading parameter which is a value less than one. For m =1/2,
it denotes an abrupt or step junction, whilst for m = 1/3, it denotes a gradual
junction. C
om
denotes the junction capacitance at zero bias voltage for an m
graded junction.

Usually, we take the side-wall junction of the drain/source of the MOS
transistor as a linearly graded junction, whilst the bottom junction of the
drain/source of the MOS transistor has an abrupt junction. Thus, their grading
parameter m are 1/3 and 1/2 respectively. Combining equation (4.5) and
equation (4.7), the drain/source capacitance of the MOS transistor follows
equation (4.8).


3 / 1
bis
R
2 / 1
bi
R
R n
V
V
1
) X W ( 2 C
V
V
1
WX C
) V ( C
|
|

\
|
+
+
+
|
|

\
|
+
=
w
jsw
bot
jbot
(4.8)

Since the output changes from V
1
to V
2
and vice versa, the average drain/source
capacitance C
navg
is equal to

|
|

\
|
+
+
+
|
|

\
|
+

=

2
q
2
1
V
V
3 / 1
bis
R
R
V
V
2 / 1
bi
R
R
1 2
R navg
V
V
1
dV ) X W ( 2 C
V
V
1
dV WX C
) V V (
1
) V ( C
w
jsw
bot
jbot
(4.9)

Let
R
V
V
2 / 1
bi
R
1 2
2 1 2 / 1
dV
V
V
1
WX C
) V V (
1
WX C ) V , V ( K
2
1

|
|

\
|
+

bot
jbot
jbot
and
R
V
V
3 / 1
bi
R
1 2
2 1 3 / 1
dV
V
V
1
) X W ( C 2
) V V (
1
) X W ( 2 C ) V , V ( K
2
1

|
|

\
|
+
+

= +

sw
jsw
jsw
. Equation (4.9) shall
become C
navg
(V
R
) = WX C ) V , V ( K
2 1 2 / 1 jbot
+ ) X W ( 2 C ) V , V ( K
2 1 3 / 1
+
jsw
.

For m grading parameter,
4 IC Fabrication, Layout, and Simulation

- 129 -

R
V
V
m
bi
R
1 2
2 1 m
dV
V
V
1
1
) V V (
1
) V , V ( K
2
1

|
|

\
|
+

sw
(4.10)

The integration result of equation (4.10) yields equation (4.11).


(
(

|
|

\
|
+
|
|

\
|
+
+
=
+ + ) 1 m (
bi
1
) 1 m (
bi
2
1 2
bi
2 1 m
V
V
1
V
V
1
) V V )( 1 m (
V
) V , V ( K
(4.11)

where K
m
(V
1
,V
2
) is called linear time-invariant factor LTI. Usually the bias
voltage V
2
and V
1
are respectively equal to V
OH
and V
OL
. Therefore, equation
(4.11) is equal to


(
(

|
|

\
|
+
|
|

\
|
+
+
=
+ + ) 1 m (
bi
OL
) 1 m (
bi
OH
OL OH
bi
OH VOL m
V
V
1
V
V
1
) V V )( 1 m (
V
) V , V ( K
(4.12)

4.6.3 Junction Leakage Current

The pn junctions formed by the drain to bulk and source to bulk interfaces in a
MOS transistor introduce leakage current that is often important in high-
performance circuit design. Consider the drain of a MOS transistor shown in Fig.
4.49 is reverse biased by drain-to-source voltage.


Figure 4.49: Drain of the MOS transistor under reverse biased condition

The junction leakage current I
R
is equal to
4 IC Fabrication, Layout, and Simulation

- 130 -
I
R
= I
o
+ I
gen
(4.13)

where I
o
is the reverse saturation current and I
gen
is the re-generation current.
The re-generation current is equal to


(
(

1
V
V
1
2
d qAn
I
bi
DS
depMin i
gen
(4.14)

Usually the reverse saturation current is very small that can be ignored. The
reverse bias current of the drain-to-substrate junction is equal to


(
(

|
|

\
|
+

1
V
V
1
2
d qAn
I
m
bi
DS
depMin i
R
(4.15)

where m is grading factor.

The switching model of the MOS transistor taken into account the parasitic
capacitance, resistance, and leakage current shall be as shown in Fig. 4.50.

Figure 4.50: An n-MOS transistor switching model

4.7 Voltage Decay on an RC Ladder

The ac RC ladder circuit for two n-channel MOS transistors connected in series
is shown in Fig. 4.51. R
1
and R
2
represent the channel resistance of MOS
transistor Mn
1
and MOS transistor Mn
2
respectively. C
1
and C
2
represent the
source capacitance of MOS transistor Mn
1
and MOS transistor Mn
2

respectively. An input voltage V
in
is fed to the drain of transistor Mn
1
. After
some time the voltage V
1
and V
2
shall be same as V
in
. If the input voltage V
in
is
removed and node D is shorted to ground, the charged stored in capacitance C
1

4 IC Fabrication, Layout, and Simulation

- 131 -
and C
2
would begin to discharge through resistance R
1
and (R
1
+R
2
)
respectively.

Figure 4.51: ac RC model of two series connected n-MOS transistors

Since V
2
is the output voltage, it can be shown that V
2
is discharged following
equation V
2
(t) =
/ t
in
e V , where the time constant is equal to =
C
1
R
1
+C
2
(R
1
+R
2
). The time constant is derived from Elmore formula for series
RC chain. The analysis can be done by applying Kirchhoffs current law at node
V
1
and V
2
, to obtain equation as function C
1
, C
2
, R
1
, and R
2
, which are
2
1 2
1
1 1
1
R
V V
R
V
dt
dV
C

= and
2
1 2 2
2
R
V V
dt
dV
C

= . One way to obtain the solution
for the equations is by means of Laplace transforming from time domain to s-
domain, which will take the form
2
1 2
1
1
1 1 1 1
R
V V
R
V
) 0 ( V C ) ( V C

= + s s and
2
2 2
2 2 2 2
R
V V
) 0 ( V C ) ( V C

= + s s , where V
1
(0) and V
2
(0) are initial condition of the
time domain and these values are V
in
value. In general the time constant for N
series connected MOS transistor would follow the general Elmore formula
which takes the form.

|

\
|
=

= =
k
1 m
m
N
1 k
k
R C (4.16)

If it is charging then the output voltage V
N
for an N connected series MOS
transistors is

V
N
(t) = ( )

/ t
in
e 1 V (4.17)

For an example, the time constant for four series connected MOS transistors
with resistance R
1
, R
2
, R
3
, and R
4
and capacitance C
1
, C
2
, C
3
, and C
4
is equal to
) R R R R ( C ) R R R ( C ) R R ( C C R
4 3 2 1 4 3 2 1 3 2 1 2 1 1
+ + + + + + + + + = .
4 IC Fabrication, Layout, and Simulation

- 132 -
4.8 RC Model of Metal Interconnect and Poly Line

A metal line with length L, width W and thickness d has resistance R
metal
equal
to R
metal
=
Wd
L
, where /d is defined as the sheet resistance R
smetal
. Thus, the
resistance of the metal interconnect line of length L and width W is equal to

R
metal
= R
smetal
W
L

(4.18)

The capacitance of the metal interconnect of length L width W, and thickness of
oxide X
int
separating the metal line and substrate is equal to

LW
X
C
int
ox
metal

= (4.19)

Equation (4.19) can be re-written as
int
ox
X

, which is the capacitance per unit area.

Based on the above analysis, two RC models of the metal line interconnect
connecting point A and point B is shown in Fig. 4.51. The lump RC model is
treating the capacitance as a lump sum putting at the end of point B. However,
this approach would end with double the time delay. A better approach is using
tree model or -model, whereby the capacitance is treated as distributed
capacitance whereby the capacitance C
metal
is distributed half at point A and half
at point B. With this approach, the time delay is a half of the lump sum model
approach.


(a) (b)
Figure 4.52: (a) Lump element model and (b) Tree model of metal interconnect

4 IC Fabrication, Layout, and Simulation

- 133 -
The extraction of capacitance of poly line follows the same approach of
extraction of diffusion capacitance for the drain/source of the MOS transistor.
There are two components, which are plate component and side wall perimeter
component due fringe electrical field caused by thickness of the poly line which
is usually larger than its width in the modern VLSI design.

4.9 Electromigration and Latch-up

The metal interconnect must be able to carry high current density which is
approximately 10
5
A/cm
2
because high speed requires high current density. High
current density leads to a phenomenon called electromigration, which is a major
cause of breakdown of integrated circuit. Figure 4.53 illustrates the
phenomenon and its effects.

Figure 4.53: The phenomenon of electromigration and its effects

Electromigration forces metal ions to move downstream mainly along the grain
structure. When this happens, it develops voids and hillocks at the curves and
forks. Electromigration can be prevented by controlling grain structure along the
micro-crystalline that forms metal lines. Larger atom such as copper has large
grain meaning less surface area and therefore less resistance to electromigration.
Copper also locks the aluminum atoms in place and prevents non-uniform
thermal effect. It prevents hillocking.

Not to forget that there is another problem, which is latch-up. Latch-up is
seen as a sudden massive increase in the current draw of an integrated circuit
that is high enough to rupture metal interconnect line and even bond wire due
high current density. Latch-up is a destructive problem. Although latch-up
problem has been well understood but this problem exists due to parasitic
component particularly the resistance as the results of scaled down. Figure 4.54
illustrates the parasitic components that lead to latch-up problem.
4 IC Fabrication, Layout, and Simulation

- 134 -

(a) (b)
Figure 4.54: Illustration of parasitic components of CMOS device (a) device geometry and
(b) latch-up model

If the product R
sub
and I
S
are larger than the base-to-emitter voltage of the
horizontal transistor, then this transistor would turn-on. As the result, the
collector of this transistor is closed to ground voltage. This may provide the
switching path for vertical transistor if the product of R
well
and I
W
current is
greater than the emitter-to-base voltage of this transistor. If this process is
happening, the 5V V
DD
is almost shorted to ground voltage via the very low
resistance of collector-to-emitter terminals of the both transistors. As the result,
high current density is registered that can rapture the metallization and bond
wire.

A method employed to overcome the latch-up problem is the formation of
deep-trench that is deeper than the well or tub as shown in Fig. 4.55. This
technique can eliminate latch-up because the n-channel and p-channel devices
are physically isolated by the filled trench.



Figure 4.55: Refilled deep trench between p-well and n-well


4 IC Fabrication, Layout, and Simulation

- 135 -
4.10 Scaling Theory

In order to achieve higher density logic integration, the approach is to develop
sub-micron size device structures. Effects which are negligible in large MOS
transistor become distinct and extremely important when the transistor
dimensions are reduced. Scaling theory provides a general guide to make MOS
transistor smaller. It is not possible or desirable to follow every aspects of the
theory. However, it remains a useful metric for measuring progress in device
physics especially the simulation or prediction of the behavior of the device
with smaller dimension.

Scaling theory deals with the question of how the device characteristics are
changed as the dimensions of the device are reduced in an idealized well-
defined manner. Scaling theory is ideal ignoring many small-device effects that
govern the performance of MOS transistor. It is often desirable to adhere to the
large device models for simplicity but modify the parameters to account for the
more important changes in the transistor parameters. Scaling of the device to
smaller dimension affects parameters such as threshold voltage and mobility.
Smaller channel length decreases the threshold voltage. Narrower device
increases threshold voltage. Small channel length increases horizontal electric
field that causes the MOS transistor to operate with saturation velocity. This
reduces the drain current of the device. High electric field means high energetic
carrier that can enter the oxide to become trapped charge and affects the
threshold voltage of the MOS transistor.

The drain and source of the MOS transistor are usually much heavily
doped than the bulk. Couple with high electric field, hot ion tunneling is
unavoidable. This issue causes leakage. In order to resolve this problem, lightly
doped drain LDD approach is adopted for the design of small dimension MOS
transistor.

Several schemes can be constructed from scaling rules shown in Fig. 4.56.
S is the dimensional scaling factor and k is factor by which voltages are scaled.
One of the earlier scaling methodologies is based on constant-field scaling,
which keep electrical field constant. In this method S is made equal to k. This
approach is theoretical viable that has to increase the speed, reduction of voltage
swing and capacitance. It is being used to scale to 1.0m. Scaling to 1.0m is in
fact closed to constant-voltage scaling, which is by making k = 1. In this
approach voltage swing stays the same, but device current increases due to
increase of oxide capacitance C
ox
. Since drive current increases roughly as the
4 IC Fabrication, Layout, and Simulation

- 136 -
square of supply voltage, constant-voltage produces more speed improvement
than constant-field scaling.

Parameters Variables Scaling Factor
Dimensions W, L, d
ox
, x
j
1/S
Potentials V
ds
, V
gs
1/k
Doping concentration N
A
, N
D
S
2
/k
Electric field E S/k
Current I
ds
S/k
2

Gate delay t
delay
k/S
2


Figure 4.56: Generalized scaling theory for MOS transistor

Using constant-voltage approach and considering a MOS transistor with a
channel width W and a channel length L such that the channel area is A = LW
and introducing the concept of a scaling factor S >1, a new scaled device is
created with reduced dimensions W and L where
S
W
W
'
= and
S
L
L
'
= . The
reduced scaled area A is equal to
2
'
S
A
A = . Similarly, the oxide thickness is
S
d
d
ox '
ox
= . Thus, the reduced oxide capacitance is
ox
ox
ox '
ox
SC
d
S C =

= . Similarly,
the reduced process parameter SK K
'
= and device parameter is = S
'
.
Threshold voltage
'
t
V and drain-to-source voltage
'
DS
V are to be scaled. With all
parameters being scaled down, the scaled down drain current is
S
I
I
D '
D
= .

Exercises

4.1. Extract the design rules of the 6 metals 0.12m technology from
Microwind layout software.

4.2. Taking into consideration of the SCMOS design rule, determine the
aspect ratio of an n-MOS transistor device.

4.3. Taking into consideration of the SCMOS design rule, determine the
aspect ratio of a p-MOS transistor device.

4.4. Given a two input NOR gate, using stick diagram to draw the layout of its
CMOS circuit.
4 IC Fabrication, Layout, and Simulation

- 137 -
4.5. Given a logic function f(A, B, C) = ( ) C B A + . Using Euler path to
optimize the final stick diagram of the circuit.

4.6. Determine the Euler path for logic function f(A, B, C, D, E)
= ) E D C B A ( + + .

4.7. Design the transistor level circuit of combinational circuit that has
function output = B ) D C ( A + + .

4.8. Design the layout of a 2-input AND gate.

4.9. Consider an n-MOS transistor that has a channel width W = 8m, a
channel length of L = 0.5m and is made with a process where K
n
=
180x10
-6
A/V
2
, V
tn
= 0.70V and V
DD
= 3.3V. Calculate the channel
resistance.

4.10. Calculate the output capacitance of the inverter shown in the figure. All
dimensions are shown in micron and the load capacitance is 50fF.

4.11. Given that the sheet resistance of the polysilicon is 4.0/ and the
capacitance per unit area of the polysilicon is 0.1fF/m
2
. Calculate the
time constant of a polysilicon polygon with structure shown in the figure,
width equals to 3 and the corner resistance is taken as 0.65 square.
4 IC Fabrication, Layout, and Simulation

- 138 -


Bibliography

1. John P. Uyemura, Chip Design for Submicron VLSI: CMOS Layout and
Simulation, Thomson, 2006.
2. John P. Uyemura, Introduction to VLSI Circuits and Systems, John
Wiley & Sons, Inc. 2002.
3. Etienne Sicard and Sonia Delmas Bendhia, Basics of CMOS Cell
Design, TATA McGraw Hill, 2006.
4. Sung-Mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuits
Analysis and Design, third edition, McGraw Hill, 2005.