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Lab 6 Report

This lab report describes the design of an SR flip-flop circuit using static CMOS technology. The report includes the schematic design with truth table, Eldo simulation results showing propagation delays, the IC layout, LVS and DRC checks confirming a correct layout, and conclusions stating the transistor count, layout size, and propagation delays.

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Vijay Preetham
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106 views

Lab 6 Report

This lab report describes the design of an SR flip-flop circuit using static CMOS technology. The report includes the schematic design with truth table, Eldo simulation results showing propagation delays, the IC layout, LVS and DRC checks confirming a correct layout, and conclusions stating the transistor count, layout size, and propagation delays.

Uploaded by

Vijay Preetham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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ECE 5540-100 DIGITAL ELECTRONICS

Lab 6 Report
Submitted to Dr. Janos L. Grantner
By Team2: Tarini Rajan and Vishwanath Preetham Kashyap
10/22/2014

Department of Electrical and Computer Engineering

Table of Contents

Lab Description and Design Approach ........................................................................................... 4


1.1

Objective: ................................................................................................................................ 4

1.2

Task:........................................................................................................................................ 4

1.3

Specifications: ......................................................................................................................... 4

Schematic Design............................................................................................................................ 5
2.1

Truth Table: ............................................................................................................................ 5

2.2

Design Architect: .................................................................................................................... 5

Eldo Simulation/ Xelga Viewer ...................................................................................................... 6

IC Layout Layout Graphics: ........................................................................................................ 7

LVS Report: .................................................................................................................................... 8

Calibre-based Post Layout DRC Checks: ....................................................................................... 8

Conclusion: ..................................................................................................................................... 9

Result .............................................................................................................................................. 9

Table of Figures

Figure 1: Truth Table ................................................................................................................. 5


Figure 2 Schematic Design ........................................................................................................ 5
Figure 3 Timing Diagram waveform ......................................................................................... 6
Figure 4 Propogation delay Tphl and Tplh ................................................................................ 6
Figure 5 IC layout ...................................................................................................................... 7
Figure 6 IC layout area .............................................................................................................. 7
Figure 7 LVS report ................................................................................................................... 8
Figure 8 DRC Report Summary ................................................................................................ 8

1
1.1

Lab Description and Design Approach


Objective:
1. Design a basic sequential logic circuit using static CMOS technology.
2. Develop a cell structure that can later be replicated for more complex designs.
3. Evaluate the performance of the circuit using Eldo and Xelga
4. Learn the layout editing commands in IcStation.
5. Perform parasitic extraction using Calibre xRC

1.2

Task:
1. Capture the schematic diagram of your SR FF using Design Architect.
2. Design a suitable functional simulation for the circuit using Eldo and Xelga. Verify
the logic function for the circuit on the basis of your simulation results.
3. Use Eldo and Xelga for transient analysis. From transient analysis, obtain TPHL, TPLH,
and TP. as well as the minimum and maximum clock frequencies, respectively. A 50%
duty cycle clock signal should be used for transient analysis.
4. Create a layout for the circuit.
5. Perform parasitic extraction.

1.3

Specifications:
You will develop a concise layout of a cell that implements a clocked CMOS 8transistor SR flip-flop, as it is given in Figure 7.21 of the Text.
The terminal configuration of the layout should allow access to all signals from both
top and bottom of the cell. The power lines should be on first-layer metal rails that pass
completely through the cell in a horizontal direction. This cell should be designed such
that it may be replicated in a horizontal direction. Be as generous as you can with the
widths of the power lines so that their current-carrying capacities will be reasonably
high. The minimum feature sizes for L and W are 1.2m and 2.0m, respectively.

2
2.1

Schematic Design
Truth Table:

Comment

No Change

Reset

Set

Invalid

Figure 1: Truth Table

2.2 Design Architect:

Figure 2 Schematic Design

Eldo Simulation/ Xelga Viewer

Figure 3 Timing Diagram waveform

Figure 4 Propogation delay Tphl and Tplh


Tplh = 26.223 Ns

Tphl= 25.355 Ns
6

Tp= (Tphl+Tplh)/2 = 25.789 Ns

IC Layout Layout Graphics:

Figure 5 IC layout

Figure 6 IC layout area


Area = 44*28.05 = 1234.2 sq area
7

LVS Report:

Figure 7 LVS report

Calibre-based Post Layout DRC Checks:

Figure 8 DRC Report Summary

Conclusion:
1. Transistor count = 8 inverters (2 PMOS and 6 NMOS)
2. IC layout size = 1234.2 sq area
3. Propagation delays = Tplh = 26.223 Ns

Tphl= 25.355 Ns

Tp= (Tphl+Tplh)/2 = 25.789 Ns

Result

SR Flip Flop was implemented using CMOS Logic. The schematic was successfully
simulated using Eldo and Xelga and also IC layout was created.

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