GLOBAL TECHNICAL CAMPUS

B. Tech II Year, IVSEM, Branch CSE

I MID TERM EXAMINATION
MICROPROCESSORS (4-CS-1A)

Duration:1.15 hrs Maximum Marks:20

Instruction to candidates: Attempt all questions
Q.1
(a) What do you mean by Addressing Mode? What are different types of addressing mode in 8085 instructions set?
Explain each addressing mode of 8085 with suitable example. (8)
OR
(b)Explain bus system in 8085 microprocessor. How the 8085 microprocessor uses the three bus system to fetch the
data 32H from the memory address 2500H. (8)
Q.2
(a) Design a memory and I/O interface to connect the following chips to 8085 microprocessor
(1)one 4K chip (2)one 16 K chip. (8)
OR
(b) What is InstructionCycle, Machine Cycle&T-states of 8085 microprocessor? Write different machine cycles.
Draw the timing diagram for the instruction MVI A, 05H. (8)
Q.3
(a) Explain the Interrupt structure of 8085 microprocessor, Describe the important pin signals and Instructions
involved in handling the Interrupts. (4)

OR
(b)Explain the Interrupts, Draw block diagram for programmable interrupt controller 8259.(4)
(4-CS-1A)

GLOBAL TECHNICAL CAMPUS

B. Tech II Year, IVSEM, Branch CSE
I MID TERM EXAMINATION
MICROPROCESSORS (4-CS-1A)
1. (A) What do you mean by Addressing Mode? What are different types of addressing mode in 8085
instructions set? Explain each addressing mode of 8085 with suitable example. [8]
Sol. The way by which the microprocessor identifies the operands for a particular instruction is known as
Addressing mode. The process of identifying the operands for a particular instruction can be carried out in
several ways. The various types of addressing modes are as shown below.

• Immediate addressing mode

• Direct addressing mode
• Register addressing mode
• Register indirect addressing mode
• Implicit addressing mode
Immediate Addressing Mode:
In this type of addressing mode the operand is specified within the instruction itself.
Let us discuss with an example.
Consider this instruction:
ADI 34H – This instruction adds the immediate data, 34H to the accumulator.
34H is the data here. H represents Hexadecimal value and the immediate value is added to the accumulator.
In this case 34H is added to the accumulator. Suppose if accumulator has a value 8H and when this
instruction is executed, 34H is added to the 8H and the result is stored in accumulator.
In the above instruction the operand is specified within instruction itself.
Direct Addressing Mode:
In this mode of addressing, the address of the data (operand) is specified within the instruction.
There is a subtle difference between the direct addressing modes and immediate addressing modes. In
immediate addressing mode the data itself is specified within instruction, but in direct addressing mode the
address of the data is specified in the instruction.
Example:
OUT 10H
LDA 4100H
STA 2000H
Consider the instruction STA 2000H
When this instruction is executed, the contents of the accumulator are stored in the memory location
specified. In the above example the contents of accumulator are stored in memory location 2000H.
Register Addressing Mode:
In this type of addressing mode the instruction specifies the name of the register in which the data is
available and Opcode specifies the name (or) address of the register on which the operation would be
performed.
Example:
MOV A, B
Here the Opcode is MOV. If the above instruction is executed, the contents of Register B are moved to the
Register A, which is nothing but the accumulator.
Register Indirect Addressing Mode:
This is indirect way of addressing. In this mode the instruction specifies the name of the register in which
the address of the data is available.
Example:
MOV A, M
SUB M
DCR M
Consider MOV A, M. This instruction will move the contents of memory location, whose address is in H-L
register pair to the accumulator.
M represents the address present in the H-L register pair. So when MOV A, M is executed, the contents of
the address specified in H-L register pair are moved to accumulator.
Implicit Addressing Mode:
There are certain instructions in 8085 which does not require the address of the operand to perform the
operation. They operate only upon the contents of accumulator.
Example:
CMA
RAL
RAR
CMA complements the contents of accumulator.
If RAL is executed the contents of accumulator is rotated left one bit through carry.
If RAR is executed the contents of accumulator is rotated right one bit through carry.

OR
(B)Explain bus system in 8085 microprocessor. How the 8085 microprocessor uses the three bus
system to fetch the data 32H from the memory address 2500H. [8]
Sol. There are three buses in Microprocessor:
1.Address Bus
2.Data Bus
3.Control Bus
1.Address Bus:-Genearlly, Microprocessor has 16 bit address bus. The bus over which the CPU sends out
the address of the memory location is known as Address bus. The address bus carries the address of memory
location to be written or to be read from.
The address bus is unidirectional. It means bits flowing occurs only in one direction, only from
microprocessor to peripheral devices.
2.Data Bus:-8085 Microprocessor has 8 bit data bus. So it can be used to carry the 8 bit data starting from
00000000H(00H) to 11111111H(FFH). Here 'H' tells the Hexadecimal Number. It is bidirectional. These
lines are used for data flowing in both direction means data can be transferred or can be received through
these lines. The data bus also connects the I/O ports and CPU. The largest number that can appear on the
data bus is 11111111.
3.Control Bus:-The control bus is used for sending control signals to the memory and I/O devices. The CPU
sends control signal on the control bus to enable the outputs of addressed memory devices or I/O port
devices.
Some of the control bus signals are as follows:
1.Memory read
2.Memory write
3.I/O read
4.I/O write.
fetching the data 32H from the memory address 2500H

Data Bus

2. (A) Design a memory and I/O interface to connect the following chips to 8085 microprocessor [8]
(1)one 4K chip (2)one 16 K chip.
Address Range for 16 KB memory Chip
Initial Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Final Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Address Range for 4 KB memory Chip

Initial Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 X X 0 0 0 0 0 0 0 0 0 0 0 0
Final Address
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 0 X X 1 1 1 1 1 1 1 1 1 1 1 1

Multiple Addresses can be generated using different values of A13 and A12

OR

(B) What is InstructionCycle, Machine Cycle&T-states of 8085 microprocessor? Write different machine
cycles. Draw the timing diagram for the instruction MVI A, 05H. [8]

MEMORY ADDRESS HEX CODE INSTRUCTION

3020 XX MVI A, 05H

3021 05
Sol. Instruction cycle: The time a microprocessor needs to fetch and execute one entire instruction is
known as an instruction cycle.

Machine cycle:

The basic microprocessor operation such as reading a byte from I/O port or writing a byte to memory is
called as machine cycle. a machine cycle consists of several T-states.

The different types of machine cycle available in 8085 microprocessor are:

• Opcode Fetch
• Memory Read
• Memory write
• I/O Read
• I/O Write
• INTR Acknowledge
• Bus Idle
T-state:

One complete cycle of clock is called as T-state A T-state is measured from the falling edge of one clock
pulse to the falling edge of the next clock pulse.
3 Explain the Interrupt structure of 8085 microprocessor, Describe the important pin signals and
Instructions involved in handling the Interrupts.
[4]

Sol. Interrupt is signals send by an external device to the processor, to request the processor to perform a
particular task or work.

Mainly in the microprocessor based system the interrupts are used for data transfer between the
peripheral and the microprocessor.

The processor will check the interrupts always at the 2nd T-state of last machine cycle.

If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.

The vectored address of particular interrupt is stored in program counter.

The processor executes an interrupt service routine (ISR) addressed in program counter.

It returned to main program by RET instruction.

Types of Interrupts:

It supports two types of interrupts.

Hardware

Software

Software interrupts:

The software interrupts are program instructions. These instructions are inserted at desired locations in a
program.

The 8085 has eight software interrupts from RST 0 to RST 7. The vector address for these interrupts can
be calculated as follows.

Interrupt number * 8 = vector address

For RST 5,5 * 8 = 40 = 28H

Vector address for interrupt RST 5 is 0028H

Hardware interrupts:
• An external device initiates the hardware interrupts and placing an appropriate signal at the
interrupt pin of the processor.
• If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

(1) TRAP (2) RST 7.5 (3) RST 6.5 (4) RST 5.5 (5) INTR

TRAP:
• This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.
• TRAP bas the highest priority and vectored interrupt.
• TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain
high until it is acknowledged.
• In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
• The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
• There are two ways to clear TRAP interrupt.

1.By resetting microprocessor (External signal)

2.By giving a high TRAP ACKNOWLEDGE (Internal signal)

RST 7.5:

The RST 7.5 interrupt is a maskable interrupt.

• It has the second highest priority.
• It is edge sensitive. ie. Input goes to high and no need to maintain high state until it recognized.
• Maskable interrupt. It is disabled by,

1.DI instruction

2.System or processor reset.

3.After reorganization of interrupt.

• Enabled by EI instruction.

RST 6.5 and 5.5:

• The RST 6.5 and RST 5.5 both are level triggered. . ie. Input goes to high and stay high until it
recognized.
• Maskable interrupt. It is disabled by,

1.DI, SIM instruction

2.System or processor reset.

3.After reorganization of interrupt.

• Enabled by EI instruction.
• The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.

INTR:
• INTR is a maskable interrupt. It is disabled by,

1.DI, SIM instruction

2.System or processor reset.

3.After reorganization of interrupt.

• Enabled by EI instruction.
• Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the address of
ISR.
• It has lowest priority.
• It is a level sensitive interrupts. i.e. Input goes to high and it is necessary to maintain high state
until it recognized.
• The following sequence of events occurs when INTR signal goes high.

· 1. The 8085 checks the status of INTR signal during execution of each instruction.

· 2. If INTR signal is high, then 8085 complete its current instruction and sends active low interrupt
acknowledge signal, if the interrupt is enabled.

· 3. In response to the acknowledge signal, external logic places an instruction OPCODE on the data
bus. In the case of multibyte instruction, additional interrupt acknowledge machine cycles are generated
by the 8085 to transfer the additional bytes into the microprocessor.

· 4. On receiving the instruction, the 8085 save the address of next instruction on stack and execute
received instruction.

SIM and RIM for interrupts:

• The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using SIM
instruction.
• The status of these interrupts can be read by executing RIM instruction.
• The masking or unmasking of RST 7.5, RST 6.5 and RST 5.5 interrupts can be performed by
moving an 8-bit data to accumulator and then executing SIM instruction.
• The format of the 8-bit data is shown below.
3 Explain the Interrupts, Draw block diagram for programmable interrupt controller 8259. [4]

Sol. Interrupt is signals send by an external device to the processor, to request the processor to perform
a particular task or work.
Features of 8259:

• It is a LSI chip which manages 8 levels of interrupts i.e. it is used to implement 8 level interrupt systems.
• It can be cascaded in a master slave configuration to handle up to 64 levels of interrupts.
• It can identify the interrupting device.
• It can resolve the priority of interrupt requests i.e. it does not require any external priority resolver.
• It can be operated in various priority modes such as fixed priority and rotating priority.
• The interrupt requests are individually mask-able.
• The operating modes and masks may be dynamically changed by the software at any time during
execution of programs.
• It accepts requests from the peripherals, determines priority of incoming request, checks whether the
incoming request has a higher priority value than the level currently being serviced and issues an interrupt
signal to the microprocessor.
• It provides 8 bit vector number as an interrupt information.
• It does not require clock signal.
• It can be used in polled as well as interrupt modes.
• The starting address of vector number is programmable.
• It can be used in buffered mode.
The block diagram of 8259 is shown in the figure below:
It contains following blocks-
Data bus buffer-
It is used to transfer data between microprocessor and internal bus.
Read/write logic-
It sets the direction of data bus buffer.
It controls all internal read/write operations.
It contains initialization and operation command registers.
Cascaded buffer and comparator-
In master mode, it functions as a cascaded buffer. The cascaded buffers outputs slave identification
number on cascade lines.
In slave mode, it functions as a comparator. The comparator reads slave identification number from
cascade lines and compares this number with its internal identification number.

In buffered mode, it generates an (EN) ̅ signal.

Control logic-

It generates an INT signal. In response to an (INTA) ̅ signal, it releases three byte CALL address or one
byte vector number.
It controls read/write control logic, cascade buffer/comparator, in service register, priority resolver and
IRR.
Interrupt request register-
It is used to store all pending interrupt requests.
Each bit of this register is set at the rising edge or at the high level of the corresponding interrupt request
line.
The microprocessor can read contents of this register by issuing appropriate command word.
In service register (InSR)-
It is used to store all interrupt levels currently being serviced.
Each bit of this register is set by priority resolver and reset by end of interrupt command word.
The microprocessor can read contents of this register by issuing appropriate command word.
Priority resolver-
It determines the priorities of the bit set in the IRR. To make decision, the priority resolver looks at the
ISR.
If the higher priority bit in the InSR is set then it ignores the new request.
If the priority resolvers find that the new interrupt has a higher priority than the highest priority interrupt
currently being serviced and the new interrupt is not in service, then it will set appropriate bit in the InSR
and send the INT signal to the microprocessor for new interrupt request.
Interrupt mask register (IMR)-
It is a programmable register.
It is used to mask unwanted interrupt request by writing appropriate command word.
The microprocessor can read contents of this register without issuing any command word.
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GLOBAL TECHNICAL CAMPUS Jaipur
GIT/GCT
B.Tech.CS – IV Sem. (I mid Term 2018)
Duration: 1:15Hrs Subject: SOFTWARE ENGINEERING (4CS4A) Branch: CSE
Max marks-20

Q.1 Discuss the problems in system development and their probable solutions? (8)
OR
Q.1 Explain the characteristics of good software?

Q.2Explain Component Based Development Model? Write its advantages and disadvantages?
OR (8)
Q.2Differentiate Waterfall, Incremental, Spiral and RAD Model?

Q.3Explain Finite State Machine with example? (4)

OR
Q.3Draw DFD (0 & 1 level) for online shopping system?
1. Problems in developing Software

Software Implementation Challenges

There are some challenges faced by the development team while implementing the
software. Some of them are mentioned below:

 Code-reuse - Programming interfaces of present-day languages are very sophisticated

and are equipped huge library functions. Still, to bring the cost down of end product, the
organization management prefers to re-use the code, which was created earlier for some
other software. There are huge issues faced by programmers for compatibility checks and
deciding how much code to re-use.
 Version Management - Every time a new software is issued to the customer, developers
have to maintain version and configuration related documentation. This documentation
needs to be highly accurate and available on time.
 Target-Host - The software program, which is being developed in the organization,
needs to be designed for host machines at the customers end. But at times, it is impossible
to design a software that works on the target machines.

2. Character tics of Good Software

software quality model identifies 6 main quality characteristics, namely:

 Functionality

 Reliability

 Usability

 Efficiency

 Maintainability

 Portability

3. Component based development model

Component Based Software Engineering and its Limitations

According to various studies in the field of Software engineering, the first successful component
system was the operating system .Operating systems can be used as a basis to understand the
concept of component based models and their implementations. Today, everyone has a basic idea
about the operating system. The operating system provides an interface between the user and the
hardware of the system. In addition, it provides an environment to execute any application. It
also allows resource access and allocation. Other basic services provided by operating system
include memory management, resource management, file management, process synchronization,
etc. There are various services, which simplifies the development of an application. These
services are used by different applications through a defined interface. Such interfaces are called
application programming interfaces (APIs). Relating it to the component model, such operating
systems are implemented using the component model. Applications are developed by various
developers after the component model implementation is developed and documented. Such
applications can be purchased from the developers or the vendors. These applications are
designed to be supported across different operating system platforms and hence can be used
together on a single computer. The standards used in the applications match the operating system
standards. However, there are few standards which match some specific operating system
standards. Hence, they are often part of a particular operating system implementation.

Limitations of Early Component Systems

In spite of the fact that the components can be used at the application level they lack the re-
usability factor. This is because of the lack of domain-specific standards for the operating system
and the lack of proper support. In addition, many application developers use the same prototype
already being used by the other developers implementing common functionalities. However,
component based software engineering (CBSE) tries to make the best out of it. The CBSE
approach separates the common factor into either the component based services or the
components that can be integrated into a single component infrastructure. It also plans attain a
certain degree of re-usability at the application level. However, the two major limitations are
mentioned below.

No composition support – There has been no support for composition at any level. In an
operating system the application is executed independently with no interaction with other
application. Data Exchange among the application is possible by the mechanism of inter-process
communication. However, the applications are not properly specified in spite of the application
using the services of the operating system.

No domain-specific standards – In general the operating system services do not support any
specific application domains. For example, a simulation system has a different set of
requirements as compared to a telecommunication application. Having reusable components in a
software system is the main goal of component based software engineering. Such reusable
components exist at a finer granularity level. In addition, they require various standards for
services, infrastructure, interaction and composition. By building such a model; the component
based software engineering can design, implement, and deploy the component infrastructures.

4.

Properties of Water-Fall Incremental Spiral Rad Model

Model Model Model Model

Planning in Yes Yes Yes No

early stage
Returning to an No Yes Yes Yes
earlier phase

Handle Large- Not Not Appropriate Not

Project Appropriate Appropriate Appropriate

Detailed Necessary Yes but not Yes Limited

Documentation much

Cost Low Low Expensive Low

Requirement Beginning Beginning Beginning Time boxed

Specifications release

Flexibility to Difficult Easy Easy Easy

change
User Only at Intermediate High Only at the
Involvement beginning beginning

Maintenance Least Promotes Typical Easily

Maintainability Maintained

Duration Long Very long Long Short

Risk High Low Medium to Low

Involvement high risk

Framework Linear Linear + Linear + Linear

Type Iterative Iterative

Testing After After every At the end After

completion iteration of the completion
of coding engineering of coding
phase phase
Overlapping No Yes (As No Yes
Phases parallel
development is
there)

Maintenance Least Maintainable Yes Easily

Maintainable Maintainable

Re-usability Least To some extent To some Yes

possible extent

Time-Frame Very Long Long Long Short

Working At the end of At the end of At the end At the end of

software the life-cycle every iteration of every the life cycle
availability iteration

Objective High Rapid High Rapid

Assurance Development Assurance development

Team size Large Team Not Large Large Team Small Team
Team

Customer Very Low Yes Yes Yes

control over
administrator

5. Finite state machine

In general, a state machine is any device that stores the status of something at a given time and
can operate on input to change the status and/or cause an action or output to take place for any
given change. A computer is basically a state machine and each machine instruction is input that
changes one or more states and may cause other actions to take place. Each computer's data
register stores a state. The read-only memory from which a boot program is loaded stores a state
(the boot program itself is an initial state). The operating system is itself a state and
each application that runs begins with some initial state that may change as it begins to handle
input. Thus, at any moment in time, a computer system can be seen as a very complex set of
states and each program in it as a state machine. In practice, however, state machines are used to
develop and describe specific device or program interactions.
To summarize it, a state machine can be described as:

 An initial state or record of something stored someplace

 A set of possible input events
 A set of new states that may result from the input
 A set of possible actions or output events that result from a new state

In their book Real-time Object-oriented Modeling, Bran Selic & Garth Gullekson view a state
machine as:

 A set of input events

 A set of output events
 A set of states
 A function that maps states and input to output
 A function that maps states and inputs to states (which is called a state transition
function)
 A description of the initial state

A finite state machine is one that has a limited or finite number of possible states. (An infinite
state machine can be conceived but is not practical.) A finite state machine can be used both as a
development tool for approaching and solving problems and as a formal way of describing the
solution for later developers and system maintainers. There are a number of ways to show state
machines, from simple tables through graphically animated illustrations.
6. DFD

Using any convention’s DFD rules or guidelines, the symbols depict the four components of data
flow diagrams.

1. External entity: an outside system that sends or receives data, communicating with the
system being diagrammed. They are the sources and destinations of information entering
or leaving the system. They might be an outside organization or person, a computer
system or a business system. They are also known as terminators, sources and sinks or
actors. They are typically drawn on the edges of the diagram.
2. Process: any process that changes the data, producing an output. It might perform
computations, or sort data based on logic, or direct the data flow based on business rules.
A short label is used to describe the process, such as “Submit payment.”
3. Data store: files or repositories that hold information for later use, such as a database
table or a membership form. Each data store receives a simple label, such as “Orders.”
4. Data flow: the route that data takes between the external entities, processes and data
stores. It portrays the interface between the other components and is shown with arrows,
typically labeled with a short data name, like “Billing details.”

While developing any kind of software product, the first question in any developer's mind is,
“What are the qualities that a good software should have ?" Well before going into technical
characteristics, I would like to state the obvious expectations one has from any software. First
and foremost, a software product must meet all the requirements of the customer or end-user.
Also, the cost of developing and maintaining the software should be low. The development of
software should be completed in the specified time-frame.
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