M AN754

Understanding Microchip’s CAN Module Bit Timing

Author: Pat Richards

Nominal Bit Time
Microchip Technology Inc. The Nominal Bit Time (NBT), or tbit, is made up of non-
overlapping segments (Figure 1), therefore, the NBT is
INTRODUCTION the summation of the following segments:

The Controller Area Network (CAN) protocol is an t bit = tSyncSeg + t PropSeg + tPS1 + t PS2
asynchronous serial bus with Non-Return to Zero
(NRZ) bit coding designed for fast, robust communica-
tions in harsh environments, such as automotive and Associated with the NBT are the Sample Point, Syn-
industrial applications. The CAN protocol allows the chronization Jump Width (SJW), and Information Pro-
user to program the bit rate, the sample point of the bit, cessing Time (IPT), which are explained later.
and the number of times the bit is sampled. With these
features, the network can be optimized for a given SYNCHRONIZATION SEGMENT
application.
The Synchronization Segment (SyncSeg) is the first
There are relationships between bit timing parameters, segment in the NBT and is used to synchronize the
the physical bus propagation delays, and the oscillator nodes on the bus. Bit edges are expected to occur
tolerances throughout the system. This application within the SyncSeg. This segment is fixed at 1TQ.
note investigates these relationships as they pertain to
Microchip’s CAN module and assists in optimizing the PROPAGATION SEGMENT
bit timing for given physical system attributes.
The Propagation Segment (PropSeg) exists to com-
pensate for physical delays between nodes. The prop-
THE CAN BIT TIME agation delay is defined as twice the sum of the signal’s
The CAN bit time is made up of non-overlapping seg- propagation time on the bus line, including the delays
ments. Each of these segments are made up of integer associated with the bus driver. The PropSeg is pro-
units called Time Quanta (TQ) and are explained later grammable from 1 - 8TQ.
in this application note. The Nominal Bit Rate (NBR) is
defined in the CAN specification as the number of bits PHASE SEGMENT 1 AND PHASE SEGMENT 2
per second transmitted by an ideal transmitter with no The two phase segments, PS1 and PS2 are used to
resynchronization and can be described with the compensate for edge phase errors on the bus. PS1 can
equation: be lengthened or PS2 can be shortened by resyncroni-
1 zation. PS1 is programmable from 1 - 8TQ and PS2 is
NBR = f bit = -------
t bit programmable from 2 - 8TQ.

FIGURE 1: CAN BIT TIME SEGMENTS

SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)

Sample
Point
Nominal Bit Time (NBT), tbit

 2001 Microchip Technology Inc. DS00754A-page 1

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SAMPLE POINT Time Quantum
The sample point is the point in the bit time in which the Each of the segments that make up a bit time are made
logic level is read and interpreted. The sample point is up of integer units called Time Quanta (TQ). The length
located at the end of phase segment 1. The exception of each Time Quantum is based on the oscillator period
to this rule is, if the sample mode is configured to sam- (tOSC). The base TQ equals twice the oscillator period.
ple three times per bit. In this case, the bit is still sam- Figure 2 shows how the bit period is derived from TOSC
pled at the end of PS1, however, two additional and TQ. The TQ length equals one TQ Clock period
samples are taken at one-half TQ intervals prior to the (tBRPCLK), which is programmable using a programma-
end of PS1 and the value of the bit is determined by a ble prescaler named the Baud Rate Prescaler (BRP).
majority decision. This is shown in the following equation:

INFORMATION PROCESSING TIME 2 ⋅ BRP

TQ = 2 ⋅ BRP ⋅ T OSC = -------------------
F OSC
The Information Processing Time (IPT) is the time
required for the logic to determine the bit level of a sam-
pled bit. The IPT begins at the sample point, is mea- Where: BRP equals the configuration as shown in
sured in TQ and is fixed at 2TQ for the Microchip CAN Figure 3.
module. Since phase segment 2 also begins at the
sample point and is the last segment in the bit time, it is Bit Timing Control Registers
required that PS2 minimum is not less than the IPT.
The CAN Bit Timing Control (CNF) registers are the
Therefore: three registers that configure the CAN bit time. Figure 3
details the function of the CNF registers.
PS2 min = IPT = 2TQ
By adjusting the length of the TQ (tTQ) and the number
of TQs in each segment, both the nominal bit time and
the sample point can easily be configured as desired.
SYNCHRONIZATION JUMP WIDTH
The Synchronization Jump Width (SJW) adjusts the bit PROGRAMMING THE TIMING SEGMENTS
clock as necessary by 1 - 4TQ (as configured) to main-
The are several requirements for programming the
tain synchronization with the transmitted message.
CAN bit timing segments.
More on synchronization is covered later.
1. PropSeg + PS1 ≥ PS2
2. PropSeg + PS1 ≥ tPROP
3. PS2 > SJW

FIGURE 2: TQ AND THE BIT PERIOD

tosc

TBRPCLK

Sync PropSeg PS1 PS2

tBIT (fixed) (Programmable) (Programmable) (Programmable)

TQ
(tTQ)

CAN Bit Time

DS00754A-page 2  2001 Microchip Technology Inc.

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FIGURE 3: CAN BIT TIMING CONTROL REGISTERS (MCP2510 CNF REGISTERS)

CNF1 SJW.1 SJW.0 BRP.5 BRP.4 BRP.3 BRP.2 BRP.1 BRP.0

bit 7 bit 0
SJW<1:0> (Synchronization Jump Width Length as measured in TQ):
11 = 4TQ
10 = 3TQ
01 = 2TQ
00 = 1TQ

BRP<5:0> (Baud Rate Prescaler TQ length as a multiple of tosc)

111111 = TQ = 2 x 64 x tOSC
. .
. .
. .
000010 = TQ = 2 x 3 x tOSC
000001 = TQ = 2 x 2 x tOSC
000000 = TQ = 2 x 1 x tOSC

CNF2 BTLMODE SAM PS1.2 PS1.1 PS1.0 PRSEG.2 PRSEG.1 PRSEG.0

bit 7 bit 0

BTLMODE (Determines how PS2 is calculated)

1 = PS2 is determined by CNF3.PS2<2:0>
0 = PS2 is the greater of PS1 and the Information Processing Time (IPT)

SAM (Configures the sample point as one sample or three samples

1 = Sample three times per bit
0 = Sample once per bit

PS1<2:0> (Configures Phase Segment 1)

111 = 8TQ
. .
. .
001 = 2TQ
000 = 1TQ

PRSEG<2:0> (Configures the Propagation Segment)

111 = 8TQ
. .
. .
001 = 2TQ
000 = 1TQ

CNF3 --- WAKFIL --- --- --- PHSEG22 PHSEG21 PHSEG20

bit 7 bit 0
WAKFIL (Enables/Disables the wakeup filter)
1 = Filter enabled
0 = Filter disabled

PS2<2:0> (Configures Phase Segment 2)

111 = 8TQ
. .
. .
001 = 2TQ
000 = Not Valid (PS2MIN = IPT = 2TQ)

 2001 Microchip Technology Inc. DS00754A-page 3

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SYNCHRONIZING THE BIT TIME A CAN system’s propagation delay is calculated as
being a signal’s round trip time on the physical bus
All nodes on the CAN bus must have the same nominal (tbus), the output driver delay (tdrv), and the input com-
bit rate. Noise, phase shifts, and oscillator drift create parator delay (tcmp). Assuming all nodes in the system
situations where the nominal bit rate does not equal the have similar component delays, the propagation delay
actual bit rate in a real system. Therefore, the nodes is explained mathematically as:
must have a method for achieving and maintaining syn-
chronization with bus messages.
t prop = 2 ⋅ ( tbus + tcmp + t drv )
Oscillator Tolerance
The bit timing for each node in a CAN system is derived
from the reference frequency (fOSC) of its node. This
Synchronization
creates a situation where phase shifting and oscillator All nodes on a given CAN bus must have the same
drift will occur between nodes due to less than ideal NBT. The NRZ bit coding does not encode a clock into
oscillator tolerances between the nodes. the message. The receivers must synchronize to the
The CAN specification indicates that the worst case transmitted data stream to insure messages are prop-
oscillator tolerance is 1.58% and is only suitable for low erly decoded. There are two methods used for achiev-
bit rates (125 kb/s or less). This application note does ing and maintaining synchronization.
not cover oscillator tolerances in detail, however, the
references at the end of this application note provide HARD SYNCHRONIZATION
more information on the subject. Hard Synchronization only occurs on the first reces-
sive-to-dominant (logic “1” to “0”) edge during a bus idle
Propagation Delay condition, which indicates a Start-of-Frame (SOF) con-
The CAN protocol has defined a recessive (logic 1) and dition. Hard synchronization causes the bit timing
dominant (logic 0) state to implement a non-destructive counter to be reset to the SyncSeg which causes the
bit-wise arbitration scheme. It is this arbitration method- edge to lie within the SyncSeg. At this point, all of the
ology that is affected the most by propagation delays. receivers will be synchronized to the transmitter.
Each node involved with arbitration must be able to Hard synchronization occurs only once during a mes-
sample each bit level within the same bit time. For sage. Also, resynchronization may not occur during the
example, if two nodes at opposite ends of the bus start same bit time (SOF) that hard synchronization
to transmit their messages at the same time, they must occurred.
arbitrate for control of the bus. This arbitration is only
effective if both nodes are able to sample during the
same bit time. Figure 4 shows a one-way propagation
delay between two nodes. Extreme propagation delays
(beyond the sample point) will result in invalid arbitra-
tion. This implies that bus lengths are limited at given
CAN data rates.

DS00754A-page 4  2001 Microchip Technology Inc.

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FIGURE 4: ONE WAY PROPAGATION DELAY

Transmitted Bit from “Node A”

SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)

Sample Point
Propagation Delay

“Node A” bit received by “Node B”

SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)

Time (t)

 2001 Microchip Technology Inc. DS00754A-page 5

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RESYNCHRONIZATION SyncSeg) and adjusting the bit time as necessary.
Resynchronization is implemented to maintain the ini- The phase error of a bit is given by the position of the
tial synchronization that was established by the hard edge in relation to the SyncSeg, measured in TQ, and
synchronization. Without resynchronization, the receiv- is defined as follows:
ing nodes could get out of synchronization due to oscil- • e = 0; the edge lies within the SyncSeg.
lator drift between nodes. • e > 0; the edge lies before the sample point. (TQ
Resynchronization is achieved by implementing a Dig- added to PS1).
ital Phase Lock Loop (DPLL) function which compares • e < 0; the edge lies after the sample point of the
the actual position of a recessive-to-dominant edge on previous bit. (TQ subtracted from PS2)
the bus to the position of the expected edge (within the

FIGURE 5: SYNCHRONIZING THE BIT TIME

Input Signal (e = 0)

PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point

Nominal Bit Time (NBT)

No Resynchronization (e = 0)

Input Signal
(e > 0)

PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point
Nominal Bit Time (NBT)

Actual Bit Time

Resynchronization to a Slower Transmitter (e > 0)

Input Signal (e < 0)

PhaseSeg2 (PS2)
SyncSeg PropSeg PhaseSeg1 (PS1)
SJW (PS2)
SJW (PS1)
Sample
Point

Nominal Bit Time (NBT)

Actual Bit Time

Resynchronization to a Faster Transmitter (e < 0)

DS00754A-page 6  2001 Microchip Technology Inc.

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Figure 5 shows how phase errors, other than zero, Resynchronization can only occur on recessive-to-
cause the bit time to be lengthened or shortened. dominant edges. This implies that there can be a max-
imum of ten bits between resynchronization due to bit
Synchronization Rules: stuffing (Figure 6).
1. Only recessive-to-dominant edges will be used The oscillator tolerance between the slowest node and
for synchronization. the fastest node can be used to determine the mini-
2. Only one synchronization within one bit time is mum SJW. Assuming Node A is the slow node (longest
allowed. bit time) and Node B is the fast node (shortest bit
3. An edge will be used for synchronization only if time):
the value at the previous sample point differs 10tbit ( A ) > 10tbit ( B ) + t SJW ( B )
from the bus value immediately after the edge.
4. A transmitting node will not resynchronize on a
Where:
positive phase error (e > 0). This implies that a
transmitter will not resynchronize due to propa- tbit(n) = bit time of node “n”
gation delays of it’s own transmitted message. tSJW(n) = SJW of node “n”
The receivers will synchronize normally.
5. If the absolute magnitude of the phase error is FIGURE 6: MAXIMUM TIME BETWEEN
greater than the SJW, then the appropriate SYNCHRONIZATION EDGES
phase segment will be adjusted by an amount
equal to the SJW.
Synchronization
PUTTING IT ALL TOGETHER Edge

As indicated previously, the CAN protocol implements

a non-destructive bitwise arbitration scheme that
allows multiple nodes to arbitrate for control of the bus.
Therefore, it is necessary for all the nodes to detect/
sample the bits within the same bit time. The relation-
ship between propagation delay and oscillator toler-
ance effect both the CAN data rate and the bus length. Bit
Time
Table 1 shows some commonly accepted bus lengths
versus data rates.
This application note does not cover all of the details for
configuring the bit time for all scenarios, however, EXAMPLE 1: Find Minimum SJW
some general methodologies for configuring the CAN Given:
bit time are covered.
Nominal Bit Time = 1 µs
TABLE 1: CAN BIT RATE VS. BUS
Oscillator tolerance = 1.25%
LENGTH
Note: #TQ per bit = 8
Bit Rate (kb/s) Bus Length (m)
Find SJW minimum:
1000 30
tbit(A) = 1.01200 µs
500 100
tbit(B) = 0.98875 µs
250 250
TQ(A) = 126.563 ns
125 500
62.5 1000 TQ(B) = 123.438 ns
Using equation above:
Calculating Oscillator Tolerance for SJW tSJW(B) > 10tbit(A) - 10tbit(B) = 0.250 µs

The bit stuffing rule guarantees that no more than five #TQSJW > tSJW(B) / TQ(B) = 250 ns / 123.44 ns
like bits in a row will be transmitted during a message = 2.025
frame. The only exception is at the end of the message #TQSJW = 3
that includes ten recessive bits (one ACK delimiter,
seven end-of-frame bits, and three interframe space
bits).

 2001 Microchip Technology Inc. DS00754A-page 7

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Alternatively, the following equation can be used to EXAMPLE 2: Maximum Oscillator
maintain synchronization during normal bus Tolerance
operation:
The maximum oscillator tolerance for a maximum data
SJW > ( 2 ∆ f ) ( 10NBT ) rate is achieved when the phase segments 1 and 2 are
equal to the maximum synchronization jump width
(4TQ). Also, the propagation segment is minimum, indi-
Solving for Oscillator Tolerance (∆f) cating a short bus and fast transceiver.
As indicated earlier, the propagation delay is twice the
∆ f < SJW ⁄ 20NBT
delays of the bus, the receiver circuitry, and the driver.

t prop = 2 ( t bus + tcmp + t drv )

Configuring the Bit
In general, the longer the bus, the slower the maximum
data rate due to propagation delays on the line. Given:
Increasing the oscillator tolerances between nodes can tBUS = 50 m @ 5.5 ns/m = 275 ns
greatly amplify the relationship.
tCMP = 40 ns
CAN system designers must take this relationship into
consideration when defining the network. The following tDRV = 60 ns
examples demonstrate bit timings for achieving maxi- tPROP = 2(tBUS+tCMP+tDRV) = 750 ns
mum oscillator tolerance or maximum bit rate. Since the propagation segment is used to compensate
for propagation delays and must be set to the minimum
1TQ, the implied time quantum = tPROP = 750 ns.
Figure 7 shows the bit timing.

FIGURE 7: BIT TIMING FOR MAXIMUM OSCILLATOR TOLERANCE

SyncSeg PropSeg PhaseSeg1 (PS1) PhaseSeg2 (PS2)

TQ

Nominal Bit Time (NBT), tbit

TQ = tPROP = 750 ns
tbit = 10TQ = 7.5 µs → 133.3 kb/s
SyncSeg = 1TQ
PropSeg = tPROP = 1TQ
PS1 = SJWMAX = 4TQ
PS2 = SJWMAX = 4TQ
SJWMAX = 0.4NBT = 4TQ

DS00754A-page 8  2001 Microchip Technology Inc.

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EXAMPLE 3: Maximum Bit Rate Given the same delays as the previous example:
The previous example showed that for a given bus tBUS = 50 m @ 5.5 ns/m = 275 ns
length, the maximum data rate is inversely affected, tCMP = 40 ns
due to oscillator tolerance (as oscillator tolerance goes
tDRV = 60 ns
up, the data rate goes down). To achieve the maximum
bit rate for a given bus length, the emphasis is placed tPROP = 2(tBUS+tCMP+tDRV) = 750 ns
on configuring the bit time for the propagation delays Since the oscillator tolerance is minimum, the phase
(i.e., adjusting PropSeg to maximum). The oscillator segments and SJW can be set to the minimum. Assum-
tolerance must be minimized. ing the bit time is 10TQ total, the PropSeg can be set to
6TQ which sets TQ = 125 ns. Figure 8 shows the bit
timing for maximum bit rate.

FIGURE 8: BIT TIMING FOR MAXIMUM BIT RATE

SyncSeg PropSeg PS1 PS2

TQ

Nominal Bit Time (NBT), tbit

TQ = tPROP / 6 = 125 ns
tbit = 10TQ = 1.25 µs → 800 kb/s
SyncSeg = 1TQ
PropSeg = tPROP = 6TQ
PS1 = 1TQ
PS2 = 2TQ
SJWMAX = 1TQ

REFERENCES CONCLUSION
MCP2510 Data Sheet, DS21291, Microchip Technol- Setting up CAN bit timing is not an arbitrary process.
ogy, Inc. The system designer must be aware of the compo-
Lawrenz, Wolfhard, “CAN System Engineering From nents that affect bit timing and compensate to get opti-
Theory to Practical Applications”, Springer, 1997 mal performance across the network. For example, if
the desired system uses oscillators with the maximum
“CAN Specification”, Version 2.0, Parts A and B, Robert tolerance, the maximum bus length is reduced. Like-
Bosch GmbH, 1991 wise, if maximum bus length is desired, the oscillator
“ISO11898”, International Standards Organization, tolerances must be minimized. CAN data rates must
1993 also be considered because the data rate is a third vari-
Controller Area Network (CAN) Basics, DS00713 able that determines maximum length and maximum
oscillator tolerances.
PIC18C Reference Manual, DS39500
This application note should help assist system engi-
PIC18C58 Datasheet, DS30475 neers design a controller area network for optimal per-
formance based on requirements of the system.

 2001 Microchip Technology Inc. DS00754A-page 9

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DEFINITION OF TERMS
Dominant bit - Logic 0, overrides a recessive bit during
arbitration.
Recessive bit - Logic 1.
CAN Node - A point in the network where CAN commu-
nications is connected.
Nominal Bit Time (NBT) - The length of a transmitted bit
by an ideal transmitter with no resynchronization.
CAN - Controller Area Network.
Nominal Bit Rate (NBR) - The number of bits per sec-
ond transmitted by an ideal transmitter.
Propagation Delay - Signals round trip time on the
physical bus.
Hard Synchronization - Resets the receiving nodes bit
timers. Occurs only at Start Of Frame (SOF).
Resynchronization - Maintains synchronization by
adjusting the bits as needed.
Information Processing Time (IPT) - The time required
to determine the bit level. Begins at the sample point.
Start Of Frame (SOF) - The first dominate bit during
bus idle. Indicates a start of frame.
Sample Point - Position within the bit where the logic
level is sampled.

DS00754A-page 10  2001 Microchip Technology Inc.

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NOTES:

 2001 Microchip Technology Inc. DS00754A-page 11

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 2001 Microchip Technology Inc. DS00754A-page 11

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DS00754A-page 12  2001 Microchip Technology Inc.