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Improved Cascode Current Mirror

The ‘classic’ cascode current sink is shown in Figure 1.

VDD

IREF
IOUT

Vout
M1 M2
2VSAT + VT
2V SAT + 2 VT

M3 M4
VSAT + VT

VSS

VDSAT + VT
Figure 1 Cascode current source, showing that the minimum voltage output is
2VSAT+VT above the rail VSS (in this case 0V). M1 and M3 are wired as diodes and each
have a voltage drop of VSAT+VT across the drain-source junction.

M1 & M2 are effectively two diodes in series with a total voltage drop of 2VSAT+2VT, which is
fairly independent of current IREF. IREF can be set using a resistor or band-gap/resistor
network. As we have seen the voltage on the drain of M2 is:
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The diode voltage is always VSAT + VT

M1 gate voltage = 2VSAT + 2VT

Drain voltage on M2 = VG − VT sub in 2VSAT + 2VT for VG

= (2VSAT + 2VT ) − VT = 2VSAT + VT

It is possible to remove the VT (which is typically ~ 0.7 – 1V) by the use of the modified
cascode current sink shown in Figure 2.

VDD

IREF

2 * VSAT + VT
Vout = 2VSAT

VSAT R
IOUT

VSAT + VT
VT M1 M2 VSAT

VSAT + VT

VSAT M3 M4 VSAT
VSAT + VT

VSS

Figure 2 Modified cascode current sink to reduce the voltage drop across the two
output FET’s of M2 & M4.

To calculate the value of the resistor we decide on the minimum output voltage we require, for
example 0.6V, this will now set VSAT to 0.3V, on M2 & M4 and decide on the current required
say 100uA.

Now we can calculate VT+VSAT

2.Iref
VDS = + VT = VSAT + VT
β

2.Iref 2 2.Iref
VSAT = VSAT =
β β

K N .W 2.Iref W 2.Iref
β = = 2
∴ = 2
L VSAT L K N .VSAT

Using the following device data KN=110uA/V2, VT=0.7V, ID set to 100uA.

Set VSAT to be 0.3V

K N .W 2.Iref W 2.Iref
β = = 2
∴ = 2
L VSAT L K N .VSAT

W 2.100E -6
= = 20.2
L 110E -6 .0.3 2

Gate voltage calculations

VG3 = VSAT+VT = 0.3+0.7 = 1V and

VG4 = 2VSAT+VT = 2*0.3 +0.7 = 1.3V

So the resistor R = VSAT/Iref = 0.3/100E-6 = 3KΩ

The ADS simulation setup for analysing this example is shown in Figure 3 with the resulting
graph and tabulated data on Figure 4.
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-200 uA
5V 5V
DC V_DC 5V R
SRC2 100 uA R1
DC I_DC
Vdc=VDD R=500 Ohm
DC1 SRC4
SweepVar="VDD Idc=100 uA
Start=0
Stop=5 100 uA -100 uA
100 uA
Step=.01 MOSFET_NMO 4.95
4.95VV I_Probe
R MOSFET5 vd4 I1
R2 Model=MOSFETM
R=3000 Length=L um
100 uA Width=W um 100 uA

1.30 V
vgs4
LEVEL1_Mode -1.32 pA 0A 0A -5.29 pA
MOSFETM Var MOSFET_NMO
Eqn VAR
NMOS=yes -100 uA -100 uA MOSFET4
VAR1
Vto=0.7 Model=MOSFETM
302 mV L=1.0
Kp=110e-6 Length=L um
VDD=5
323 Width=W um
Lambda=0.04 100 uA W=20 100 mV
uA
vd1
MOSFET_NMO
MOSFET6 1V MOSFET_NMO
Model=MOSFETM vgs2 MOSFET2
Length=L um -312 fA 0A 0A -333 fA Model=MOSFETM
Width=W um Length=L um
-100 uA -100 uA Width=W um

Figure 3 ADS Simulation for the self-biased high swing cascode current source.
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I1.i, uA
120
m1
100

80

60
m1
VDD=0.630
40 I1.i=99.99uA
20

0
0 1 2 3 4 5

VDD
vd1[70] vd4[70] vgs2[70] vgs4[70]
0.300 0.650 1.000 1.300

Figure 4 Result of the ADS simulation of Figure 3. From the plot we can see that the
minimum output voltage (for current regulation) is ~ 0.6V. The table shows the 70 data
point (out of 500) where the output voltage is 0.65V the gate voltages agree with the
hand calculations given earlier.

Similarly we can design a current sink in the same way.

Using the following device data KP=50uA/V2, VT=0.7V, ID set to 100uA.

Set VSAT to be 0.3V

K N .W 2.Iref W 2.Iref
β = = 2
∴ = 2
L VSAT L K N .VSAT

W 2.100E -6
= = 44
L 50E -6 .0.3 2
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Gate voltage calculations

Vg1 = VSAT+VT = 0.3+0.7 = 1V and

Vg2 = 2VSAT+VT = 2*0.3 +0.7 = 1.3V

So the resistor R = VSAT/Iref = 0.3/100E-6 = 3KΩ

Vcc MOSFET_PMOS
V_DC MOSFET7
DC SRC2 Model=MOSFETM2
Vcc vg1 Vcc
DC Vdc=VDD Length=L um
DC1 MOSFET_PMOS Width=W um
SweepVar="VDD" von
MOSFET8
Start=0 Model=MOSFETM2
Stop=5 Length=L um
Step=.01 Width=W um

MOSFET_PMOS
MOSFET9
Model=MOSFETM2
Vcc vg2 Vcc
Length=L um
MOSFET_PMOS Width=W um
LEVEL1_Model MOSFET10
MOSFETM2 Model=MOSFETM2
PMOS=yes Length=L um
Vto=-0.7 Width=W um
Kp=50e-6 R I_Probe
Gamma=0.57 R2 I2
Phi=0.8 R=3000 Ohm
Lambda=0.05 Var
VAR
Eqn
Cgso=220e-12 VAR1
R
Cgdo=220e-12 L=1.0
R1
Cgbo=700E-12 I_DC VDD=5
R=500 Ohm
Cj=560e-12 SRC4 W=44
Mj=0.5 Idc=100 uA
Cjsw=350e-12
Mjsw=0.35
Tox=24.7e-4

Figure 5 Self biased cascode high swing current sink circuit using P-MOS devices.
Note that as this circuit is using P-type MOSFETS, VTO is set to –0.7V in the spice
model parameter list MOSFETM2.
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I2.i, uA

120

100

80

60

40

20

0
0 1 2 3 4 5

VDD
Eqn g1=Vcc[500]-vg1[500] Eqn vsat=Vcc[500]-von[500]
Eqn g2=Vcc[500]-vg2[500]

g1 g2 vsat
1.007 1.307 0.257

Figure 6 Resulting plot and node voltages of the current sink shown in Figure 5. For
this example the gate voltages are subtracted from VDD to make them referenced to
VDD. The [500] signifies the 500 data point which will be the parameter sweep of VDD
at 5V.