CHAPTER MODELING EXAMPLES n Chapter 2, we looked at the synthesis of Verilog HDL statements I into gates. In this chapter we look at an orthogonal view, that is the task of modeling hardware elements for synthesis and how Verilog HDL can be used to achieve this. As before, we show both the Verilog HDL model and the schematic for the synthesized output. This chapter also provides a number of more complicated Verilog HDL synthesis examples. These models illustrate the usage of Verilog HDL constructs collectively to model a design that can be synthesized. Sequential logic and combinational logic can be synthesized from a Verilog HDL description. There are two main styles for describing combi- national logic: i, Using continuous assignment statements: This is the most natural style, since it explicitly shows the parallelism in the hardware. It also implicitly shows the structure. 107CHAPTER 3 Modeling Examples ii, Using procedural assignment statements in a sequential block of an always statement: The statements describe the composi- tion of intermediate values within a combinational logic block; this is because the language semantics specify that all statements in a sequential block execute sequentially. Sequential logic elements, that is, flip-flops and latches, can be in- ferred by writing statements within an always statement using styles de- scribed in Chapter 2. It is best not to synthesize a memory as a two- dimensional array of flip-flops because this is an inefficient way to imple- ment a memory. The best way to create a memory is to instantiate a pre- defined memory block using a module instantiation statement. 3.1 Modeling Combinational Logic One good approach for describing combinational logic is to use con- tinuous assignment statements. An always statement can also be used to describe combinational logic; however, the synthesized logic may not be apparent from the description. If combinational logic is described using continuous assignment statements, then the synthesized logic is implicit in the description. Consider the following model of a built-in self-test cell. module BistCell (BO, B1, DO, Dl, 2); input 80, Bl, DO, D1; output 2; wire S1, S2, S3, S4; assign S1 =~ (BO & Di); assign $2 = ~ (D0 & Bl); assign $3 = ~ (S2 | S1); $2 & $1; assign Z = ~ (S4 | $3); endmodule // Synthesized netlist is shown in Figure 3-1. Notice the structure of the synthesized circuit is very similar to that of the continuous assignment statements. Here is the same model, but this time the cell is described using an al- ways statement. 108Modeling Combinational Logic SECTION 3.1 faa 7 > ss 8 = — ie ~ ‘oe ane N02 ore se f >a nae } a, 7 Figure 3-1 Combinational logic from continuous assignments. module BistCellReg (B0, Bl, DO, Dl, Z); input BO, B1, DO, D1; output Z; reg Z; reg S1, S2, $3; always @(B0 or D0 or B1 or D1) begin Sl =~ (BO & D1); S2 =~ (D0 & Bl); $3 =~ (s2| $1); $1 = S2& Sl; Z=~ (S1 | $3); end endmodule In module BistCell, each wire declared corresponded to a unique wire in the synthesized netlist, Not so with reg variable S/ in module BistCellReg. Notice that the variable S/ is used as a temporary in more than one place and does not represent one wire. The synthesized circuit still remains the same as that shown in Figure 3-1; however, the one-to-one mapping be- tween the variables in the always statement and the nets in the synthesized netlist is not present. Here is an example of a combinational logic model of a 2-to-1 multi- plexer with an enable. module Mux2Tol (A, B, Select, Enable, ZeeQ); input [1:0] A, B; input Select, Enable; 109CHAPTER 3 Modeling Examples output [1:0] Zeeg; assign ZeeQ = (Enable) ? (Select ? A: B) : ‘bz; endmodule // Synthesized netlist is shown in Figure 3-2. Enob > TNR far fl aa B AH Zee ? po fe. ret [7 Tous AL Felect b> ia td Zee0 80 INRBH > o fy eel INRGH TeUS pe ee Ao1ze Figure 3-2 A 2-to-1 multiplexer. 3.2 Modeling Sequential Logic ‘The following sequential logic elements can be modeled. i. flip-flop: see section 2.17. ii, flip-flop with asynchronous preset and or clear: see section 217. -flop with synchronous preset and or clear: see section 2.17. iv. latch: see section 2.15. y. latch with asynchronous preset and or clear: see section 2.15. = 110Modeling a Memory SECTION 3.3 3.3. Modeling a Memory A memory is best modeled as a component. Typically, synthesis tools are not efficient at designing a memory. More traditional techniques are generally used to build a memory. Once having built this module, it can then be instantiated in a synthesis model as a component using the module instantiation statement. module ROM (Clock, OutEnable, Address, Q, Qbar); input Clock, OutEnable; input (+-1:0] Address; output [11:0] Q, Qbar; // Memory description here (might not be // synthesizable) . endmodule module MyModule (.. .); wire Clk, Enable; wire (1%1:0] Abus; wire [IH1:0] Dbus; ROM R1 (.Clock(Clk), .QutEnable(Enable), -Address(Abus), .Q(Dbus), .Qbar()); endmodule A register file can be modeled as a two-dimensional reg variable (a two-dimensional reg variable is referred to as memory in Verilog HDL), which can then be synthesized. Here is an example of a register file. module RegFilewWithMemory (Clk, ReadWrite, Index, DataIn, DataOut) ; parameter N= 2, M= 2; input Clk, ReadWrite; input [1:N] Index; // Range need not be that large. input [0:41] DataIn; output [0:41] Datadut; reg [0:1] DataOut; ulCHAPTERS — Modeling Examples reg [0:41] RegFile [0:M1]; always @ (negedge Clk) if (ReadWrite) DataOut Pp Nextstate 8 Machine [State a logic F—- state (sequential) (combinational) (combinational) Figure 3-5 A Moore finite state machine. reg Z; parameter S0= 0, S1=1, S2= 2, S3= xeg [0:1] MooreState; always @ (posedge Clk) case (MooreState) SO: begin BB: 'bx; assign CompZ = (OpCode endmodule // Synthesized netlist is shown in Figure 3-13. 127CHAPTER 3 Modeling Examples Figure 3-13 A 2-bit custom ALU, 3.8 Modeling a Counter 3.8.1 Binary Counter Here is a model for a parameterized N-bit binary up-down counter with synchronous preset and preclear controls. The counting is synchro- nized to the rising edge of a clock. module BinaryCounter (Ck, UpDown, PresetClear, LoadData, DataIn, Q, ON); parameter NBITS = 2; input Ck, UpDown, PresetClear, LoadData; Anput [NBITS-1:0] DatalIn; output [NBITS-1:0] Q; output [NBITS-1:0) QN; reg [NBITS-1:0} Counter; 128Modeling a Counter — SECTION 3.8. always @ (posedge Ck) if (PresetClear) Counter B) ResultBus = 6'b010110; assign (£0, GT, LT, NE, GE, LE) = ResultBus; endmodule // Synthesized netlist for a 2-bit comparator is shown // in Figure 3-19. Figure 3-19 A 2-bit comparator. 135,CHAPTER 3 — Modeling Examples 3.11 Modeling a Decoder 3.11.1 A Simple Decoder Here is an example of a simple 2-by-4 decoder circuit. This is a com- binational circuit modeled purely using continuous assignment state- ments. Delays specified with the assignment statements, if any, are typically ignored by a synthesis system. module SimpleDecoder (A, B, Enable, DecodeOut); input A, B, Enable; output [0:3] Decodeout; wire Abar, Bbar; sign Abar = ~ A; assign Bbar = ~ B; assign DecodeOut (0) sign Decodeout [1] assign Decodeout [2] assign DecodeOut [3] = endmodule // Synthesized netlist is shown in Figure 3-20. (Enable & Abar & Bhar); (Enable & Abar & B); (Enable & A & Boar) ; (Enable & A & B); t —— 02 8 Boe f } Decnéout2 veo | ) +} Dees ‘ws 103 Dacodaut3 Figure 3-20 A simple 2-by-4 decoder. 3.11.2 Binary Decoder Here is a model of a parameterized N-bit binary decoder. 136Modeling a Decoder SECTION 3.11 module BinaryDecoder (SelectAddress, DecodeOut) ; parameter SBITS = 2; parameter OUT_BITS = 4; // Should be 2 to power of SBITS input [SBITS-1:0] SelectAddress; output [OUT_BITS-1:0] Decodeout; reg [OUT_BITS-1:0] DecodeOut; integer k; always @ (SelectAddress) for (k = OUT_BITS - 1; k >= Decodeout [kl] = (k endmodule // Synthesized netlist of a 2-bit binary decoder is shown // in Figure 3-21. k=k-1) SelectAddress) ? 'bl : 'b0; aot Sacer De 8 ‘we 4 Dera Saetiane Pe “J we Figure 3-21 A 2-bit binary decoder. 3.11.3 Johnson Decoder Here is a model of a parameterized N-bit Johnson decoder with an en- able control. module JohnsonDecoder (S, En, Y); parameter N= 3; input [0:1] $7 input En; output [0:2*N1] ¥; reg (0:2*N1] ¥; reg (0:2*N-1] Address; integer J; 137CHAPTER 3 — Modeling Examples always @ (S or En) if (En == 'bl) begin Address = 0; for (J= 0; J 1) && (! Done)) begin NextResult = Result * InLatch; InLatch 256) begin NextResult = NextResult >> 1; Exponent = 17) && (TotPts Won = 22) && (TotPts 100) UMA = SMA + BMA; e: UMA = SMA ~ CMA; If no resource allocation is performed, the "+" and "—" operators get syn- thesized into two separate ALUs. However, if resource allocation is per- 158Resource Allocation SECTION 4.1 formed, only one ALU is necessary that performs both the "+" and "—" operations. This is because the two operators are used under mutually- exclusive conditions. A multiplexer is also generated; it is needed at the second input port of the ALU to direct inputs BMA and CMA. Figure 4-2 shows the hardware synthesized for the i £ statement when no resource al- location is performed. Figure 4-3 shows the same example when resource allocation is performed. SMA BMA CMA MAX 100 ALU(4), LU (-) Suux/ IMA Figure 4-2 Without resource allocation. MAX 100 BMA CMA vy oY \vx/ JMA Figure 4-3. With resource allocation. Notice that with sharing an ALU, a multiplexer has been introduced at one of the inputs of the ALU that contributes to the path delay, However, 159CHAPTER 4 160 Model Optimizations the amount of logic generated has been reduced due to sharing of the ALU. This is again a trade-off that a designer may have to make, if such a capability is not provided by the synthesis tool. In timing-critical designs, it may be better if no resource sharing is performed. There are other variations of sharing that a synthesis tool may auto- matically enforce. Operators that are usually shared are: i, relational operators ii, addition iii. subtraction iv. multiplication vy. division Usually it is not worthwhile to generate an ALU that does an addition and a multiplication. Multiplication and division operators are typically shared amongst themselves. When sharing with other operators, the fol- lowing possibilities exist: i, Same operator, same operands: definitely must share. Exam- ple: A+B,A+B ii, Same operator, one different operand: trade-off, since one multiplexer will be introduced. Example: A + B, A +C iii, Same operator, different operands: trade-off since two multi- plexers are introduced. Example: A + B, C+ D iv. Different operators, same operands: useful to share. Example: A+B,A-B v. Different operators, one different operand: trade-off since one multiplexer introduced. Example: A + B, A - C Different operators, different operands: trade-off since two multiplexers introduced. Example: A + B, C - D vi, Possibility (i) is the best case to share followed by (iv), (ii, v) and (iii, vi). Resource allocation may also be performed manually by rewriting the model. Here is such an example. df (! ShReg) DataOut = AddrLoad + ChipSelectN; else if (Readwrite) DataOut = ReadN + WriteN;Common Subexpressions SECTION 4.2 else DataOut = AddrLoad + ReadN; // After manual resource allocation: if (1 ShReg) begin Temp1 = AddrLoad; Temp2 = ChipSelectN; end else if (ReadWrite) begin Temp1 Temp2 end else begin Temp1 = AddrLoad; Temp2 = ReadN; end ReadN; WriteN; DataOut = Templ + Temp2; The modified model guarantees only one adder and the multiplexers at the input ports of the adder are implied by the if statement. The original ex- ample may synthesize with three adders. 4.2 Common Subexpressions Itis often useful in practice to identify common subexpressions and to reuse computed values where possible. Here is a simple example. Run = Rl + R2; ge // Assume that the second assignment is executed every // time the first statement is executed. Note that this // assumption may not be true if either of the statements // is inside an if statement or a case statement. 161CHAPTER 4 — Model Optimizations If a synthesis tool does not identify common subexpressions, two adders would be generated, each computing the same result, that of R/ + R2. A logic optimization tool may or may not be able to identify such common logic, thus leading to larger designs. Therefore it is useful to identify com- mon subexpressions and to reuse the computed values. For the previous example, we could replace the second assignment by: Car = R3 - Run; The problem of identifying common subexpressions becomes more im- portant if larger blocks such as multipliers are used. 43 Moving Code It may so happen that within a for-loop statement, there is an expres- sion whose value does not change through every iteration of the loop. Also typically a synthesis tool handles a for-loop by unrolling the loop the specified number of times. In such a case, redundant code is introduced for the expression whose value is invariant of the loop index. Again a log- ic optimizer may or may not be smart enough to optimize such logic. Per- forming the optimizations at a higher level, that is, within the model, would help the optimizer in working on more critical pieces of the code. Here is an example of such a for-loop. car for (Count = 1; Count 4) Oly = Sdy & Ray; Clearly, there is no need to synthesize an and gate since the assignment statement will never get executed and represents dead code. Constant folding implies the computation of constant expressions dur- ing compile time as opposed to implementing logic and then allowing a logic optimizer to eliminate the logic. Here is a simple example. parameter FAC = Yak = 2 * FAC; 165CHAPTER 4 — Model Optimizations Constant folding computes the value of the right-hand-side expression during compile time and assigns the value to Yak. No hardware need be generated. This leads to savings in logic optimization time. 4.7 Flip-flop and Latch Optimizations 4.7.1 Avoiding Flip-flops It is important to understand the flip-flop inference rules of a synthesis tool. These rules may vary from one synthesis tool to another. If the infer- ence rules are not followed, a synthesized netlist may have many more flip-flops than are really necessary. Here is a case in point. reg PresentState; reg [0:3] Zout; wire ClockA; always @ (posedge Clock) case (PresentState) 0 begin PresentState Match? Netlist Figure 6-3 Using a common test bench. Synthesis module TestBenchFA; parameter WORDS = 5; reg [1:3] MemV [1:WORDS]; reg A, B, Cin; wire SumBeh, CoutBeh, SumStr, CoutStr; integer J; // Instantiate the design module under test: FA_RTL Fl (A, B, Cin, SumBeh, CoutBeh) ; // Instantiate the synthesized netlist module: FA_Netlist F2 (A, B, Cin, SumStr, CoutStr); 175CHAPTER5 Verification initial begin // Read the file with input vectors: $xeadmemb ("Inputs.vec", MemV); // Bpply each vector to both design module and // synthesized netlist module: for (J = 1; J coe FOISICX Cuz, NR, fp Pog fulenBust a LoadDatet je Figure 5-5 Variable asynchronous preset. 185CHAPTER 5 Verification Two flip-flops with asynchronous preset and clear are synthesized for the variable QuickBus. The variable LoadData is connected to the preset clear inputs of the flip-flops through other logic. When PreLoad is active (is 0) and LoadData changes, the outputs of the flip-flops are immediately af- fected because of the asynchronous data change. However in the design model, any change on LoadData has no effect on the output QuickBus. Thus there is a mismatch. Recommendation: Avoid asynchronously reading a variable and as- signing it to a flip-flop; else ensure that there are no changes on asynchro- nous data when the asynchronous conditions are active. 5.9 Blocking and Non-blocking Assignments In Chapter 2, we recommended that: * blocking assignments be used for modeling combinational logic, and * non-blocking assignments be used for modeling sequential logic; blocking assignments may be used for variables that are assigned and used, all within an always statement. In this section, we explain why this recommendation is important to be followed; else there is a risk of getting functional mismatches. 5.9.1 Combinational Logic Blocking assignments mirror the dataflow in a combinational circuit. Consider the following always statement. reg TM, TN, TO, TZ; always @ (A or Bor Cor Dor £) begin T™ = A&B; IN = C&D; TO= TM | TN| E; TZ =! 70; end 186Blocking and Non-blocking Assignments SECTION 5.9 All the assignments are blocking assignments. Statements within the se- quential block imply to compute the value of 7M first, then execute the second statement, assign to TN, then go to third statement, assign to TO, and so on. This mimics the dataflow through the combinational logic. Let us now change all these to non-blocking assignments. reg TM, TN, TO, TZ; always @ (A or Bor Cor Dor £) begin TM R&B; endmodule module AOI21 (Al, A2, B, Z); input Al, A2, B; output Z; //%=1 ((AL&A2) |B); endmodule 199APPENDIX B A Generic Library 200 module AOI211 (Al, A2, Bl, B2, 2); input Al, A2, Bl, B2; output Z; //@=% ((Al &A2) | B1 | B2); endmodule module AOI22 (Al, A2, Bl, B2, Z); input Al, A2, Bl, B2; output Z; //%=4% ((Al &A2) | (Bl & B2)); endmodule module BN20T20D (A, ST, STN, PADI, Z, PADO); input A, ST, STN, PADI; output Z, PADO; // Bidirectional buffer. // % = PADI; // PADO = 0 when (!A && !STN) else Ws 1 when (A && ST) els Ws "bz; endmodule module BUF (A, 2); input a; output Z; J/2= 2; endmodule module FD1P3AX (D, SP, CK, Q, QN); input D, SP, CK; output 0, ON; // Positive edge-triggered, positive-level sample, // static D-type FF. endmodule module FDISIA (D, CK, Q, QN); input D, CK; output 0, ON; // Positive-level sense static D-type FF (latch) . endmoduleAGeneric Library APPENDIX B module FD1S1B (D, CK, PD, Q, QN); input D, CK, PD; output Q, ON; // Positive-level sense, positive asynchronous // preset, static D-type FF (latch). endmodule module FD1S1D (D, CK, CD, Q, QN); input D, CK, CD; output Q, ON; // Positive-level sense, positive asynchronous // clear, static D-type FF (latch). endmodule module FDISIE (D, CK, CDN, Q, ON); input D, CK, CDN; output Q, ON; // Positive-level sense, negative asynchronous clear, // static D-type FF (latch). endmodule module FDISIF (D, CK, PD, CDN, Q, ON); input D, CK, PD, CDN; output Q, ON; // Positive-level sense, negative asynchronous clear, // positive asynchronous preset, static // D-type FF (latch). endmodule module FD1S2AX (D, CK, Q, QN); input D, CK; output 0, ON; // Negative edge-triggered, static D-type FF. endmodule module FDIS2BX (D, CK, PD, Q, ON); input D, CK, PD; output 0, ON; // Negative edge-triggered, positive asynchronous // preset, static D-type FF. endmodule 201APPENDIXB A Generic Library module FDIS2CX (D, CK, PD, Q, ON); input D, CK, PD; output 9, ON; // Negative edge-triggered, positive asynchronous // preset, positive asynchronous clear, // static D-type FF. endmodule module FD1S2DX (D, CK, CD, Q, QN); input D, CK, CD; output Q, ON; // Negative edge-triggered, positive asynchronous // clear, static D-type FF. endmodule module FD1S2EX (D, CK, CDN, Q, ON): Amput D, CK, CDN; output Q, ON; // Negative edge-triggered, negative asynchronous // clear, static D-type FF. endmodule module FD1S2FX (D, CK, PD, CDN, Q, ON): input D, CK, PD, CDN; output Q, ON; // Negative edge-triggered, negative asynchronous // clear, positive asynchronous preset, static // D-type FF. endmodule module FD1S2GX (D, CK, PD, CDN, Q, QN); input D, CK, PD, CDN; output 0, ON; // Negative edge-triggered, negative asynchronous // preset, static D-type FF. endmodule module FD1S2IX (D, CK, CD, Q, ON); input D, CK, CD; output Q, ON; // Negative edge-triggered, positive synchronous 202A Generic Library APPENDIX B // clear, static D-type FF. endmodule module FD1S2UX (D, CK, PD, Q, ON); input D, CK, PD; output 0, ON; // Negative edge-triggered, positive synchronous // preset, static D-type FF. endmodule module FDIS2NX (D, CK, PDN, CD, Q, ON); input D, CK, PDN, CD; output 0, ON; // Negative edge-triggered, positive asynchronous // clear, negative asynchronous preset, static // D-type FF. endmodule module FD1S20X (D, CK, PD, CD, Q, ON); input D, CK, PD, CD; output 0, ON; // Negative edge-triggered, positive synchronous // clear, positive synchronous preset, static // D-type FF. endmodule module FD1S3AX (D, CK, Q, ON); input D, CK; output 0, ON; // Positive edge-triggered, static D-type FF. endmodule module FD1S3BX (D, CK, Q, QN); input D, CK; output Q, ON; // Positive edge-triggered, positive asynchronous // preset, static D-type FF. endmodule module FD1S3CX (D, CK, Q, ON); input D, CK; output 0, ON; 208APPENDIXB A Generic Library // Positive edge-triggered, positive asynchronous // clear, positive asynchronous preset, static // D-type FF. endmodule module FD1S3EX (D, CK, CDN, Q, QN); input D, CK, CDN; output Q, ON; // Positive edge-triggered, negative synchronous // clear, static D-type FF. endmodule module FLIS2AX (D0, D1, CK, SD, Q, QN); input D0, D1, CK, SD; output Q, ON; // Negative edge-triggered, data select front end, // scan FF. endmodule module FLIS2EX (DO, D1, CK, SD, CDN, Q, ON); input DO, D1, CK, SD, CDN; output 0, ON; // Negative edge-triggered, data select front end, // negative asynchronous clear, scan FF. endmodule module FLIS3AX (D0, D1, CK, SD, Q, QM); input DO, D1, CK, SD; output Q, ON; // Positive edge-triggered, data select front end, // scan FF. endmodule module FLIS3CX (DO, D1, CK, SD, Q, QN); input DO, D1, CK, SD; output 0, ON; // Positive edge-triggered, data select front end, // positive asynchronous clear, positive asynchronous // preset, scan FF, endmoduleA Generic Library APPENDIX B module FL1S3EX (D0, D1, CK, SD, CDN, Q, QN); input DO, D1, CK, SD, CDN; output 0, QN; // Positive edge-triggered, data select front end, // negative asynchronous clear, scan FF. endmodule module FS0SID (S, R, CD, Q, QN); input S, R, CD; output 0, ON; // Positive-level S input, positive-level R input, // positive asynchronous clear, R-S FF (latch). endmodule module INRB (A, Z); input A; output 2; W122; endmodule module INRBH (A, Z); input A; output Z; //2= 0A; (same as INRB) endmodule module ND2 (A, B, Z); input a, B; output Z; J) B= 1 (K&B); endmodule module ND3 (A, B, C, Z); input A, B, C; output Z; /1Z=1 (ARBEC); endmodule module ND4 (A, B, C, D, 2); input A, B, C, D; output Z; 205APPENDIX B A Generic Library 206 J/%=4 (ARBRCED); endmodule module NR2 (A, B, Z); input A, B; output Z; 11221 (A] B); endmodule module NR3 (A, B,C, Z); input a, B, C; output Z; 1B (AL BIC); endmodule module NR4 (A, B, C, D, Z); input A, B, C, D; output Z; //Z=t(A| BIC |D); endnodule module OAI21 (Al, A2, B, 2); input Al, a2, B; output Z; //2=% ((Al | A2) &B); endmodule module OAI22 (Al, A2, Bl, B2, Z); input Al, A2, Bl, B2; output Z; //@= 1 ((Al| A2) & (B1 | B2)); endmodule module 0AI4321 (Al, A2, A3, A4, Bl, B2, B3, Cl, C2, D, 2); input Al, A2, A3, A4, Bl, B2, B3, Cl, C2, D; output Z; //%=1 ((Al | a2 | a3 | Ad) & (B1 | B2 | B3) Ws & (Cl C2) &D); endmoduleAGeneric Library APPENDIX B module OR2 (A, B, Z); input A, B; output Z; //B=R|B; endmodule module OR4 (A, B, C, D, Z); input A, B, C, output Z; %=a[B[C|D: endmodule module TBUS (D, CK, CKN, Q); dnput D, CK, CKN; output 0; //Q= ‘bz when (! CK && CKN), wy ‘bO when (CK && ! D), My ‘bl when (! CKN && D); endmodule module XNOR2 (A, B, 2); — output 7/%= | (AB); endmodule module XOR2 (A, B, Z); input a, B; output Z; //Z=RAB; endmodule module XOR2Z (A, B, Z, Z1); input A, B; output Z, 21; //G=A*B; 21 = 1 (A|B); endmoduleBIBLIOGRAPHY N N . Bhasker J., A Verilog HDL Primer, Star Galaxy Press, Allentown, PA, 1997, ISBN 0-9656277-4-8. . IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Std 1364-1995, IEEE, 1995. . Lee James, Verilog Quickstart, Kiuwer Academic, MA 1997, ISBN 0- 7923992-7-7. . Palnitkar S., Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall, NJ, 1996, ISBN 0-13-451675-3. . Sagdeo Vivek, The Complete Verilog Book, Kluwer Academic, MA, 1998, ISBN 0-7923818-8-2. . Smith Douglas, HDL Chip Design, Doone Publications, AL, 1996, ISBN 0-9651934-3-8, ”. Sternheim E., R. Singh and Y. Trivedi, Digital Design with Verilog HDL, Automata Publishing Company, CA, 1990, ISBN 0-9627488-0- 3: . Thomas D. and P. Moorby, The Verilog Hardware Description Lan- guage, Kluwer Academic, MA, 1991, ISBN 0-7923912-6-8. Qa 209INDEX $display 3 2s complement 9, 22 A adder 17, 133, 165 addition 160 algorithmic level 1 ALU 124, 158 always statement 12, 17, 37, 41,51, 68, 89, 95, 101, 108, 114, 145, 166, 168, 180, 182, 186, 188, and primitive 97 architecture level xvi ArchSyn synthesis system xvi, 191 area constraints 2 area-delay trade-off 158 arithmetic operator 22, 158 arithmetic-logic-unit xvi, 1, 124, 158 assignment statement 136, 176 associativity 164 associativity rule 164 asynchronous clear 64, 78, 79, 80 asynchronous condition 185 asynchronous logic 78 asynchronous preclear 131 asynchronous preset 64, 78, 79, 80 asynchronous preset clear flip- flop 185 B base format form 9 behavioral description 99 behavioral model 177 binary code 113 binary comparator 134 binary counter 128, 132 binary decoder 136 bit-select 33, 139 black box 98 blackjack 153 blocking assignment 73, 186, 188 blocking procedural assignment 17, 84 boolean equation 113 buf primitive 97 bufif0 primitive 97 bufifl primitive 97 built-in primitive xvi built-in self-test cell 108 c carry 24 carry bit 24 carry input 133 carry output 133 case equality 27 case expression 45,52 case inequality 27 case item 45, 52, 56, 58, 94, 120 211INDEX case item expression 48 case statement 45,51, 59, 93, 94, 114, 119, 122, 161, 180 casex statement 6,49, 55 casez statement 6, 48, 55 circuit performance 157 clock edge 70, 77, 80, 89, 91, 114, 145 clock event 68, 78, 95, 114, 183 clocked always statement 68, 81, 89, 114 clocked behavior xvi combinational circuit 136 combinational logic xvi, 18, 39, 88, 89, 107, 108, 113, 117, 139, 186, 188 comment 53 common factoring 163 common subexpression 161, 163, 164, 170 common subexpression identification 164 commutative operation 164 commutativity 164 commutativity rule 164 comparator xvi, 134 concatenation 24 concatenation operator 33 concurrent behavior xv conditional branch 61 conditional expression 36, 94, 126 conditional statement 12, 60, 64, 180 constant 9 constant folding 165 constant index 33 constant shift 28 continuous assignment 16, 21,25, 31 continuous assignment statement 16, 107, 108, 113, 126, 136, 139 counter xviii critical path 170 custom-made flip-flop 101 D data flow analysis 9, 179 data type 2 dataflow 186 datapath operator 169 dead-code elimination 165 decoder xviii, 35, 56, 136 decoding logic 56 default branch 54, 119 212 delay 20, 136, 176, 181 delay control 20 design size 168 designer xix wider block 153 division 160 don't-care 6,48, 49 don’t-care value, D 6 D-type flip-flop 78 E edge event 78 edge-triggered storage element 10 efficient code 163 enable control 137 encoding states 121 equality operator 27 even parity 141 event list 12, 38, 42, 78, 182, 187, 188 exponent 146 expression 88, 162, 170 extraction 163 F factorial 146 falling edge 68,70, 144 falling-edge-triggered flip-flop 69, 70,71, 73, 80 flip-flop 1,3, 10, 12, 19, 68, 70, 78, 79, 81, 89, 95, 101, 108, 145, 166 forever-loop 66 for-loop 66 for-loop statement 88, 90, 162 full case 52, 119 full_case directive 53 full_case synthesis directive 58, 120, 122, 183 full-adder 21,98 function 88 function call 88 functional mismatch 20, 39, 58, 68, 87, 93, 179, 185, 186 functional mismatches 55 functionality 174 G gate instantiation 97 gate level 1 gate level modeling 97 gate level netlist xv gate level primitive 97 Gray code 113Gray counter 132 Gray to binary 114 H hardware element xviii hierarchy 89, 169 high-impedance 93 high-impedance value, Z 6 high-level synthesis xvi I IBEE Std 1364-1995 xv if statement 40, 43, 45, 50, 52, 59, 67, 78, 161, 179, 180 ignored construct 191 inference rule 70, 166 inferring latch 179 initial statement 17 in-line expansion 88, 90, 92 integer 9, 72 integer register 73 integer type 9, 22,27 intermediate variable 73 intra-statement delay 20 invariant 162 inverter 16 J Johnson counter 130,131 Johnson decoder 137 L latch 3, 10, 12, 19, 42, 43, 51, 58, 59, 108, 167 latch inferencing 42 left shift operator 28 level-sensitive storage element 10 local variable 88 locally declared variables 73 logic circuit 168 logie gate xvi logic optimization 168 logic optimization tool 162 logic optimizer 2, 157, 162, 164, 168, 178 logic structure 170 logic synthesis xvi logic-0 6,8, 93 INDEX logic-1 6,8, 93 logical operator 21 loop index 162 loop iteration 163 loop statement 66 loop-invariant expression 163 M machine code 157 machine state 114 mantissa 146 Mealy finite state machine 117 memory 10, 13, 108, 111, 167 mismatch violation 176 modeling flip-flop 68 module binding xvi module builder 2 module declaration 98 module instance 98, 101, 173, 177 module instantiation statement 98, 108, 111 modulo-N counter 129 Moore finite state machine 114 multi-phase clocks 77 le clocks 75 multiple driver resolution 7 multiple drivers 7 multiplexer xviii, 1, 34, 109, 139, 140, 159 multiplication 160 multiplication logic 99 multiplication operator 169 multiplier 99, 169 multiply operator 100 mutually exclusive 56 mutually-exclusive branch 163 mutually-exclusive condition 158 N named constant 10 nand primitive 97 negative edge 77 negedge 68, 78 net 16 net data type 6,10, 11 net declaration 7 net type 22 netlist xvi, 173, 17 next state logic 117 non-blocking assignment 73, 86, 186, 188, 189 non-blocking procedural 213INDEX assignment 18, 68, 84, 189 non-constant bit-select 35 non-constant expression 58 non-constant index 34 non-encoded select lines 140 non-logical value 93 nor primitive 97 not primitive 97 not supported construct 191 notif0 primitive 97 notif1 primitive 97 ° odd parity 141 one-hot state encoding 120 optimization 157 or primitive 97 output logic 117 output parameter 89 output response 175 P parallel case 55 parallel data 147 parallel_case synthesis directive 56, 183 parameter 10, 103, 122, 126, 140 parameter declaration 122 parameterized adder 133 parameterized ALU 124 parameterized binary decoder 136 parameterized comparator 134 parameterized decoder 136 parameterized design 103 parameterized Gray counter 132 parameterized Johnson counter 131 parameterized Johnson decoder 137 parameterized module 103 parameterized multiplexer 140 parameterized parity generator 141 parameterized register file 104 parentheses 170 parity generator 141 part-select 32 path delay 159 posedge 68, 78 positive edge 77 predefined block 99 predefined flip-flop 101 predefined multiplier 100 primitive component 98 priority encoder 49, 58 214 priority logic 55 priority order 55 procedural assignment 17,20, 37 procedural assignment statement 17, 108 procedural behavior 37 R RAM 169 real 9 real type 9 receiver block 150 redundant code 162 reg 9,11 reg declaration 9 reg register 73 reg type 22 register 103 register data type 6,8, 10, 11 register file 111 register type 8 register-transfer level xv, 1 relational operator 25, 158, 160 repeat-loop 66 reserved word xix resource allocation 158 results file 174 reuse 161 right shift operator 28 rising clock edge 114 rising edge 68, 128, 153 rising-edge-triggered flip-flop 70, 71, 166 ROM 169 RS-232 147 RTL 1 RTL block xvi, 2 RTL subset xvii run-time 158 s sequential behavior xv sequential block 11, 37, 84, 86, 108, 187 sequential logic xvi, 18, 39, 68, 89, 107, 117, 186, 188 sequential logic element 108 sequential state assignment 116 serial input 147 sharing 158 shift operator 28 shift register 123shifter 28 shift-type counter 130 signed arithmetic 23 signed arithmetic operator 22 signed number 9, 23, 27 simple decimal form 9 simulate 174 simulation 173, 189 simulation cycle 187 simulation efficiency 163 simulation language 3 simulation semantics xvi simulation time 86 simulation tool 183 simulator 188 state assignment 119 state encoding 122 state table 123 state transition 114 stimulus 174 stimulus application time 178 stimulus file 177 stimulus period 177 string 9 structure xv, 31 subtracter 162, 165 subtraction 160 subtraction operation 25 supply0 7 supply0 net 8 supply1 7 supply1 net 8 supported construct 191 switch level xvi synchronous clear 81, 83 synchronous logic 78 synchronous preclear 128, 129, 132 synchronous preset 81, 83, 128 synthesis 1 synthesis directive 53, 56, 183 synthesis full_case 54,119 synthesis methodology checker 5 synthesis modeling style 5 synthesis parallel_case 57 synthesis process xvi synthesis run-time 168 synthesis system xix synthesis tool xix, 183 synthesizable constructs 191 synthesized netlist. xviti, 173 INDEX T target netlist xvi, 2 target technology xvi, 2 task 89 task call 89,92 technology translation xvi test bench 175 three-state 95 three-state gate 93, 97, 143 time type 9 timing constraints 2 timing-critical design 160 trade-off 160 transmitter block 148 tri 7 tri net 8 two-dimensional reg variable 111 u UART 147 unconnected input port 178 unconnected port 178 universal shift register 123 unknown 93 unknown value, U 6 unrolling 66 unsigned arithmetic 22 unsigned arithmetic operator 22 unsigned number 9, 22 up-down counter 70, 79, 101, 128 user-built multiplier 99 user-defined primitive xvi user-specific flip-flop 101 v value x 93 value z 93. variable 6, 179 variable shift 28 vector 30 vector file 175 vector operand 30 vectors 177 verification 173 verification results 5 Verilog Hardware Description Language xv Verilog HDL xv Verilog simulator xvi 215w wand 7 while-loop 66 wire 2,7, 10, 11,19, 39, 88 wire net 8 wor 7 x xvalue 6,93 xnor primitive 97 xor primitive 97 Zz zvalue 6,93Order Form x Fax orders: (610) 391-7296 4 Telephone orders: Call toll free (888) 727-7296 On-line orders: [email protected] + Web site orders: http://users.aol.com/SGalaxyPub +r Postal orders: Star Galaxy Publishing, Suite 401, 1058 Treeline Drive, Allentown, PA 18103. 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