Verilog LABs

Gonzalo Fernandez

© 2016 Synopsys, Inc. 1

Full Design
Simple Processor

© 2016 Synopsys, Inc. 2

Design: Simple processor
• The objective is to create a basic multicycle processor as shown in the diagram below.

zero
d_in1 2
d_in2 error
Mux A
d_in3 w

alu
{dout_high, dout_low}
2w

Mux B

2w 4
reset
clk

cmdin
control
6

© 2016 Synopsys, Inc. 3

Design details
• Specifications of the design:
–This is a multicycle processor (3 stages) with no pipelining.
–It has 3 variable width input buses to be used as operands.
–The ALU has 2 multiplexed inputs:
– Each MUX is feed by the 3 input buses and the ALU output.
–Both reset (rst) and clock (clk) signals should be connected to every module that uses
them.
–It has a control unit feed by a 6 bit word (cmdin).

© 2016 Synopsys, Inc. 4

Lab 1
Basic modules

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Lab 1 – Basic modules

• This lab will consist on creating some basic designs (modules).

• A description of the design functionality will be provided.

• The objective is to translate the description into a synthesizable Verilog code.

• It is very important to use the module interface that will be provided.

• In order to do a syntax check on the Verilog code written, vlogan tool can be used. The
following line can be executed on the shell

vlogan <verilog_file.v> –full64 –sverilog +v2k

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Lab 1a – Parameterized 4-input MUX

• Write the Verilog code that implements a 4-input multiplexer (mux) with variable (parameterized)
input and output bus width.

• Use the following interface

1 module mux4 #(
2 parameter WIDTH= 8 din_1
3 ) ( din_2
dout
4 input [WIDTH-1:0] din_1, din_2, din_3, din_4, din_3
5 input [1:0] select, din_4
6 output [WIDTH-1:0] dout
7 );
select

© 2016 Synopsys, Inc. 7

Lab 1b – Parameterized Register Bank

• Write the Verilog code that implements a D-type Register Bank with parameterized depth. It
should:
– Operate on positive edge of the clock (clk)
– Have a Synchronous reset (rst)
– Have an enable signal (wr_en) which allows data capturing only when asserted.

• Use the following interface

1 module register_bank #(
2 parameter WIDTH = 8
3 ) (
4 input [0:0] clk, dout
din
5 input [0:0] rst, 8
8
6 input [0:0] wr_en,
7 input [WIDTH-1:0] din,
8 output [WIDTH-1:0] dout
9 ); clk

wr_en rst
© 2016 Synopsys, Inc. 8
Lab 1c – Basic ALU
• Write the Verilog code for a basic ALU module (Arithmetic Logic Unit).
– This ALU has to have addition, subtraction, multiplication and division operations.
– All 4 bits must be used to define the 4 possible opcode values for all 4 operations defined previously.
– It should have two variable (parameterized) width inputs and output bus in accordance.
– Signal zero[0] should be asserted when the result of the current operation is 0.
– Signal error[0] should be asserted when dividing by 0 is attempted or when input data is not valid.
– On error condition, output must be forced to be -1
– Operations should be described using Verilog arithmetic operators.

• Use the following interface

1 module ALU #(
2 parameter WIDTH = 8
3 ) (
4 input signed[WIDTH-1:0] in_a, in_b,
5 input [3:0] opcode,
6 input [0:0] nvalid_data,
7 output [2*WIDTH-1:0] out,
8 output [0:0] zero,
9 output [0:0] error
10 );
© 2016 Synopsys, Inc. 10
Lab 2
Simulation with VCS

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Lab 2 - Simulation

• This lab will be focused on simulating each module created in Lab 1 (a, b, c)
–Simulations will be done using VCS tool.

• For lab 1a (Multiplexer) there is a test bench available, so the task is to

simulate the module using that test bench.
vcs –full_debug –sverilog mux4_tb.v <verilog_file.v>

• For labs 1b and 1c:

–Write a test bench for each module.
–Simulate them in VCS.

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Lab 3
FSM Design, Implementation and simulation

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Lab 3 – FMS design for control module
• The control unit feed by a 6 bit word (cmdin). This control unit has to:
–Enable the register stages only when applicable
–Select the outputs of each MUX
–Provide the control signals for the ALU.
– Details on how to control the ALU are available in Lab 1c.
– Inverted valid data signal must be asserted when data is feed from the feedback loop and the
previous result was not valid (Error condition)
– OPCODE to select the operation performed by the ALU.
REG
Muxes BANKs ALU
Registers
Enabling OP Code
Valid data
Mux Selection
Error Status

CONTROL
Instruction
© 2016 Synopsys, Inc. 14
Clock - Reset
Lab 3 – FMS design for control module (cont.)
• The control block shall be designed to implement the following Instruction Set Architecture
(ISA):
cmdin
5 4 3 2 1 0

muxA muxB opcode

• The opcode bus should be decoded according to the following table:

opcode[1] opcode[0] Operation

0 0 Add
0 1 Sub
1 0 Mul
1 1 Div

© 2016 Synopsys, Inc. 15

Lab 3 – FMS design for control module (cont.)
• The control module
– Draw the FSM diagram.
– Write the Verilog code for implementing this module based on the details and ISA provided previously.
– Write a test bench to validate this module. It should cover all possible operations, corner cases and
exercise all outputs.
– Its interface should be as follows:
1 module control (
2 input wire [0:0] clk,
3 input wire [0:0] rst,
4 input wire [5:0] cmd_in,
5 input wire [0:0] p_error,
6 output reg [0:0] aluin_reg_en,
7 output reg [0:0] datain_reg_en,
8 output reg [0:0] aluout_reg_en,
9 output reg [0:0] nvalid_data,
10 output wire [1:0] in_select_a,
11 output wire [1:0] in_select_b,
12 output reg [4:0] opcode
13 );
© 2016 Synopsys, Inc. 16
Lab 4
Full design integration and simulation with VCS

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Lab 4 – Full design
• Full design
– Write the Verilog code that implements this simple microprocessor.
– At this point it is mostly about connecting together all the modules created so far.
– A test bench will be provided.
– Its interface should be as follows

1 module top #(
2 parameter WIDTH= 8
3 ) (
4 input wire [0:0] clk,
5 input wire [0:0] rst,
6 input wire [5:0] cmdin,
7 input wire [WIDTH-1:0] din_1,
8 input wire [WIDTH-1:0] din_2,
9 input wire [WIDTH-1:0] din_3,
10 output wire [WIDTH-1:0] dout_low,
10 output wire [WIDTH-1:0] dout_high,
10 output wire [0:0] zero,
10 output wire [0:0] error
11 );
© 2016 Synopsys, Inc. 18
Design: Simple processor

zero
d_in1 2
d_in2 error
Mux A
d_in3 w

alu
{dout_high, dout_low}
2w

Mux B

2w 4
reset
clk

cmdin
control
6

© 2016 Synopsys, Inc. 19

Thank You