Design for Low Power

Barry Pangrle, Ph.D.

Director, R&D
Power Management

October 21, 2004

Power Management Approaches

Architectural
Hardware vs. Software
Hardware / Software Allocation

System Level
Multi-threshold Algorithm/
Compilers
Multi-voltage Implementation
Power aware OS
Clock, data gating Tradeoffs
Hibernation modes
Low-power circuits
Memory Access
Retention latches
Power aware memories

Hardware & IP Software

Multi-threshold, Multi-voltage, SOI, High-K,
Body bias, Copper interconnect, SiGe substrates

Process
© 2004 Synopsys, Inc. (2) Interoperability Forum CONFIDENTIAL
Galaxy Power Management
Power Management Throughout the Design Flow

Power Compiler
Galaxy • Dynamic and leakage power optimization
Design
Design Compiler
Compiler within DC & PC
Compiler

•
Compiler
RTL power analysis
Compiler
Module

Power

DFT
PrimeTime SI, PrimePower

PrimePower
JupiterXT
JupiterXT
Milkyway • Gate-level peak and average power analysis
Physical
Physical Compiler
Compiler • Vector-Free Capability
Astro,
Astro, Astro-Rail
Astro-Rail

JupiterXT
Star-RCXT
Star-RCXT
• Design planning, power network analysis
Hercules
Hercules
Astro-Rail
• Voltage-drop and electromigration analysis

© 2004 Synopsys, Inc. (3) Interoperability Forum CONFIDENTIAL

Power Dissipation In CMOS Designs
Dynamic Power Pdyn = a f * C * V2
VDD
• Switching Power
ƒ Load Capacitance
Charge/Discharge
• Internal Power
ƒ Short Circuit between Power and Iint
Ground during transition
Isw
ƒ Internal Capacitance within a (Gate)
(Subthreshold)
Gate
Cload
Static Power Ileak
• Subthreshold Leakage
Isub = I0(e[-Vth/S] [1-e-qVds/kT]) (at Vgs = 0)
Gnd
• Gate Leakage

© 2004 Synopsys, Inc. (4) Interoperability Forum CONFIDENTIAL

90 nm Leakage vs Delay

1000

100
Ioff (nA/µm)

10

1 Ioffn
Ioffp
0.1

0.01

0.001
5 10 15 20 25 30
Gate Delay (ps)

© 2004 Synopsys, Inc. (5) Interoperability Forum CONFIDENTIAL

90nm Low Vth & High Vth Cells
100000

10000

1000

nW
100

10

2
2
8
4
0
6
2
8
4
0
6
2
8
4
0
6
2
8
4
0
6

8
4
0
6

8
0
16
32
48
64
80
96
11
12
14
16
17
19
20
22
24
25
27
28
30
32
33
35
36
38
40
41
43
44
46
48
49
51
52
© 2004 Synopsys, Inc. (6) Interoperability Forum CONFIDENTIAL
Multi-Vth Optimization Results
Case Study: 210K instances, 300MHz, initial leakage ~20uW

Pre-route Post-route
1-pass
Cell Swap
Physical Opt.
Leakage (µW) 10.8 11.1

High-Vth (%) 87.5% 89.7%

Meets timing – same slack as before Multi-Vth Opt

Checks DRC for better design QoR and closure

© 2004 Synopsys, Inc. (7) Interoperability Forum CONFIDENTIAL

Multi-Voltage Design Styles

Voltage Island Voltage Island

Monitor A Monitor B
Voltage Island Voltage Island

A B Mode Voltage
Regulators

Programmable
Control
Voltage Island Voltage Island
Voltage Voltage Island
Mode
A B Control Regulators Monitor C
1.2 V, 350 MHz 1.0 V, 250 MHz
Voltage Island

Voltage Island C Adaptive Voltage Scaling

C - Voltage areas with variable Vdd
1.5 V, 500 MHz Dynamic Voltage Scaling - Software controlled modes
- Voltage areas with fixed,
multiple voltages IEM Partnership
Multiple Supply - Software controlled modes
Multi-Voltage Islands
- Voltage areas with fixed, single
voltages

© 2004 Synopsys, Inc. (8) Interoperability Forum CONFIDENTIAL

Multi-VDD Design
• Isolation cells and level
shifters for routing
across voltage areas
VA ƒ Timing Constraints
VB ƒ Clock Frequency
ƒ Power
VE
• Automatic insertion,
optimization & power
VD
VC routing of special cells
ƒ Isolation cells
ƒ level shifters
ƒ retention registers

© 2004 Synopsys, Inc. (9) Interoperability Forum CONFIDENTIAL

Power Gating

• Shut down non-active blocks

ƒ Reduces leakage power
ƒ Savings can be > 99%
• State Options:
1) Throw away
2) Scan out to memory
3) Retain locally in “retention” registers
• States are restored or re-initialized when the
blocks are reactivated
• Requires isolation cells at the boundaries

© 2004 Synopsys, Inc. (10) Interoperability Forum CONFIDENTIAL

Leakage (Gated Ground or VDD)

VDD

cell
Virtual VDD
Virtual VSS
cell

VSS
“Header” “Footer”

© 2004 Synopsys, Inc. (11) Interoperability Forum CONFIDENTIAL

Leakage (Gated Ground or VDD)

cell

Enable

1 Transistor / Cluster Gate Transistor in Cell

© 2004 Synopsys, Inc. (12) Interoperability Forum CONFIDENTIAL

Example Retention Register

HVth
LVth
HVth
B2 B2_b

HVth
B1_b B1

D Q

LVth

© 2004 Synopsys, Inc. (13) Interoperability Forum CONFIDENTIAL

Retention Register Insertion in Synthesis

• Same functionality, different styles

ƒ Additional restrictions on cell swapping
• Styles on HDL blocks
ƒ Set power gating style on named always blocks in Verilog or
VHDL processes
• Control pins (save & restore)
ƒ Specially handled in synthesis
• Additional features supported
ƒ Scan Cells
ƒ Compile with gate level design
ƒ Incremental compile
ƒ Physopt

© 2004 Synopsys, Inc. (14) Interoperability Forum CONFIDENTIAL

Power Compiler RTL Clock Gating
Synchronous-load-enable Implementation
always
always @ @ (posedge
(posedge CLK)
CLK)
ifif (EN)
(EN)
D_OUT
D_OUT == D_IN
D_IN
D_OUT
Register
D_IN
Bank
EN

CLK
Standard Non Clock Gating Implementation

D_IN D_OUT
Register
EN G_CLK Bank
Latch

CLK
Power Compiler Gated Clock Implementation

© 2004 Synopsys, Inc. (15) Interoperability Forum CONFIDENTIAL

Challenge:
Concurrent Placement, Timing, Power & Clocking

Peak &
Average Power

IR Drop
Slew
IR Drop

Skew
Clocking Placement

Max. Frequency IR Drop

Path Delays
& Slew
Skew Timing

© 2004 Synopsys, Inc. (16) Interoperability Forum CONFIDENTIAL

Synopsys Multi-Voltage Flow
Multi-Supply, Multi-Voltage Islands, Multi-Threshold Design

Design
Design Compiler
Compiler
• Support throughout
Synthesis
Synthesis implementation & sign-off flow

• Multi-Voltage & Multi-Threshold

JupiterXT
JupiterXT
Design
synthesis in DC
Design Planning
Planning

• Power plan synthesis in JupiterXT

Physical
Physical Compiler
Compiler
Implementation
Implementation • Multi-Voltage placement & Multi-
Threshold optimization in PC
Astro
Astro
Implementation
Implementation
• Multi-Voltage clock-tree synthesis
& routing in Astro
PrimeTime
PrimeTime SI
SI • Sign-off with PrimeTime
Sign-off
Sign-off

© 2004 Synopsys, Inc. (17) Interoperability Forum CONFIDENTIAL

AMBA DesignWare for AHB & APB Subsystems

© 2004 Synopsys, Inc. (18) Interoperability Forum CONFIDENTIAL

Synopsys supplies:

• Low Power IEM Design Methodology

• Multi-voltage Galaxy Implementation Flow
• AMBA DesignWare IP
• Low Power
Design Services

© 2004 Synopsys, Inc. (19) Interoperability Forum CONFIDENTIAL