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Electronics Refresher 6 – Digital Electronics

1. In 2's complement representation the number 12. ECL has high switching speed because the transistors
11100101 represents the decimal number are
A. 37 C. -31 A. switching between cutoff and saturation regions
B. +27 D. -27 B. switching between cutoff and active regions
C. switching between active and saturation regions
2. BCD input 1000 is fed to a 7 segment display through a
D. none of the above
BCD to 7 segment decoder/driver. The segments which
will lit up are 13. In the given figure, the flip flop is
A. a, b, d C. a, b, c
B. all D. a, b, g, c, d
3. A full adder can be made out of
A. two half adders A. negative edge triggered C. positive edge triggered
B. two half adders and a OR gate B. level triggered D. either A or B
C. two half adders and a NOT gate
14. In a 4 input OR gate, the total number of High outputs
D. three half adders
for the 16 input states are
4. 7BF16 = __________ 2 A. 16 C. 15
A. 0111 1011 1110 C. 0111 1011 1111 B. 14 D. 13
B. 0111 1011 0111 D. 0111 1011 0011
15. Which of the following is not a characteristic of a flip
5. A 4 : 1 multiplexer requires __________ data select flop?
line. A. It is a bistable device
A. 1 C. 2 B. It has two outputs
B. 3 D. 4 C. It has two outputs are complement of each other
D. It has one input terminal
6. AECF116 + 15ACD16 = __________ .
A. C47BB16 C. C47BE16 16. Find the output voltage for 011100 in a 6 bit R-2R
B. A234F16 D. A111116 ladder D/A converter has a reference voltage of 6.5 V.
A. 6.4 V C. 2.84 V
7. A XOR gate has inputs A and B and output Y. Then the
B. 0.1 V D. 8 V
output equation is
A. Y = AB C. Y = AB + A’B 17. In the given figure shows a negative logic AND gate. If
B. Y = A’ B + A B’ D. Y = A B’ + A’ B’ positive logic is used this gate is equivalent to
8. The minimum number of NAND gates required to
implement the Boolean function A +AB + ABC is equal
to A. AND gate C. OR gate
A. 0 C. 1 B. NOR gate D. NAND gate
B. 4 D. 7
18. A combination circuit is one in which the output
9. The initial state of MOD-16 down counter is 0110. What depends on
state will it be after 37 clock pulses? A. input combination at that time
A. Indeterminate C. 0110 B. input combination and previous output
B. 0101 D. 0001 C. input combination and previous input
D. present output and previous output
10. In a mod-12 counter the input clock frequency is 10
kHz. The output frequency is 19. A counter has a modulus of 10. The number of flip flops
A. 0.833 kHz C. 1.0 kHz is
B. 0.91 kHz D. 0.77 kHz A. 10 C. 5
B. 4 D. 3
11. A 4 input AND gate is equivalent to
A. 4 switches in parallel 20. In 8085 microprocessor, how many lines are there in
B. 2 switches in series and 2 in parallel data bus?
C. three switches in parallel and one in series A. 6 C. 8
D. 4 switches in series B. 2 D. 16
21. TTL logic is preferred to DRL logic because 32. Which of them has 10 inputs and 4 outputs?
A. greater fan-out is possible A. Decimal to BCD encoder C. BCD to decimal decoder
B. greater logic levels are possible B. Octal to binary encoder D. All encoders
C. greater fan-in is possible
33. The main advantage of CMOS circuit is
D. less power consumption is achieve
A. high gain
22. Gray code is used in devices which convert analog B. high output impedance
quantities to digital signal because it is C. low power consumption
A. more error free D. high gain and high output impedance
B. much simpler than binary code
34. RS latch can be built with
C. superior to Excess-3 code
A. NOR gates C. NAND gates
D. absolutely error free
B. NOR or NAND gates D. none of the above
23. Each cell of a static RAM has
35. To convert JK flip flop to D flip flop
A. 4 MOS transistors
A. connect D to both J and K
B. 4 MOS transistors and 2 capacitors
B. connect D to J directly and D to K through inverter
C. 2 MOS transistors and two capacitors
C. connect D to K directly and D to J through inverter
D. 1 MOS transistor and 1 capacitor
D. connect D to K and leave J open
24. The initial state of MOD-16 down counter is 011. After
36. The noise margin of a TTL gate is about
37 clock pulses, the state of the counter will be
A. 0.2 V C. 0.4 V
A. 1011 C. 0110
B. 0.6 V D. 0.8 V
B. 0101 D. 0001
37. Which of the following is not a specification of D/A and
25. The ALU carries out arithmetic and logic operations (OR
A/D converters?
AND, NOT, etc.) it processes
A. Gain C. Drift
A. decimal numbers C. binary numbers
B. Speed D. Accuracy
B. hexadecimal numbers D. octal numbers
38. An A/D converter uses for reference purposes
26. Medium scale integration refers to ICs with
A. DC voltage C. a saw tooth generator
A. more than 12 but less than 30 gates on the same
B. set of keys D. a flip-flop
chip
B. more than 50 gates on the same chip 39. A pulse stretcher is same as a
C. more than 20 but less than 100 gates on the same A. free running multivibrator
chip B. bistable multivibrator
D. more than 12 but less than 100 gates on the same C. monostable multivibrator
chip D. latch
27. A TTL circuit with totem pole output has 40. The term VLSI generally refers to a digital IC having
A. high output impedance A. more than 1000 gates
B. low output impedance B. more than 100 gates
C. very high output impedance C. more than 1000 but less than 9999 gates
D. none of the above D. more than 100 but less than 999 gates
28. The abbreviation DTL stands for 41. The fetching, decoding and executing of an instruction
A. Digital Timing Logic C. Diode Transistor Logic is broken down into several time intervals. Each of
B. Dynamic Transient Logic D. Delayed Tracking Logic these intervals, involving one or more clock periods, is
called a
29. A half adder adds __________ bits and a full adder adds
A. instruction cycle C. machine cycle
__________ bits.
B. process cycle D. none of the above
A. two, three C. three, four
B. four, six D. two, four 42. In the generic microprocessor
A. instruction cycle time period is shorter than machine
30. D flip flop can be used as a
cycle time period
A. differentiator C. divider circuit
B. machine cycle time period is shorter than instruction
B. delay switch D. none
cycle time period
31. The process of entering data into ROM is called C. instruction cycle time period is exactly half of
A. writing C. burning machine cycle time period
B. decoding D. registering
D. instruction cycle time period is exactly equal to B. clock, float D. pulsed, float
machine cycle time period
53. The output of a standard TTL NAND gate is used to pull
43. By placing an inverter between both inputs of an S-R an LED indicator LOW. The LED is in series with a 470-
flip-flop, the resulting flip-flop becomes resistor. What is the current in the circuit when the LED
A. J-K flip-flop is on?
B. D-flip-flop A. 7.02 mA C. 8.51 mA
C. T-flip-flop B. 10.63 mA D. 5.32 mA
D. Master salve JK flip-flop
54. When the inputs to a flip-flop are changing at the same
44. It is desired to route data from many registers to one time that the active trigger edge of the input clock is
register. The device needed is making its transition, this condition is called:
A. decoder C. multiplexer A. racing C. toggling
B. demultiplexer D. counter B. slave loading D. pulse timing
45. It is desired to clean up ragged looking pulsed that have 55. The term "hex inverter" refers to:
been distorted during transmission from one place to A. an inverter that has six inputs
another, which of the following device will be B. six inverters in a single package
appropriate? C. a six-input symbolic logic device
A. Multiplexer C. D/A converter D. an inverter that has a history of failure
B. JK flip-flop D. Schmitt trigger
56. What is unique about TTL devices such as the 74SXX?
46. The difference between sequential and combinational A. These devices use Schottky transistors and diodes to
circuits is prevent them from going into saturation; this results in
A. Combinational circuits store bits faster turn-on and turn-off times, which translates into
B. Combinational circuits have memory higher frequency operation.
C. Sequential circuits store bits B. The gate transistors are silicon (S), and the gates
D. Sequential circuits have memory therefore have lower values of leakage current.
C. The S denotes the fact that a single gate is present in
47. 10's complement of 16_10 is
the IC rather than the usual package of 2–6 gates.
A. 83_10 C. 84_10
D. The S denotes a slow version of the device, which is
B. 38_10 D. 48_10
a consequence of its higher power rating.
48. One of the functions of the Sio2 layer in an IC is to
57. Why must CMOS devices be handled with care?
A. act as a dielectric for capacitors
A. so they don’t get dirty
B. prevent shorting of elements by interconnections
B. because they break easily
C. from cathodes for diodes
C. because they can be damaged by static electricity
D. afford protection from the radiations
discharge
49. A logic circuit that provides a HIGH output if one input D. none of these
or the other input, but not both, is HIGH, is a(n):
58. Totem-pole outputs ________ be connected ________
A. Ex-NOR gate C. OR gate
because ________.
B. Ex-OR gate D. NAND gate
A. can, in parallel, sometimes higher current is required
50. Which of the following circuit parameters would be B. cannot, together, if the outputs are in opposite
most likely to limit the maximum operating frequency states excessively high currents can damage one or
of a flip-flop? both devices
A. setup and hold time C. should, in series, certain applications may require
B. clock pulse HIGH and LOW time higher output voltage
C. propagation delay time D. can, together, together they can handle larger load
D. clock transition time currents and higher output voltages
51. Which type of gate can be used to add two bits? 59. A basic multiplexer principle can be demonstrated
A. Ex-OR C. Ex-NOR through the use of a:
B. Ex-NAND D. NOR A. single-pole relay C. DPDT switch
B. rotary switch D. linear stepper
52. The purpose of a pull-up resistor is to keep a terminal
at a ________ level when it would normally be at a 60. In a BCD-to-seven-segment converter, why must a code
________ level. converter be utilized?
A. LOW, float C. HIGH, float A. to convert the 4-bit BCD into 7-bit code
B. to convert the 4-bit BCD into 10-bit code B. The delay times are greatly reduced over other
C. to convert the 4-bit BCD into Gray code forms.
D. No conversion is necessary. C. No signal must pass through more than two gates,
not including inverters.
61. Convert BCD 0001 0010 0110 to binary.
D. The maximum number of gates that any signal must
A. 1111110 C. 1111101
pass through is reduced by a factor of two.
B. 1111000 D. 1111111
68. Which of the following combinations of logic gates can
62. The implementation of simplified sum-of-products
decode binary 1101?
expressions may be easily implemented into actual
A. One 4-input AND gate
logic circuits using all universal ________ gates with
B. One 4-input AND gate, one OR gate
little or no increase in circuit complexity.
C. One 4-input NAND gate, one inverter
A. AND/OR C. NAND
D. One 4-input AND gate, one inverter
B. NOR D. OR/AND
69. The condition occurring when two or more devices try
63. Which of the following statements accurately
to write data to a bus simultaneously is called
represents the two BEST methods of logic circuit
A. address decoding C. bus contention
simplification?
B. bus collisions D. address multiplexing
A. Boolean algebra and Karnaugh mapping
B. Karnaugh mapping and circuit waveform analysis 70. Which of the following best describes static memory
C. Actual circuit trial and error evaluation and devices?
waveform analysis A. memory devices that are magnetic in nature and do
D. Boolean algebra and actual circuit trial and error not require constant refreshing
evaluation B. memory devices that are magnetic in nature and
require constant refreshing
64. As a technician you are confronted with a TTL circuit
C. semiconductor memory devices in which stored data
board containing dozens of IC chips. You have taken
will not be retained with the power applied unless
several readings at numerous IC chips, but the readings
constantly refreshed
are inconclusive because of their erratic nature. Of the
D. semiconductor memory devices in which stored data
possible faults listed, select the one that most probably
is retained as long as power is applied
is causing the problem.
A. A defective IC chip that is drawing excessive current 71. The nominal value of the dc supply voltage for TTL and
from the power supply CMOS is
B. A solar bridge between the inputs on the first IC chip A. +3 V C. +9 V
on the board B. +5 V D. +12 V
C. An open input on the first IC chip on the board
72. An open-collector output requires
D. A defective output IC chip that has an internal open
A. a pull-down resistor C. no output resistor
to Vcc
B. a pull-up resistor D. an output resistor
65. Which gate is best used as a basic comparator?
73. Emitter-coupled logic (ECL) is much faster than TTL
A. NOR C. OR
because
B. Exclusive-OR D. AND
A. transistor do not operate in saturation
66. The device shown here is most likely a ________. B. transistor do not operate in cut-off
C. it has less power dissipation
D. all of them
74. Which of the following is not a jump instruction?
A. JB (jump back) C. JO (jump if overflow)
B. JA (jump above) D. JMP(unconditional jump)
75. Which of the following computer memories is fastest?
A. comparator C. multiplexer A. Cache C. Mass storage
B. demultiplexer D. parity generator B. Primary D. Off line back up
67. Which of the following is an important feature of the 76. The bit capacity of a memory that has 2048 addresses
sum-of-products form of expressions? and can store 8 bits at each address is
A. All logic circuits are reduced to nothing more than A. 4096 C. 16358
simple AND and OR operations. B. 8129 D. 32768