Exploring the Nature of

Spice Convergence
Problems

A discussion of Spice

algorithms and

guidlines for avoiding

convergence

problems.

Exploring the Nature of

Spice Convergence Problems
table of contents Preface
Overcoming problems that impede convergence is key to successful
Spice simulation. Some causes of convergence problems are common to
all Spice simulators.

This appendix discusses common errors

How to avoid them is explained here.
and convergence problems in PSpice.
Note: PSpice® has several unique characteristics that make it better at
achieving convergence than some other Spice simulators. Therefore, it
is used in the discussion following.

Preface 1

Introduction
In order to calculate the bias point, DC sweep and transient analysis for
analog devices PSpice must solve a set of nonlinear equations which
Introduction 1
describe the circuit's behavior. This is accomplished by using an iterative
technique—the Newton-Raphson algorithm—which starts by having an
initial approximation to the solution and iteratively improves it until
successive voltages and currents converge to the same result.
Bias point and DC sweep 5
In a few cases PSpice cannot find a solution to the nonlinear circuit
equations. This is generally called a “convergence problem” because
the symptom is that the Newton-Raphson repeating series cannot con-
verge onto a consistent set of voltages and currents. The following
Transient analysis 8
discussion gives some background on the algorithms in PSpice and
some guidelines for avoiding convergence problems.

The AC and noise analyses are linear and do not use an iterative algo-
Diagnostics 11 rithm, so the following discussion does not apply to them. Digital
devices are evaluated using boolean algebra; this discussion does not
apply to them either.

The transient analysis has the additional possibility of being unable to

continue because the time step required becomes too small from some-
thing in the circuit moving too fast. This is also discussed herein.

1
Newton-Raphson requirements To find out more about the diode equations, refer to the Analog
The Newton-Raphson algorithm is guaranteed to converge to Devices chapter in the online PSpice A/D Reference Manual.
a solution. However, this guarantee has some conditions: It can be shown that the current through a diode is:

I = IS ∗eV/(N∗k∗T)
1 The nonlinear equations must have a solution.
N defaults to one and k*T at room temperature is about .025 volts.
2 The equations must be continuous. So, in this example the current through the diode would be:

3 The algorithm needs the equations’ derivatives. I = 1e-16∗e200 = 7.22e70 amps

4 The initial approximation must be close enough to the solution. This circuit also does not have a solution within the limits of the
dynamic range of PSpice. In general, be careful of components without
Each of these can be taken in order. Remember that the PSpice limits built into them. Extra care is needed when using the expressions
algorithms are used in computer hardware that has finite precision and for controlled sources (such as for behavioral modeling). It is easy to
finite dynamic range that produce these limits: write expressions with very large values.

• Voltages and currents in PSpice are limited to +/-1e10 volts

and amps. Are the Equations Continuous?
The device equations built into PSpice are continuous. The functions
• Derivatives in PSpice are limited to 1e14. available for behavioral modeling are also continuous (there are several
functions, such as int(x), which cannot be added because of this). So,
• The arithmetic used in PSpice is double precision and has 15 digits for physically realistic circuits the equations can also be continuous.
of accuracy. Exceptions that come are usually from exceeding the limits of the
numerics in PSpice. This example tries to approximate an ideal switch
using the diode model:
Is there a solution?
.MODEL DMOD(IS=1e-16 N=1e-6)
Yes, for any physically realistic circuit. However, it is not difficult to set
up a circuit that has no solution within the limits of PSpice numerics.
The current through this diode is:
Consider, for example, a voltage source of one megavolt connected to
a resistor of one micro-ohm. This circuit does not have a solution I = 1e-16 ∗eV/(N∗.025) = 1e-16∗e V/25e-9
within the dynamic range of currents (+/- 1e10 amps). Here is another
example: Avoid unrealistic model parameters. Behavioral modeling expressions
need extra care.
V1 1, 0 5v
D1 1, 0 DMOD
.MODEL DMOD(IS=1e-16) Because the denominator in the exponential is so small, the current I is
essentially zero for V < 0 and almost infinite for V > 0. Even if there are
The problem here is that the diode model has no series resistance. external components that limit the current, the “knee” of the diode’s
I-V curve is so sharp that it is almost a discontinuity.

2 3
Are the derivatives correct? not variable, however. If a solution cannot be found at a step then the
The device equations built into PSpice include the derivatives, and bias point algorithm is used for that step.
these are correct. Depending on the device, the physical meaning of
the derivatives is small-signal conductance, transconductance or gain. The whole process relies heavily on continuity. It also requires that the
circuit be linear when the supplies are turned off.
Unrealistic model parameters can exceed the limit of 1e14, but it
requires some effort. The main thing to look at is the behavioral STEPGMIN
modeling expressions, especially those having denominators. An alterative algorithm is GMIN stepping. This is not obtained by
default, and is enabled by specifying the circuit analysis option STEPG-
MIN (either using .OPTION STEPGMIN in the netlist, or by making the
Is the initial approximation close enough? appropriate choice from the Analysis/Setup/Options menu). When
Newton-Raphson is guaranteed to converge only if the analysis is start- enabled, the GMIN stepping algorithm is applied after the circuit fails
ed close to the answer. Also, there is no measurement that can tell how to converge with the power supplies at 100 percent, and if GMIN step-
close is close enough. ping also fails, the supplies are then cut back to almost zero.

PSpice gets around this by making heavy use of continuity. Each analy- GMIN stepping attempts to find a solution by starting the repeating
sis starts from a known solution and uses a variable step size to find cycle with a large value of GMIN, initially 1.0e10 times the nominal
the next solution. If the next solution does not converge PSpice reduces value. If a solution is found at this setting it then reduces GMIN by a
the step size, falls back and tries again. factor of 10, and tries again. This continues until either GMIN is back to
the nominal value, or a repeating cycle fails to converge. In the latter
Bias point case, GMIN is restored to the nominal value and the power supplies
The hardest part of the whole process is getting started, that is, finding are stepped.
the bias point. PSpice first tries with the power supplies set to 100%. A
solution is not guaranteed, but most of the time the PSpice algorithm
finds one. If not, then the power supplies are cut back to almost zero. Bias point and DC sweep
They are cut to a level small enough that all nonlinearities are turned Power supply stepping
off. When the circuit is linear a solution can be found (very near zero, As previously discussed, PSpice uses a proprietary algorithm which finds
of course). Then, PSpice works its way back up to 100% power supplies a continuous path from zero power supplies levels to 100%. It starts
using a variable step size. at almost zero (.001%) power supplies levels and works its way back up
to the 100% levels. The minimum step size is 1e-6 (.0001%). The first
Once a bias point is found the transient analysis can be run. It starts repeating series of the first step starts at zero for all voltages .
from a known solution (the bias point) and steps forward in time. The
step size is variable and is reduced as needed to find further solutions.
Semiconductors
DC sweep Model parameters
The DC sweep uses a hybrid approach. It uses the bias point algorithm The first consideration for semiconductors is to avoid physically unreal-
(varying the power supplies) to get started. For subsequent steps it uses istic model parameters. Remember that as PSpice steps the power sup-
the previous solution as the initial approximation. The sweep step is plies up it has to step carefully through the turn on transition for each
device. In the diode example above, for the setting N=1e-6, the knee of

4 5
the I-V curve would be too sharp for PSpice to maintain its continuity Behavioral modeling expressions
within the power supply step size limit of 1e-6. Range limits
Voltages and currents in PSpice are limited to the range +/- 1e10. Care
Unguarded p-n junctions must be taken that the output of expressions fall within this range.
A second consideration is to avoid “unguarded” p-n junctions (no series This is especially important when one is building an electrical analog of
resistance). The above diode example also applies to the p-n junctions a mechanical, hydraulic or other type of system.
inside bipolar transistors, MOSFETs (drain-bulk and source-bulk), JFETs
and GaAsFETs. Source limits
Another consideration is that the controlled sources must turn off
No leakage resistance when the supplies are almost 0 (.001%). There is special code in PSpice
A third consideration is to avoid situations which could have an ideal which “squelches” the controlled sources in a continuous way near 0
current source pushing current into a reverse-biased p-n junction supplies. However, care should still be taken using expressions that
without a shunt resistance. Since p-n junctions in PSpice have (almost) have denominators. Take, for example, a constant power load:
no leakage resistance and would cause the junction's voltage to go GLOAD 3, 5 VALUE = {2Watts/V(3,5)}
beyond 1e10 volts.

The first repeating series starts with V(3,5) = 0 and the current through
The model libraries which are part of PSpice follow these guidelines.
GLOAD would be infinite (actually, the code in PSpice which does
the division clips the result to a finite value). The “squelching” code is
Typos can cause unrealistic device parameters. The following MOSFET:
M1 3, 2, 1, 0 MMOD L=5 W=3 required to be a smooth and well-behaved function.
has a length of five meters and a width of three meters instead of
micrometers. It should have been: Note: The “squelching” code cannot be “strong” enough to suppress
M1 3, 2, 1, 0 MMOD L=5u W=3u dividing by 0.

PSpice flags an error for L too large, but cannot for W because power The result is that GLOAD does not turn off near 0 power supplies. A
MOSFETs are so interdigitated (a zipper-like trace) that their effective better way is described in the application note Modeling Constant
W can be very high. The LIST option can show this kind of problem. Power Loads. The “squelching” code is sufficient for turning off all
When the devices are listed in the output file their values are shown in expressions except those having denominators. In general, though, it is
scientific notation making it easy to spot unusual values. good practice to constrain expressions having the LIMIT function to
keep results within physically realistic bounds.

Switches Example: A first approximation to an opamp that has an open loop

PSpice switches have gain in their transition region. If several are cas- gain of 100,000 is:
caded then the cumulative gain can easily exceed the derivative limit of VOPAMP 3, 5 VALUE = {V(in+,in-)*1e5}
1e14. This can happen when modeling simple logic gates using totem-
pole switches and there are several gates in cascaded in series. Usually This has the undesirable property that there is no limit on the output.
a cascade of two switches works but three or more can cause trouble. A better expression is:
VOPAMP 3, 5 VALUE =
+ {LIMIT(V(in+,in-)*1e5,15v,-15v}
where the output is limited to +/- 15 volts.

6 7
Transient analysis The dynamic range of TIME
The transient analysis starts using a known solution - the bias point. It TIME, the simulation time during transient analysis, is a double preci-
then uses the most recent solution as the first guess for each new time sion variable which gives it about 15 digits of accuracy. The dynamic
point. If necessary, the time step is cut back to keep the new time point range is set to be 15 digits minus the number of digits of accuracy
close enough that the first guess allows the Newton-Raphson repeating required by RELTOL. For a default value of RELTOL = .001 (.1% or 3 dig-
series to converge. The time step is also adjusted to keep the integra- its) this gives 15-3 = 12 digits. This means that the minimum time step is
tion of charges and fluxes accurate enough. the overall run time (TSTOP) divided by 1e12. The dynamic range is
large but finite.
In theory the same considerations which were noted for the bias point
calculation apply to the transient analysis. However, in practice they It is possible to exceed this dynamic range in some circuits. Consider,
show up during the bias point calculation first and, hence, are correct- for example, a timer circuit which charges up a 100uF capacitor to pro-
ed before a transient analysis is run. vide a delay of 100 seconds. At a certain threshold a comparator turns
on a power MOSFET. The overall simulation time is 100 seconds. For
The transient analysis can fail to complete if the time step gets too default RELTOL this gives us a minimum time step of 100 picoseconds.
small. This can have two different effects: If the comparator and other circuitry has portions that switch in a
nanosecond then PSpice needs steps of less than 100 picoseconds to
1 The Newton-Raphson iterations would not converge even for the calculate the transition accurately.
smallest time step size, or

2 Something in the circuit is moving faster than can be accommodat- Failure at the first time step
ed by the minimum step size. If the transient analysis fails at the first time point then usually there is
an unreasonably large capacitor or inductor. Usually this is due to a
The message PSpice puts into the output file specifies which condition typographical error. Consider the following capacitor:
occurred. C 1 3, 0 1Ouf

“1O” (has the letter O) should have been “10.” This capacitor has a
value of one farad, not 10 microfarads. An easy way to catch these is to
Skipping the bias point
use the LIST option (on the .OPTIONS command).
The SKIPBP option for the transient analysis skips the bias point calcula-
tion. In this case the transient analysis has no known solution to start
LIST
from and, therefore, is not assured of converging at the first time
The LIST option can echo back all the devices into the output file
point. Because of this, its use is not recommended. Its inclusion in
that have their values in scientific notation.
PSpice is to maintain compatibility with UC Berkeley SPICE. SKIPBP has
the same meaning as UIC in Berkeley SPICE. UIC is not needed in order
That makes it easy to spot any unusual values. This kind of problem
to specify initial conditions.
does not show up during the bias point calculation because capacitors
and inductors do not participate in the bias point.

Similar comments apply to the parasitic capacitance parameters in tran-

sistor (and diode) models. These are normally echoed to the output file

8 9
(the NOMOD option suppresses the echo but the default is to echo). Note: Orcad recommends that all inductors have a parallel resistor
As in the LIST output, the model parameters are echoed in scientific (series resistance is good for modeling DC effects but does not limit the
notation making it easy to spot unusual values. A further diagnostic is inductor’s bandwidth).
to ask for the detailed operating bias point (.TRAN/OP) information.
The parallel resistor gives a good model for eddy current loss and limits
.TRAN/OP the bandwidth of the inductor. The size of resistor should be set to be
This lists the small-signal parameters for each semiconductor device equal to the inductor’s impedance at the frequency at which its Q
including the calculated parasitic capacitances. begins to roll off.

Example: A common one millihenry iron core inductor begins to roll off
Parasitic capacitances at no less than 100KHz. A good resistor value to use in parallel is then
It is important that switching times be nonzero. This is assured if R = 2* π*100e3*.001 = 628 ohms. Below the roll-off frequency the
devices have parasitic capacitances. The semiconductor model libraries inductor dominates; above it the resistor does. This keeps the width of
in PSpice have such capacitances. If switches and/or controlled sources spikes from becoming unreasonably nar row.
are used, then care should be taken to assure that no sections of
circuitry can try to switch in zero time. In practice this means that if
any positive feedback loops exist (such as a Schmidt trigger built out of Bipolar transistors substrate junction
switches) then such loops should include capacitances. The UC Berkeley SPICE contains an unfortunate convention for the sub-
strate node of bipolar transistors. The collector-substrate p-n junction
Another way of saying all this is that during transient analysis the has no DC component. If the capacitance model parameters are speci-
circuit equations must be continuous over time (just as during the bias fied (e.g., CJS) then the junction has (voltage-dependent) capacitance
point calculation the equations must be continuous with the power but no DC current. This can lead to a sneaky problem: if the junction is
supply level). inadvertently forward-biased it can create a very large capacitance.
The capacitance goes as a power of the junction voltage. Normal junc-
tions cannot sustain much forward voltage because a large current
Inductors and transformers flows. The collector-substrate junction is an exception because it has no
While the impedance of capacitors gets lower at high frequencies DC current.
(and small time steps) the impedance of inductors gets higher.
If this happens it usually shows up at the first time step. It can be spot-
Note: The inductors in PSpice have an infinite bandwidth. ted turning on the detailed operating point information (.TRAN/OP)
and looking at the calculated value of CJS for bipolar transistors. The
Real inductors have a finite bandwidth due to eddy current losses whole problem can be prevented by using the PSpice model parameter
and/or skin effect. At high frequencies the effective inductance drops. ISS. This parameter “turns on” DC current for the substrate junction.
Another way to say this is that physical inductors have a frequency at
which their Q begins to roll off. The inductors in PSpice have no such
limit. This can lead to very fast spikes as transistors (and diodes) con-
nected to inductors turn on and off. The fast spikes, in turn, can force
PSpice to take unrealistically small time steps.

10 11
Diagnostics
If PSpice encounters a convergence problem it inserts into the output
file a message that looks like the following.

ERROR -- Convergence problem in transient analysis at Time = 7.920E-03

Time step = 47.69E-15, minimum allowable step size = 300.0E-15

These voltages failed to converge:

V(x2.23) = 1230.23 / -68.4137
V(x2.25) = -1211.94 / 86.6888

These supply currents failed to converge:

I(X2.L1) = -36.6259 / 2.25682
I(X2.L2) = -36.5838 / 2.29898

These devices failed to converge:

X2.DCR3 X2.DCR4 x2.ktr X2.Q1 X2.Q2

Last node voltages tried were:

NODE VOLTAGE NODE VOLTA GE NODE VOLTAGE NODE VOLTAGE
( 1) 25.2000 ( 3) 4.0000 ( 4) 0.0000 ( 6) 25.2030
(x2.23) 1230.2000 (X2.24) 9.1441 (x2.25) -1211.9000 (X2.26) 256.9700
(X2.28) -206.6100 (X2.29) 75.4870 (X2.30) -25.0780 (X2.31) 26.2810
(X3.34) 1.771E-06 (X3.35) 1.0881 (X3.36) .4279 (X2.XU1.6) 1.2636

The message always includes the banner (ERROR -- convergence

problem ...) and the trailer (Last node voltages tried were
...). It cannot include all three of the middle blocks.

The Last node voltages tried... trailer shows the voltages tried
at the last Newton-Raphson iteration. If any of the nodes have unrea-
sonable large values this is a clue that these nodes are related to the
problem. These voltages failed to converge lists the specific
nodes which did not settle onto consistent values. It also shows their
values for the last two iterations. These supply currents failed
converge does the same for currents through voltage sources and
inductors. If any of the listed numbers are +/- 1e10 then that is an indi-
cation that the value is being clipped from an unreasonable value.
Finally, These devices failed to converge shows devices whose
terminal currents or core fluxes did not settle onto consistent values.

The message gives a clue as to the part of the circuit which is causing
the problem. Looking at those devices and/or nodes for the problems
discussed above is recommended.

12