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LM494 Spice Model

This document describes the circuit design of a TL494 pulse width modulated control circuit. Key components include an oscillator to generate pulses, a dead time comparator to prevent simultaneous switching, a PWM comparator to compare feedback and reference signals, and error amplifiers. Additional circuitry includes undervoltage locks, a flip flop for 50% duty cycle, and transistor drivers for the output. The circuit uses operational amplifiers, diodes, resistors, capacitors and NPN and PNP transistors in the design.

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0% found this document useful (0 votes)
227 views3 pages

LM494 Spice Model

This document describes the circuit design of a TL494 pulse width modulated control circuit. Key components include an oscillator to generate pulses, a dead time comparator to prevent simultaneous switching, a PWM comparator to compare feedback and reference signals, and error amplifiers. Additional circuitry includes undervoltage locks, a flip flop for 50% duty cycle, and transistor drivers for the output. The circuit uses operational amplifiers, diodes, resistors, capacitors and NPN and PNP transistors in the design.

Uploaded by

Robert
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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**************************************************************************

**** LM494 Pulse Width Modulated Control Circuit ****


**************************************************************************
.SUBCKT TL494_1 1IN+ 1IN- FB DTC CT RT GND CL1 EM1 EM2 CL2 VCC OCO REF 2IN-
2IN+
*.................1...2...3...4...5...6...7...8...9...10...11...12...13...14...15..
.16
*;
**** TL494 OSCILLATOR ****
* Vref bias & transistor mirror to separate RT & CT legs
Vref1 VREF1 GND DC 3.65V
*;
Q1 RT RT VREF1 T0094C
Q2 CT RT VREF1 T0094C
*;
Stof1 CT DISCH CT GND SOSC_1
*.....P..N...CP..CN
R1 DISCH GND 300
*;
**** Dead Time Comparator ****
Vref2 DT_OFFSET DTC DC +0.12V
Vref3 TRIM1 GND DC +3.0V
*;
Ecomp1 C_DT GND value = { IF
+((~V(CT,GND) < V(DT_OFFSET,GND)), V(TRIM1,CT), 0V ) } ; NOTTED
*;
**** PWM Comparator ****
Vref4 PWM_OFFSET CT DC +0.7V
Gref5 FB GND DC +0.7ma
Vref6 TRIM2 GND DC +3.0V
*;
Ecomp2 C_PWM GND value = { IF
+(( ~V(PWM_OFFSET,GND) > V(FB,GND) ), 0V, V(TRIM2,CT) ) } ; NOTTED
*;
**** Error Amp1 ****
Eerr1 ERR1 GND value = { IF
+(( V(1IN+,GND) < V(1IN-,GND)), 0V, V(1IN+,1IN-) ) }
D1 FB ERR1 D
*;
**** Error Amp2 ****
Eerr2 ERR2 GND value = { IF
+(( V(2IN+,GND) < V(2IN-,GND)), 0V, V(2IN+,2IN-) ) }
*;
D2 FB ERR2 D
*;
**** UV LOCK1 ****
Vref7 UV1_REF GND DC +4.9V
Euv1 C_UV1 GND value = { IF
+(( V(VCC,GND) < V(UV1_REF,GND)), +5.0V, 0V ) }
*;
**** UV LOCK2 ****
Vref8 UV2_REF GND DC +3.5V
Vref9 REF GND DC +5.0V ; +5.0V REF out @ pin 14
Euv2 C_UV2 GND value = { IF
+(( V(REF,GND) < V(UV2_REF,GND)), +5.0V, 0V ) }
*;
**** OR 4 ***
Eor4 PWMY GND value = { IF
+(( V(C_DT,GND) < +2.5V )
+|( V(C_PWM,GND) < +2.5V )
+|( V(C_UV1,GND) > +2.5V )
+|( V(C_UV2,GND) > +2.5V ), +5.0V, 0V ) }
*;
*********************************************
**** 50% Duty Cycle Flip Flop ****
*;
.subckt NAND3_1 1 2 3 4
*...............A.A.A.Y
E1 5 0 VALUE = { IF
+(( V(1) > +1.0V ) ; critical non standard
+&( V(2) > +2.5V )
+&( V(3) > +2.5V ), 0V, +5.0V ) }
R1 5 4 100
C1 4 0 20P
.ends NAND3_1
*;
.subckt FFLOP_1 1 2 3 4 5 6
*.............CLK..D..R..S..QB..Q
X1 7 4 2 8 NAND3_1
X2 8 3 10 9 NAND3_1
X3 1 8 10 7 NAND3_1
X4 4 9 1 10 NAND3_1
X5 4 7 6 5 NAND3_1
X6 5 10 3 6 NAND3_1
.ends FFLOP_1
*;
**** exor T FF conversion of D ff *********
Exor DIV2 GND value = { IF
+(( V(50,GND) > +2.5V )
+^( V(51,GND) > +2.5V ), +5.0V, 0V ) }
*;
Xtoggle PWMY DIV2 REF REF 50 51 FFLOP_1
*.......CLK...D...R...S...Q..QB
*;
****************************************
**** PWM OUTPUT CONTROL ****
*;
**** Control AND'S ****
.subckt AND2_1 1 2 3
*..............A.A.Y
Eand1 4 0 value = { IF
+(( V(1) > +2.5V )
+&( V(2) > +2.5V ), +5.0V, 0V ) }
R1 4 3 100
C1 3 0 20P
.ends AND2_1
*;
Xand1 OCO 50 ANDOUT1 AND2_1
Xand2 OCO 51 ANDOUT2 AND2_1
*;
**** NOR Drive to Transistors ****
.subckt NOR2_1 1 2 3
*..............A.A.Y
E1 4 0 value = { IF
+(( V(2) > +2.5V )
+|( V(1) > +2.5V ), 0V, +5.0V ) }
R1 4 3 100
C1 3 0 20P
.ends NOR2_1
*;
Xnor1 PWMY ANDOUT1 DRIVE1 NOR2_1
Xnor2 PWMY ANDOUT2 DRIVE2 NOR2_1
*;
**** Transistor Drivers Output ****
Q3 EM1 DRIVE1 CL1 2N3904G
Q4 EM2 DRIVE2 CL2 2N3904G
*;
******* MODELS LIST ******
*;
.model SOSC_1 VSWITCH (RON=.01 ROFF=1MEG VT=+0.625V VH=+0.3125V
*;
.model T0094C PNP
+(IS=28.000F NF=1.000 BF=520 VAF=43.000 IKF=0.380
+ ISE=24.903F NE=2.234 NR=1.005 BR=4.800 VAR=6.960 IKR=0.932
+ ISC=0.125P NC=2.074
+ RB=2.200 IRB=0.100M RBM=1.500
+ RE=0.300 RC=2.251
+ CJE=11.800P VJE=1.000 MJE=0.435 FC=0.750
+ CJC=8.700P VJC=0.900 MJC=0.600 XCJC=0.650
+ TF=0.600N TR=2.604N PTF=1.000
+ XTF=6.500 VTF=2.000 ITF=0.314
+ XTB=1.600 EG=1.110 XTI=3.300
+ KF=5.000F AF=1.000)
*;
.model D D
;
.model 2N3904G NPN
+IS=1.26532e-10 BF=206.302 NF=1.5 VAF=1000
+IKF=0.0272221 ISE=2.30771e-09 NE=3.31052 BR=20.6302
+NR=2.89609 VAR=9.39809 IKR=0.272221 ISC=2.30771e-09
+NC=1.9876 RB=5.8376 IRB=50.3624 RBM=0.634251
+RE=0.0001 RC=2.65711 XTB=0.1 XTI=1
+EG=1.05 CJE=4.64214e-12 VJE=0.4 MJE=0.256227
+TF=4.19578e-10 XTF=0.906167 VTF=8.75418 ITF=0.0105823
+CJC=3.76961e-12 VJC=0.4 MJC=0.238109 XCJC=0.8
+FC=0.512134 CJS=0 VJS=0.75 MJS=0.5
+TR=6.82023e-08 PTF=0 KF=0 AF=1
*;
.ENDS TL494_1
**************************************************************************

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