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05/23 Change To Voltage Control FAN: LPC & Misc

This document provides a schematic for an electronic circuit board. The schematic shows the connections between various components including capacitors, resistors, and integrated circuits. Lines and labels indicate signal paths and I/O pins between the components. The design aims to control gates, reset buttons, PWM signals, and beep functions through connections between the listed parts.
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© © All Rights Reserved
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Available Formats
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0% found this document useful (0 votes)
245 views

05/23 Change To Voltage Control FAN: LPC & Misc

This document provides a schematic for an electronic circuit board. The schematic shows the connections between various components including capacitors, resistors, and integrated circuits. Lines and labels indicate signal paths and I/O pins between the components. The design aims to control gates, reset buttons, PWM signals, and beep functions through connections between the listed parts.
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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+3VALW_EC

+3VALW_EC
Ra

1
0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K R405
+3VALW
1 1 1 1 1
+3VALW_EC +EC_AVCC 100K_0402_5%
C469 C470 C471 C472 C473 R406

2
2 1 M/B_ID
2 2 2 2 2 0_0805_5% Rb

1
0.1U_0402_16V4Z 1000P_0402_50V7K 1
@ C474 R407

111
125
22
33
96

67
0_0402_5%

9
U20 0.1U_0402_16V4Z
2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC

2
GATEA20 1 21 INV_PWM
19 GATEA20 KB_RST# GA20/GPIO00 INVT_PWM/PWM1/GPIO0F EC_BEEP INV_PWM 17
19 KB_RST#
2
KBRST#/GPIO01 BEEP#/PWM2/GPIO10
23 EC_BEEP 27 VCC 3.3V+/-5%
SIRQ 3 26
20 SIRQ SERIRQ# FANPWM1/GPIO12
LPC_LFRAME# 4 27 ACOFF Ra 100K+/-5%
19,22,31 LPC_FRAME# LPC_LAD3 LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 35
@ C476 @ R408 19,22,31 LPC_AD3 5 LAD3 1 2 ECAGND
1 2 1 2 19,22,31 LPC_AD2 LPC_LAD2 7 PWM Output C475 0.01U_0402_16V7K Board ID Rb V AD_BID min V AD_BID typ V AD_BID max
LPC_LAD1 LAD2 BATT_TEMP
19,22,31 LPC_AD1 8 63 BATT_TEMP 40
LPC_LAD0 LAD1 BATT_TEMP/AD0/GPIO38 BATT_OVP
15P_0402_50V8J 33_0402_5% 19,22,31 LPC_AD0 10
LAD0 LPC & MISC BATT_OVP/AD1/GPIO39
64 BATT_OVP 35 0 0 0V 0V 0V
65 ADP_IN
ADP_I/AD2/GPIO3A ADP_I 35
CLK_PCI_EC 12 AD Input 66 M/B_ID 1 8.2K+/-5% 0.216V 0.250V 0.289V
15 CLK_PCI_EC PCI_RST# PCICLK AD3/GPIO3B
13 75
18,31 PCI_RST# ECRST# PCIRST#/GPIO05 AD4/GPIO42
+3VALW 2 R409 1 37 ECRST# SELIO2#/AD5/GPIO43 76 05/23 change to 2 18K+/-5% 0.436V 0.503V 0.538V
47K_0402_5% EC_SCI#
C477 20 EC_SCI#
20
38
SCI#/GPIO0E voltage control FAN 3 33K+/-5% 0.712V 0.819V 0.875V
CLKRUN#/GPIO1D

1
1 2 J1 68 DAC_BRIG
DAC_BRIG/DA0/GPIO3C EN_FAN DAC_BRIG 17
EN_DFAN1/DA1/GPIO3D
70 EN_FAN 4 4 56K+/-5% 1.036V 1.185V 1.264V
JOPEN DA Output 71 IR EF
IREF 35

2
0.1U_0402_16V4Z KSI0 IREF/DA2/GPIO3E
55
KSI0/GPIO30 DA3/GPIO3F
72 5 100K+/-5% 1.453V 1.650V 1.759V
KSI1 56
KSI2 KSI1/GPIO31
57 KSI2/GPIO32 6 200K+/-5% 1.935V 2.200V 2.341V
KSI3 58 83 EC_MUTE#
KSI4 KSI3/GPIO33 PSCLK1/GPIO4A ACZ_RST# EC_MUTE# 28
59 KSI4/GPIO34 PSDAT1/GPIO4B 84
ACZ_RST# 19,27 7 NC 2.500V 3.300V 3.300V
KSI5 60 85
KSI6 KSI5/GPIO35 PSCLK2/GPIO4C
61
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
86
+3VS +5VALW KSI7 62 87 TP_CLK TP_CLK 30 +5VS
KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA
39 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F 88 TP_DATA 30
+3VALW +3VS KSO1 40
KSO2 KSO1/GPIO21 R411 CLK_ENABLE TP_CLK
41 CLK_ENABLE 15 2 1
KSO3 KSO2/GPIO22
42 KSO3/GPIO23 SDICS#/GPXOA00 97 2 1 10K_0402_5% 10K_0402_5% R410
1

KSO4 43 98 LAN_POWER_OFF TP_DATA 2 1


KSO5 KSO4/GPIO24 SDICLK/GPXOA01 LAN_POWER_OFF 24
KSO5/GPIO25 Int. K/B
R415 R416 44 99 10K_0402_5% R412
SDIDO/GPXOA02
1

4.7K_0402_5% KSO6 45 109


KSO7 KSO6/GPIO26 Matrix SDIDI/GPXID0 Remove T/P dis/ena
R417 R418 4.7K_0402_5% R413 R414 46 KSO7/GPIO27 SPI Device Interface 06/14
4.7K_0402_5% 10K_0402_5% 10K_0402_5% KSO8 47
2

4.7K_0402_5% KSO9 KSO8/GPIO28 FR D#


48 KSO9/GPIO29 SPIDI/RD# 119 FRD# 31 C505
SMB_EC_DA1 KSO10 49 120 FWR#
FWR# 31
2

SMB_EC_CK1 KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK AC IN


50
KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 126 SPI_CLK 31 1 2
SMB_EC_DA2 KSO12 51 128 FSEL#
SMB_EC_CK2 LID_SW# WL_BTN# KSO13 KSO12/GPIO2C SPICS# FSEL# 31
52 KSO13/GPIO2D
KSO14 53 100P_0402_50V8J
R467 0_0402_5% KSO15 KSO14/GPIO2E I2C_INT
SUSP# EC_SUSP#
54 KSO15/GPIO2F CIR_RX/GPIO40 73
VCC1_PWRGD I2C_INT 30 04/17
R468
1 2
0_0402_5%
81
82
KSO16/GPIO48 CIR_RLC_TX/GPIO41
74
89 FSTCHG VCC1_PWRGD 31 05/23 EC request
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 FSTCHG 35
PWRBTN_OUT# 1 2 EC_PWRBTN_OUT# 90
BATT_CHGI_LED#/GPIO52 AMBER_LED# 30
91 CAPS_LED#
SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED# CAPS_LED# 31
R451 @ 0_0402_5%
31,40 SMB_EC_CK1 77
SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54 92 BLUE_LED# 30
SUSP# 1 2 SMB_EC_DA1 78 93 ON/OFFBTN_LED#
23,33,35,37,38 SUSP# 31,40 SMB_EC_DA1 SMB_EC_CK2 SDA1/GPIO45 SUSP_LED#/GPIO55 SYSON ON/OFFBTN_LED# 30,31
R460 0_0402_5%
4,30 SMB_EC_CK2 79 SCL2/GPIO46 S M Bus SYSON/GPIO56 95
SYSON 23,33,37
PWRBTN_OUT#1 @ 2 SMB_EC_DA2 80 121 VR_ON
20 PWRBTN_OUT# 4,30 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 39
AC IN
R461 @ 0_0402_5% AC_IN/GPIO59
127
2
ACIN
1
35 For EMI
ESB_CLK 1 2 EC_PIN17 R419 10K_0402_5% CP1
ESB_CLK SLP_S3# EC_RSMRST# KSO14
R462 0_0402_5% 6 100 JP31 1 8
ESB_DATA EC_PIN18 20 SLP_S3# SLP_S5# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 20 KSO15 KSO11
ESB_DATA 1 @ 2 14 101 R420 1 0_0402_5%
2 EC_LID_OUT# 20 1 2 7
20 SLP_S5# EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON KSO10 1 KSO10
15 EC_SMI#/GPIO08 EC_ON/GPXO05 102 EC_ON 30 2 2 3 6
20 EC_SMI# LID_SW# KSO11 KSO15
30 LID_SW# EC_PIN17
16
17
LID_SW#/GPIO0A EC_SWI#/GPXO06
103
104 PM_PWROK BT_OFF 29 04/14 KSO14
3
4
3
4 5

EC_PIN18 SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PM_PWROK 7,20 KSO13 4


18
PBTN_OUT#/GPIO0C G PO BKOFF#/GPXO08
105
BKOFF# 17
5
5
@ 100P_1206_8P4C_50V8
PCI_PME# 19 GPIO 106 M_PWROK KSO12 6 CP2
18 PCI_PME# EC_PME#/GPIO0D WL_OFF#/GPXO09 M_PWROK 7,20 KSO3 6 KSO6
06/15 Change pin define for try ENE cap bottom 25
EC_THERM#/GPIO11 GPXO10
107
WL_ON#
EC_MUTE 28
KSO6
7
7 KSO3
1 8
4 FAN_SPEED CAP_RESET
28
29
FAN_SPEED1/FANFB1/GPIO14 GPXO11 108 WL_ON# 22 05/03 KSO8
8
9
8 KSO12
2
3
7
6
30 CAP_RESET UTX FANFB2/GPIO15 KSO7 9 KSO13
05/23 change to URX
30
EC_TX/GPIO16 SLP_S4# KSO4
10
10
4 5
voltage control FAN ON/OFF
31 EC_RX/GPIO17 PM_SLP_S4#/GPXID1 110
ENABLT
SLP_S4# 20
KSO2
11 11 @ 100P_1206_8P4C_50V8
30 ON/OFF CPUSB#
32
34
ON_OFF/GPIO18 ENBKL/GPXID2
112
114
ENABLT 9,17 04/04 KSI0
12
13
12
20,23 CPUSB# NUM_LED# PWR_LED#/GPIO19 GPXID3 THERM_SCI# KSO1 13
31 NUM_LED#
36
NUMLED#/GPIO1A GPI GPXID4
115 THERM_SCI# 20 14
14
CP3
EC_SUSP# KSO5 KSO2
EC DEBUG port GPXID5
116
117 EC_PWRBTN_OUT# KSI3
15
16
15 KSO4
1
2
8
7
GPXID6 KSI2 16 KSO7
GPXID7 118 17 17 3 6
1 2 C R Y2 122 KSO0 18 KSO8 4 5
CONN@
JP32 XCLK1 KSI5 18
123 XCLK0 V18R 124 19 19
1 27P_0402_50V8J KSI4 20 @ 100P_1206_8P4C_50V8
1 +5VALW 20
1

AGND

2 URX C478 KSO9 21 CP4


GND
GND
GND
GND
GND

2 UTX KSI6 21 KSI3


3 3 3 NC OUT 4 22 22 1 8
4 @ 20M_0402_5% KSI7 23 KSO5 2 7
4 R422 KB926QFB0_LQFP128_14X14 KSI1 23 KSO1
2
IN 1
24 3 6
11
24
35
94
113

69

ACES_85205-0400 NC 24 KSI0 4 5
2

Y5 32.768KHZ_12.5P_1TJS125DJ2A073
1 2 C R Y1 @ 100P_1206_8P4C_50V8
25
FOR LPC SIO DEBUG PORT 27P_0402_50V8J +3VALW_EC 26
GND1
GND2
CP5
CONN@
JP33 C479 KSI4 1 8
ECAGND

1 ACES_85201-24051 KSI5 2 7
1 +5VS
1

2 CONN@ KSO0 3 6
2 SUSP# +EC_AVCC L18 KSI2
3 +3VS 4 5
3 0_0603_5%
4
4 @ 100P_1206_8P4C_50V8
5
5
1

6 L19 SP01000FF00 85201-24051 24P P1.0


CLK_14M_DEBUG 15 CP6
2

6 LPC_AD0 R421 ACES_85201-24051_24P


7 1 2 1 2
7 LPC_AD1 100K_0402_5% C480 0_0603_5% KSI1
8 1 8
8 LPC_AD2 0.1U_0402_16V4Z KSI7
9 9 2 7
10 LPC_AD3 3 6
2

10 LPC_FRAME#
11 11 4 5
12 LPC_DRQ#0 @ R423
12 LPC_DRQ#0 19
13 PCI_RST# 10K_0402_5% @ 100P_1206_8P4C_50V8
13
14 14 2 1
15 CLK_DEBUG_PORT_1
15 SIRQ CLK_DEBUG_PORT_2 15
16
16
17 17
Security Classification Compal Secret Data Compal Electronics, Inc.
18 18 Issued Date 2006/02/13 Deciphered Date 2006/07/26 Title
19
19
20 20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC KB926/KB conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number R ev
ACES_85201-2005 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3821P 0.3
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Tuesday, July 31, 2007 Sheet 32 of 43

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