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CH11 General VLSI System Components

This document discusses various digital components used in VLSI systems, including multiplexers, decoders, comparators, encoders, rotators and shifters, latches and flip-flops, and registers. It provides logic diagrams and descriptions of common implementations of these components using transistor-level logic gates and circuits. Examples of 2:1 and 4:1 multiplexers, 2/4 decoders, 4-bit and 8-bit comparators, 8-bit priority encoders, 4-bit rotators, D latches, D flip-flops, and n-bit registers are shown across multiple pages.

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82 views30 pages

CH11 General VLSI System Components

This document discusses various digital components used in VLSI systems, including multiplexers, decoders, comparators, encoders, rotators and shifters, latches and flip-flops, and registers. It provides logic diagrams and descriptions of common implementations of these components using transistor-level logic gates and circuits. Examples of 2:1 and 4:1 multiplexers, 2/4 decoders, 4-bit and 8-bit comparators, 8-bit priority encoders, 4-bit rotators, D latches, D flip-flops, and n-bit registers are shown across multiple pages.

Uploaded by

ravi
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© © All Rights Reserved
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GENERAL VLSI SYSTEM

COMPONENTS
Dr. Mohammed M. Farag
Faculty of Engineering - Alexandria University 2013

Multiplexers

Gate-level NAND 2:1 multiplexor.


Multiplexor using switch logic.

Gate-level 4:1 MUX A 4:1 MUX using instanced 2:1 devices.


EE 432 VLSI Modeling and Design 2
Faculty of Engineering - Alexandria University 2013

Multiplexers (2)

4:1 MUX using nFET pass transistors.


Simple 4:1 pass-FET MUX layout.

EE 432 VLSI Modeling and Design 3


Faculty of Engineering - Alexandria University 2013

Multiplexers (3)

Split-array 4:1 MUX for full-rail output.

EE 432 VLSI Modeling and Design 4


Faculty of Engineering - Alexandria University 2013

Multiplexers (4)

A vector 2:1 MUX.

Single-bit cell tiling for an 8-bit 2:1 MUX.


EE 432 VLSI Modeling and Design 5
Faculty of Engineering - Alexandria University 2013

Decoders

An active-high 2/4 decoder.

EE 432 VLSI Modeling and Design 6


Faculty of Engineering - Alexandria University 2013

Decoders (2)

Active low 2/4 decoder.

EE 432 VLSI Modeling and Design 7


Faculty of Engineering - Alexandria University 2013

Comparators

a 4-bit equality detector.

8-bit equality detector.

EE 432 VLSI Modeling and Design 8


Faculty of Engineering - Alexandria University 2013

Comparators (2)

4-bit magnitude comparator logic.

Comparator output summary.

EE 432 VLSI Modeling and Design 9


Faculty of Engineering - Alexandria University 2013

Comparators (3)

Comp 8 logic diagram.

Additional logic for A_EQ_B


and Enable features.

EE 432 VLSI Modeling and Design 10


Faculty of Engineering - Alexandria University 2013

Comparators (4)

8-bit comparator system.

EE 432 VLSI Modeling and Design 11


Faculty of Engineering - Alexandria University 2013

Encoders

Symbol for priority encoder Function table for an 8-bit priority


encoder.

EE 432 VLSI Modeling and Design 12


Faculty of Engineering - Alexandria University 2013

Encoders (2)

Logic diagram for the priority encoder.

EE 432 VLSI Modeling and Design 13


Faculty of Engineering - Alexandria University 2013

Encoders (3)

Q0 and Q1 circuits for the 8-bit priority


encoder.
EE 432 VLSI Modeling and Design 14
Faculty of Engineering - Alexandria University 2013

Rotators and Shifters

General rotator.

A 4-bit rotate-right network.

EE 432 VLSI Modeling and Design 15


Faculty of Engineering - Alexandria University 2013

Rotators and Shifters (2)

Left-rotate switching array.

EE 432 VLSI Modeling and Design 16


Faculty of Engineering - Alexandria University 2013

Rotators and Shifters (3)

An 8 X 4 barrel shifter. FET-array barrel shifter.


EE 432 VLSI Modeling and Design 17
Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops

D-latch.
CMOS circuit for a D-latch.

Gated D-latch with Enable control.

AOI CMOS gate for D-latch with Enable.


EE 432 VLSI Modeling and Design 18
Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (2)

Closed-loop inverter configurations.

Operation of a bistable circuit.

EE 432 VLSI Modeling and Design 19


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (3)

Adding an input node to the bistable circuit.

D-latch using oppositely phased switches.


EE 432 VLSI Modeling and Design 20
Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (4)

Operation of the D-latch.

EE 432 VLSI Modeling and Design 21


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (5)

C2MOS-based D-latch circuits.

EE 432 VLSI Modeling and Design 22


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (6)

Master-slave D-type flip-flop.

Edge-triggered DFF symbols.

EE 432 VLSI Modeling and Design 23


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (7)

Alternate circuitry for the master-slave DFF.

EE 432 VLSI Modeling and Design 24


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (8)

DFF circuits with assert-low Clear and


Clear/Set controls.
EE 432 VLSI Modeling and Design 25
Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (9)

DFF modified to a TFF circuit using feedback.

EE 432 VLSI Modeling and Design 26


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (10)

D-type flip-flop with Load control.

EE 432 VLSI Modeling and Design 27


Faculty of Engineering - Alexandria University 2013

Latches and Flip-Flops (11)

CMOS master-slave FF
with Load control.

Operation of the CMOS DFF with load control.


EE 432 VLSI Modeling and Design 28
Faculty of Engineering - Alexandria University 2013

Registers

Construction of an n-bit register.


EE 432 VLSI Modeling and Design 29
Faculty of Engineering - Alexandria University 2013

Registers (2)

One-bit static multiport register circuit.

An n-bit static multiport register.

EE 432 VLSI Modeling and Design 30

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