Introduction to VHDL

Ying-Shieh Kung
Professor Sep. 2014 ~ Jan. 2015

Department of Electrical Engineering

Southern Taiwan University of Science and Technology
Introduction to VHDL

2
Library and Data type

LIBRARY
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;

Data type
BIT
BIT_VECTOR (3 downto 0)
STD_LOGIC
STD_LOGIC_VECTOR (3 downto 0)
INTEGER range 0 to 7

3
Data Types and Object Declarations

 Data Types and Object Declarations

The values of signals, variables, and constants can
correspond to different data TYPES, such as INTEGER,
REAL, BIT, and nonnumeric sets. VHDL has the following
classes of types:

4
Data Types and Object Declarations
 Examples of user-defined enumerated types

 Examples of user-defined array types

 A SUBTYPE is a subset of a type obtained by

constraining its range

5
Data Types and Object Declarations

 The data type of signals, variables, and constants

are specified with object declarations, which also
assign an initial value to the object.

6
VHDL statement
Conditional Signal Assignment Statement

_signal <= _expression WHEN _boolean_expression ELSE

_expression WHEN _boolean_expression ELSE
_expression;

Selected Signal Assignment Statement

_label:
WITH _expression SELECT
_signal <= _expression WHEN _constant_value,
_expression WHEN _constant_value,
_expression WHEN _constant_value,
_expression WHEN _constant_value;

7
Example-1: decoder
A 2-Line to 4-Line decoder with active-LOW enable

Truth table

Logic circuit
8
VHDL for decoder

Using Selected Signal Assignment Statement Using Conditional Signal Assignment Statement

9
Example-2: truth table
Truth table

10
Control Flow Statements

CASE Statement within a PROCESS IF Statement within a PROCESS

_process_label: _process_label:
PROCESS (sensitivity list); PROCESS (sensitivity list);
BEGIN BEGIN
CASE _expression IS IF _expression THEN
WHEN _constant_value => _statement;
_statement; _statement;
_statement; ELSIF _expression THEN
WHEN _constant_value => _statement;
_statement; _statement;
_statement; ELSE
WHEN OTHERS => _statement;
_statement; _statement;
_statement; END IF;
END CASE; END PROCESS _process_label;
END PROCESS _process_label;
11
Control Flow Statements

CASE statement, such as  IF statement, such as

CASE Data IS IF (clk = ‘1’) AND (x=‘1’)
THEN
WHEN “000” => k :=1;
z := a OR b;
WHEN “111” => k :=0; ELSIF (clk = ‘0’) THEN
WHEN others => k := k+1; z := ‘0’:
END CASE; END IF;

12
Example-3: Multiplexer
- mux4case.vhd
-- 4-to-1 multiplexer
-- Directs one of four input signals (d0 to d3) to output,
d0
-- depending on status of select bits (s1, s0).
d1
d2
y
-- Define inputs and outputs
d3 ENTITY mux4case IS
PORT(
s1 s0 d0, d1, d2, d3 : IN BIT; -- data inputs
s : IN BIT_VECTOR (1 downto 0); -- select inputs
4 to 1 MUX y : OUT BIT);
END mux4case;
ARCHITECTURE mux4to1 OF mux4case IS
BEGIN
-- Monitor select inputs and execute if they change
PROCESS (s)
s1 s0 y BEGIN
CASE s IS
0 0 d0 WHEN "00“ => y <= d0;
WHEN "01“ => y <= d1;
0 1 d1 WHEN "10“ => y <= d2;
1 0 d2 WHEN "11“ => y <= d3;
WHEN others => y <= '0';
1 1 d3
END CASE;
END PROCESS;
Truth table for a 4 to 1 MUX END mux4to1;

13
Control Flow Statements

 FOR LOOP statement,  WHILE LOOP statement,

such as such as

14
Example-4: One-bit adder

ENTITY full_add IS
PORT( a, b, c_in : IN BIT;
c_out, sum : OUT BIT); full_add
END full_add; a c_out
b sum
ARCHITECTURE adder OF full_add IS
BEGIN
c_in
c_out <= ((a xor b) and c_in) or (a and b);
sum <= (a xor b) xor c_in;
END adder;

15
Example-5: Four-bit adder
ENTITY add4gen IS add4gen
PORT( c0 : IN BIT;
full_add
a, b : IN BIT_VECTOR(4 downto 1); C(1)
c4 : OUT BIT; a(1) a c_out
b(1) b sum sum(1)
sum : OUT BIT_VECTOR(4 downto 1)); C(0)
c0 c_in
END add4gen;

ARCHITECTURE adder OF add4gen IS full_add C(2)

-- Component declaration a(2) a c_out
COMPONENT full_add b(2) b sum sum(2)
PORT( a, b, c_in : IN BIT; c_in
c_out, sum : OUT BIT);
END COMPONENT; full_add C(3)
-- Define a signal for internal carry bits a(3) a c_out
SIGNAL c : BIT_VECTOR (4 downto 0); b(3) b sum sum(3)
BEGIN c_in
c(0) <= c0;
adders: full_add
FOR i IN 1 to 4 GENERATE C(4)
a(4) a c_out c4
adder: full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i)); b(4) b sum sum(4)
END GENERATE; c_in
c4 <= c(4);
END adder;
16
Example -6: multiplier
Design a VHDL to compute
y = a*b

VHDL code
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;

library lpm;
use lpm.lpm_components.all;

entity mu is port (
a,b :in std_logic_vector(3 downto 0);
y :out std_logic_vector(7 downto 0);
clk :in std_logic );
end mu; 17

17
architecture main of mu is
signal mula,mulb : std_logic_vector( 3 downto 0);
signal mulr : std_logic_vector( 7 downto 0);
signal CNT :STD_LOGIC_VECTOR(7 downto 0);

begin
u4:lpm_mult
generic map(LPM_WIDTHA=>4, LPM_WIDTHB=>4,
LPM_WIDTHS=>4, LPM_WIDTHP=>8,
LPM_REPRESENTATION=>"signed",
lpm_pipeline=>1)
port map (dataa =>mula, datab =>mulb, result=>mulr, clock=>clk);

process(clk)
begin
IF clk='1' and clk'event THEN
CNT<=CNT+1;
IF CNT=X"00" THEN
mula <= a;
mulb <= b;
ELSIF CNT=X"01" THEN
y <= mulr;
ELSIF CNT=X"02" THEN
CNT <= X"00";
end if;
end if; 18
end process;

end main; 18
Implementation of sum-of-product
computation
 Example: Y  a1 * x1  a2 * x2  a3 * x3
 Parallel processing: a1
x1 x
+
three multipliers a2 One clock
x2 x + y
and execute time
two adders a3
x3 x

 Sequential processing using Finite State Machine (FSM):

x1
a1
one multiplier x +
a2 Five clocks
and x y execute time
one adder x3 +
x2
a3
x
s1 s2 s3 s4 s5 19
Example-7: matrix computation

Write a VHDL code to compute a matrix

 y1   A 11 A 12 A 13   x 1 
y   A A 22 A 23   x 2 
 2  21
 y 3   A 31 A 32 A 33   x 3 

Example:
23 4 2  1  40
 7 9 15 2  70
    
10 11 1  3 35
20

20
Method –1 (Parallel Computation)

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;

ENTITY matrix IS
port(CLK,CLK_40n :IN STD_LOGIC;
A11,A12,A13,A21,A22,A23 :IN STD_LOGIC_VECTOR(11 downto 0);
A31,A32,A33,X1,X2,X3 :IN STD_LOGIC_VECTOR(11 downto 0);
Y1,Y2,Y3 :OUT STD_LOGIC_VECTOR(23 downto 0)
);
END matrix;

ARCHITECTURE matrix_arch OF matrix IS

BEGIN
Y1<=A11*X1+A12*X2+A13*X3;
Y2<=A21*X1+A22*X2+A23*X3;
Y3<=A32*X1+A23*X2+A33*X3;
END matrix_arch;

 y1   A 11 A 12 A 13   x 1 
y   A A 22 A 23   x 2 
 2  21 21
 y 3   A 31 A 32 A 33   x 3 
21
Simulation result

22

22
Method –2 ELSIF CNT=X"02" THEN
addb <= mulr;
mula <= A13;
(Sequential Computation) mulb <= X3;
ELSIF CNT=X"03" THEN
LIBRARY IEEE; adda <= addr;
USE IEEE.std_logic_1164.all; addb <= mulr;
USE IEEE.std_logic_arith.all; mula <= A21;
USE IEEE.std_logic_signed.all; mulb <= X1;
LIBRARY lpm; ELSIF CNT=X"04" THEN
USE lpm.LPM_COMPONENTS.ALL; ram1 <= addr;
ENTITY matrix IS adda <= mulr;
port(CLK,CLK_40n :IN STD_LOGIC; mula <= A22;
A11,A12,A13,A21,A22,A23 :IN STD_LOGIC_VECTOR(11 downto 0); mulb <= X2;
A31,A32,A33,X1,X2,X3 :IN STD_LOGIC_VECTOR(11 downto 0); ELSIF CNT=X"05" THEN
Y1,Y2,Y3 :OUT STD_LOGIC_VECTOR(23 downto 0) addb <= mulr;
); mula <= A23;
END matrix; mulb <= X3;
ARCHITECTURE matrix_arch OF matrix IS ELSIF CNT=X"06" THEN
SIGNAL mula,mulb :STD_LOGIC_VECTOR(11 downto 0); adda <= addr;
SIGNAL mulr :STD_LOGIC_VECTOR(23 downto 0); addb <= mulr;
SIGNAL adda,addb,addr,ram1,ram2 :STD_LOGIC_VECTOR(23 downto 0); mula <= A31;
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0); mulb <= X1;
ELSIF CNT=X"07" THEN
BEGIN ram2 <= addr;
multiplier: lpm_mult adda <= mulr;
generic map(LPM_WIDTHA=>12,LPM_WIDTHB=>12,LPM_WIDTHS=>12,LPM_WI mula <= A32;
DTHP=>24,LPM_REPRESENTATION=>"signed",LPM_PIPELINE=>1) mulb <= X2;
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr); ELSIF CNT=X"08" THEN
adder: lpm_add_sub addb <= mulr;
generic map(lpm_width=>24,LPM_REPRESENTATION=>"signed",lpm_pipeline=>1) mula <= A33;
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr); mulb <= X3;
GEN:block ELSIF CNT=X"09" THEN
BEGIN adda <= addr;
PROCESS(CLK_40n) addb <= mulr;
BEGIN ELSIF CNT=X"0A" THEN
IF CLK_40n'EVENT and CLK_40n='1' THEN Y3 <= addr;
CNT<=CNT+1; Y1 <= ram1;
IF CNT=X"00" THEN Y2 <= ram2;
mula <= A11;  y  1A 11 A 12 A13   x1  CNT <= X"00";
23
y   A x 
mulb <= X1; END IF;
A A END IF;
    2
ELSIF CNT=X"01" THEN 2 21 22 23
adda <= mulr; END PROCESS;
mula <= A12;  y 3
 A 31 A 32 A 33
  x 3  END BLOCK GEN;
END matrix_arch; 23
mulb <= X2;
Simulation result

24

11 clocks 24
Q-format and fraction operation
 The bit number behind the decimal point at the binary
digital value is called the Q-format (or Q-value)

Ex. for 4 bit binary Therefore,

01.10 is Q2 We can consider
1001. is Q0 0.110 is 0.75,
1.001 is -0.875。
for 16 bits binary 0.110100000000000 is 0.8125，
0.110011001111010 is Q15 1110.110000000000 is -1.25。
0110.011001111010 is Q12

Actually, the decimal point does not exist in the binary system.

25
Multiplication technique for Fixed-point
Fractions Integers
Decimal Binary Decimal
Q3 -0.875 1001 -7 Q0
x Q3 x 0.375 0011 x 3 x Q0

Q6 -0.328125 11101011 -21 Q0

-0.375 11.101011 11101011 -5(Error)

 Q: refers to the number of place to the right of the point.

 Multiplying number, the Q values add.

26
Binary Fractions
 To use fractions, it necessary to describe them as integers
Fractional 16-bit integer
+1 +32K ( 7FFFH )
+1/2 +16K ( 4000H )
0 0
-1/2 -16K ( C000H )
-1 -32K ( 8000H )
 By multiplying a fraction by 32K(32768), a normalized fraction is created

Example 1 :
 To represent 0.62 : 62 x 32768 / 100 = 20316
 To represent 0.1405: 1405 x 32768 / 10000 = 4604

27
Binary / Fractions transformation
using Matlab

Hint: (in Matlab) signed

format hex 16 bits
Q15
fi(0.1,1,16,15) Result : X”0CCD”
fi(-0.4525,1,16,15) Result : X”C614”
fi(0.2001,1,16,15) Result : X”199D”
24 bits
fi(0.1,1,24,15) Result : X”000CCD”
fi(-0.4525,1,24,15) Result : X”ff199D”
fi(0.2001,1,24,15) Result : X”00199D”
fi(1.5,1,24,15) Result : X”00C000”
fi(-1.5,1,24,15) Result : X”FF4000”
Example -8: sum of product

Design a VHDL to compute

Y = A0*X0+A1*X1+A2*X2

Let
A0 =0.1 ; 0.1*32768= 3277= X"0CCD";
A1 = 0.2001 ; 0.2001*32768= 6557= X"199D";
A2 =-0.4525 ; -0.4525*32768= -14828 = X"C614";
X0=0.2001 ; 0.2001*32768= 6557= X"199D";
X1=0.2001 ; 0.2001*32768= 6557= X"199D";
X2=0.1 ; 0.1*32768= 3277= X"0CCD";

Therefore Y=0.01479 ; 0.01479*32768=484= X“1E4";

29
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;

ENTITY STEP IS
port (CLK,CLK_40n : IN STD_LOGIC;
X0,X1,X2 : IN STD_LOGIC_VECTOR(15 downto 0);
Y : OUT STD_LOGIC_VECTOR(15 downto 0)
);
END STEP;

ARCHITECTURE STEP_arch OF STEP IS

SIGNAL A0,A1,A2 :STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mula,mulb :STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mulr :STD_LOGIC_VECTOR(31 downto 0);
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0);
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0);

BEGIN
mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
LPM_REPRESENTATION=>"signed",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"signed",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);

30
--Q15
A0 <= X"0CCD";-- 3277 (0.1*32768)
A1 <= X"199D";-- 6557 (0.2001*32768)
A2 <= X"C614";-- -14828 (-0.4525*32768)

GEN:block
BEGIN
PROCESS(CLK_40n)
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN
CNT<=CNT+1;
IF CNT=X"00" THEN
mula <= A0;
mulb <= X0;
ELSIF CNT=X"01" THEN
adda <= mulr(30 downto 15);
mula <= A1;
mulb <= X1;
ELSIF CNT=X"02" THEN
addb <= mulr(30 downto 15);
mula <= A2;
mulb <= X2;
ELSIF CNT=X"03" THEN
adda <= addr;
addb <= mulr(30 downto 15);
ELSIF CNT=X"04" THEN
Y <= addr;
CNT <= X"00";
END IF;
END IF;
END PROCESS;
END BLOCK GEN;

END STEP_arch; 31
Simulation results in Quartus II

32
Simulation results in ModelSim

X“01E4"
33
Case study for Computing SoP
Design a VHDL to compute
Y = A0*X0+A1*X1+A2*X2

Case-1 : Computing SoP with16bit Q0

(for integer computation)

Case-2 : Computing SoP with16bit Q15

(for fraction computation but the result less than  1)

Case-3 : Computing SoP with 24bit Q15

(for fraction computation but the result less than  256)

34
Case-1 xxxxxxxxxxxxxxxx 16bit Q0
x xxxxxxxxxxxxxxxx 16bit Q0
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
15:0 16bit Q0
error
Case-2 x.xxxxxxxxxxxxxxx 16bit Q15
x x.xxxxxxxxxxxxxxx 16bit Q15
xx.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
error 30:15 error
16bit Q15

Case-3 xxxxxxxxx.xxxxxxxxxxxxxxx 24bit Q15

x xxxxxxxxx.xxxxxxxxxxxxxxx 24bit Q15
xxxxxxxxxxxxxxxxxx.xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
error 38:15 error
24bit Q15
Case-1: VHDL code for SoP (Sum of Product) with16bit Q0

LIBRARY IEEE; GEN:block

USE IEEE.std_logic_1164.all; BEGIN
USE IEEE.std_logic_arith.all; PROCESS(CLK_40n)
USE IEEE.std_logic_signed.all; BEGIN
LIBRARY lpm; IF CLK_40n'EVENT and CLK_40n='1' THEN
USE lpm.LPM_COMPONENTS.ALL; CNT<=CNT+1;
ENTITY SoP_16Q0 IS IF CNT=X"00" THEN
Port (CLK,CLK_40n : IN STD_LOGIC:='0'; mula<=A1;
X1, X2, X3 : IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); mulb<=X1;
A1, A2, A3 : IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); ELSIF CNT=X"01" THEN
Y : OUT STD_LOGIC_VECTOR(15 downto 0):=(others =>'0‘) adda<=mulr(15 downto 0);
); mula<=A2;
END SoP_16Q0; mulb<=X2;
ELSIF CNT=X"02" THEN
ARCHITECTURE SoP_arch OF SoP_16Q0 IS addb<=mulr(15 downto 0);
SIGNAL mula,mulb :STD_LOGIC_VECTOR(15 downto 0):=(others mula<=A3;
=>'0'); mulb<=X3;
SIGNAL mulr :STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); ELSIF CNT=X"03" THEN
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); adda<=addr;
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0):=(others =>'0'); addb<=mulr(15 downto 0);
ELSIF CNT=X"04" THEN
BEGIN Y <=addr;
mull: lpm_mult CNT <=X"00";
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32, END IF;
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1) END IF;
port map(dataa=> mula,datab=>mulb,clock=> clk,result=> mulr); END PROCESS;
END BLOCK GEN;
adder1: lpm_add_sub END SoP_arch;
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);

36
Co-Simulation result for SoP with16bit Q0

fixdt(1,16,0)
O: unsigned
1: signed
Q format (Q0)
data length (16bits)

37
Case-2: VHDL code for SoP (Sum of Product) with16bit Q15

LIBRARY IEEE; GEN:block

USE IEEE.std_logic_1164.all; BEGIN
USE IEEE.std_logic_arith.all; PROCESS(CLK_40n)
USE IEEE.std_logic_signed.all; BEGIN
LIBRARY lpm; IF CLK_40n'EVENT and CLK_40n='1' THEN
USE lpm.LPM_COMPONENTS.ALL; CNT<=CNT+1;
ENTITY SoP_16Q15 IS IF CNT=X"00" THEN
Port (CLK,CLK_40n : IN STD_LOGIC:='0'; mula<=A1;
X1, X2, X3 : IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); mulb<=X1;
A1, A2, A3 : IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); ELSIF CNT=X"01" THEN
Y : OUT STD_LOGIC_VECTOR(15 downto 0):=(others =>'0') adda<=mulr(30 downto 15);
); mula<=A2;
END SoP_16Q15; mulb<=X2;
ELSIF CNT=X"02" THEN
ARCHITECTURE SoP_arch OF SoP_16Q15 IS addb<=mulr(30 downto 15);
SIGNAL mula,mulb :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); mula<=A3;
SIGNAL mulr :STD_LOGIC_VECTOR(31 downto 0):=(others =>'0'); mulb<=X3;
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'); ELSIF CNT=X"03" THEN
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0):=(others =>'0'); adda<=addr;
addb<=mulr(30 downto 15);
BEGIN ELSIF CNT=X"04" THEN
mull: lpm_mult Y <=addr;
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32, CNT <=X"00";
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1) END IF;
port map(dataa=> mula,datab=>mulb,clock=> clk,result=> mulr); END IF;
END PROCESS;
adder1: lpm_add_sub END BLOCK GEN;
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1) END SoP_arch;
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);

38
Co-Simulation result for SoP with16bit Q15

fixdt(1,16,15)
O: unsigned
1: signed
Q format (Q15)
data length (16bits)

function y = fcn(x1,x2,x3,a1,a2,a3) 39
y=a1*x1+a2*x2+a3*x3
Case-3: VHDL code for SoP (Sum of Product) with 24bit Q15

LIBRARY IEEE; GEN:block

USE IEEE.std_logic_1164.all; BEGIN
USE IEEE.std_logic_arith.all; PROCESS(CLK_40n)
USE IEEE.std_logic_signed.all; BEGIN
LIBRARY lpm; IF CLK_40n'EVENT and CLK_40n='1' THEN
USE lpm.LPM_COMPONENTS.ALL; CNT<=CNT+1;
ENTITY SoP_24Q15 IS IF CNT=X"00" THEN
Port (CLK,CLK_40n : IN STD_LOGIC:='0'; mula<=A1;
X1, X2, X3 : IN STD_LOGIC_VECTOR(23 downto 0):=(others =>'0'); mulb<=X1;
A1, A2, A3 : IN STD_LOGIC_VECTOR(23 downto 0):=(others =>'0'); ELSIF CNT=X"01" THEN
Y : OUT STD_LOGIC_VECTOR(23 downto 0):=(others =>'0') adda<=mulr(38 downto 15);
); mula<=A2;
END SoP_24Q15; mulb<=X2;
ELSIF CNT=X"02" THEN
ARCHITECTURE SoP_arch OF SoP_24Q15 IS addb<=mulr(38 downto 15);
SIGNAL mula,mulb :STD_LOGIC_VECTOR(23 downto 0):=(others =>'0'); mula<=A3;
SIGNAL mulr :STD_LOGIC_VECTOR(47 downto 0):=(others =>'0'); mulb<=X3;
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(23 downto 0):=(others =>'0'); ELSIF CNT=X"03" THEN
SIGNAL CNT :STD_LOGIC_VECTOR(7 downto 0):=(others =>'0'); adda<=addr;
addb<=mulr(38 downto 15);
BEGIN ELSIF CNT=X"04" THEN
mull: lpm_mult Y <=addr;
generic map(LPM_WIDTHA=>24,LPM_WIDTHB=>24,LPM_WIDTHS=>24,LPM_WIDTHP=>48, CNT <=X"00";
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1) END IF;
port map(dataa=> mula,datab=>mulb,clock=> clk,result=> mulr); END IF;
END PROCESS;
adder1: lpm_add_sub END BLOCK GEN;
generic map(lpm_width=>24,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1) END SoP_arch;
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);

40
Co-Simulation result for SoP with 24bit Q15

fixdt(1,24,15)
O: unsigned
1: signed
Q format (Q15)
data length (24bits)

function y = fcn(x1,x2,x3,a1,a2,a3) 41
y=a1*x1+a2*x2+a3*x3
Homework-1
1. Write a VHDL code (16bitsQ15) to compute the
following polynomial equation.
Homework format :
x3 x5 x7
y  sin( x)  x    (word file)
3! 5! 7!
1. Topic
and x=0.1, 0.2, 0.3, 0.4 2. Technique description
3. VHDL code
Hint: (in Matlab) signed 4. Simulation result
format hex 16 bits
Q15 5. Discussion
fi(1/(3*2),1,16,15)
fi(1/(5*4*3*2),1,16,15) Result : X”0111”
fi(1/(7*6*5*4*3*2),1,16,15)

42
Homework-1

2. Write a VHDL code (24bitsQ15) to compute the exponential function.

 x2 / 2
ye with  1  x  1 and 0.4    1

and let x= -0.9,-0.8,…,-0.1, 0, 0.1, 0.2.. , 0.8, 0.9.

Due date: Oct. 28 (Monday) (Every student need to prepare a presentation in class)
Homework (ppt file) has to send to my_digital_learning.
43
Topic-2 : Matlab simulation
clear;  x2 / 2
s=0.4; ye  eu
ma=20; % order
u2 u3 um
xx=-1:0.01:1;  1  u    ... 
xi=length(xx) 2! 3! m!
for i=1:xi
x=-xx(i)^2/s^2; Good Bad
1 1.2
y1(i)=exp(x); 0.9
1
mi=1; 0.8

y=1; 0.7 0.8

0.6
for m=1:ma 0.6

mi=mi*m;
0.5

0.4 m=20, =0.4 0.4 m=15, =0.4

y=y+x^m/mi; 0.3 0.2

end; 0.2
0
0.1
y2(i)=y; -0.2
0 -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1
end; -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

plot(xx,y1,xx,y2)
Transfer function response
with step input
plant
x(s) 2n
連續系統 y(s)
s 2  2n s  2n
Continuous system
n  10,   0.5
t samp  0.01s

plant

數位系統 x(n) a 0  a 1z 1  a 2 z 2
y(n)
1  b1z 1  b 2 z  2
Digital system
a0 = 0.002575，a1=0.00485，
a2=0.002575，b1=-1.895，b2=0.905

If x(n)=0.5 (Q15:16384) , find the response of y(n)?

45
clear;clf;format long;
za=0.5; Step Response
1.4
wn=10;
num=wn^2; 1.2

den=[1,2*za*wn,wn^2]; 1
S1=tf(num,den)
D1=c2d(S1,0.01,'tustin') 0.8

Amplitude
step(S1) 0.6

Pause
0.4

% 0.2

numd=[0.002575,0.00485,0.002575];
0
dend=[1,-1.895,0.905]; 0 20 40 60 80 100 120
Time (samples)
Dstep(numd,dend)
Transfer response with step input
Digital system

1 Y ( z 1 ) a 0  a 1 z 1  a 2 z 2
G (z )  1

X (z ) 1  b 1 z 1  b 2 z  2
The difference equation:

y(n) = - b1*y(n-1)- b2*y(n-2)+ a0 *x(n)+ a1*x(n-1)+ a2*x(n-2)

=1.895*y(n-1)-0.905*y(n-2)+0.002575*x(n)+
0.00485*x(n-1)+ 0.002575*x(n-2)
To avoid overflow occurred, reformulate it as

y(n)/2= 0.9475*y(n-1)-0.4525* y(n-2)+ 0.0012875*x(n)

+ 0.002425*x(n-1)+ 0.0012875*x(n-2)
Transfer to 16-bit Q15 format:
y(n)/2= 31048*y(n-1)-14828*y(n-2)+42*x(n)
+ 80*x(n-1)+42*x(n-2)

47
Transfer response with step input
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
Use IEEE.numeric_std.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY STEP IS
port(CLK,CLK_40n :IN STD_LOGIC:='0';
X0 :IN STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0):=(others =>'0'));
END STEP;

ARCHITECTURE STEP_arch OF STEP IS

SIGNAL A0,A1,A2,B1,B2 :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL Y2,Y1,X1,X2 :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL Yn1 :STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
SIGNAL mula,mulb :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL mulr :STD_LOGIC_VECTOR(31 downto 0):=(others =>'0');
SIGNAL adda,addb,addr :STD_LOGIC_VECTOR(15 downto 0):=(others =>'0');
SIGNAL CNT :STD_LOGIC_VECTOR(19 downto 0):=(others =>'0');
BEGIN

mull: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
--Q15
A0 <= X"002A";--42 (0.00128)
A1 <= X"0050";--80 (0.00244)
A2 <= X"002A";--42 (0.00128)
B1 <= X"7948";--31048 (0.94754)
B2 <= X"C614";---14828 (-0.4525) 48
Transfer response with step input
GEN:block ELSIF CNT=X"05" THEN
BEGIN adda <= addr;
PROCESS(CLK_40n) addb <= mulr(30 downto 15);
BEGIN
IF CLK_40n'EVENT and CLK_40n='1' THEN ELSIF CNT=X"06" THEN
CNT<=CNT+1; Yn <= (addr(15) & addr(13 downto 0) & '0');
ELSIF CNT=X"07" THEN
IF CNT=X"00" THEN Y1 <= Yn;
mula <= A0; Y2 <= Y1;
mulb <= X0; X2 <= X1;
ELSIF CNT=X"01" THEN X1 <= X0;
adda <= mulr(30 downto 15); ELSIF CNT=250000 THEN
mula <= A1; CNT <= X"00000";
mulb <= X1; END IF;
ELSIF CNT=X"02" THEN END IF;
addb <= mulr(30 downto 15); END PROCESS;
mula <= A2; END BLOCK GEN;
mulb <= X2; END STEP_arch;
ELSIF CNT=X"03" THEN
adda <= addr;
addb <= mulr(30 downto 15);
mula <= B1;
mulb <= Y1; mulr(30..0)
ELSIF CNT=X"04" THEN
A0
X + + + + Yn
adda <= addr; mulr(30..0) mulr(30..0) mulr(30..0) mulr(30..0) addr(15) &
addb <= mulr(30 downto 15); A1
X addr(13..0)
mula <= B2; X0 A2 B1 B2 & '0'
X X X
mulb <= Y2;
X1 Yn =>Y2;
1 X1 =>X2;
X2 Yn Y2 X0 =>x1;

S 0 S1 S2 S3 S 4 S5 S6 S7 S8 S9 S10 S11 S12

49
50
Homework-2 (for 2013)
Filter design
A second-order low-pass filter is designed with Bandwidth 5Hz and damping ratio 1.0
The continuous transfer function of the second order low pass filter is
986
G2(s)= --------------------------
s^2 + 62.8 s + 986

And its fourth order low pass filter is

9.721*10^5
G4(s)= G2(s)*G2(s)= ------------------------------------------------------------------------------
s^4 + 125.6 s^3 + 5916 s^2 + 1.238*10^5 s + 9.721*10^5

After the bilinear transform with sampling time 0.01, its discrete transfer function is

0.0003391 z^4 + 0.001356 z^3 + 0.002034 z^2 + 0.001356 z + 0.0003391

G4(z)= -------------------------------------------------------------------------------------------------
z^4 - 2.914 z^3 + 3.185 z^2 -1.547 z + 0.2818

Difference equation after Q15 format: (y(n)*32768/4, or x(n)*32768/4)

y(n)/4 = 23871*y(n-1)-26092*y(n-2)+12673*y(n-3)-2305*y(n-4)+3*x(n)+11*x(n-1)
+17*x(n-2)+11*x(n-3)+3*x(n-4)

Where x(n) is inputs and y is outputs.

Filter design
Co-simulation using ModelSim/Simulink

53
Scope-2 Scope-4

Scope-1 Scope
54
Homework format :
Due date: Dec. 2 (Monday)
(ppt file) (Every student need to prepare a presentation in class)
1. Topic
2. Technique description
Homework (ppt file) needs to be submitted from the
website of my_digital_learning.
3. VHDL code
4. Simulation result
5. Discussion
PI controller design
Parallel processing :
PI controller 16
e1
up(n) Ki 16 × ui
Kp mulr1(30..15)

ui 16 ＋ 16
＋ Yn
Xn(n) e(n) 1 + Yn(n)
+ Ki z ui(n) + e1 mulr1(30..15)
Xn 16 e
1
- 1 z -feed 16 ＋ 16
16 × up
Kp
feed Sequential processing using
Finite State Machine (FSM)
 PI controller :
u p (n)  K p e(n) mulr1(30..15)
e1 ui
ui (n)  ui (n - 1)  K i e(n - 1)
X + + Yn
e1
Ki ui up
Yn(n)  u p (n)  ui (n) Xn e mulr1(30..15)
+ X
 ui ( n  1 )  K p e( n )  K i e( n  1 )
-feed Kp

S0 S1 S 2 S3 S4 S5 S6 S 7 S8 S 9 S10

using one multiplier and one adder 56

LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
PI USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;

controller LIBRARY lpm;

USE lpm.LPM_COMPONENTS.ALL;
ENTITY PI_ctrl IS
(VHDL) port(
CLK :IN STD_LOGIC;
Xn,Kp,Ki :IN STD_LOGIC_VECTOR(15 downto 0);
feed :IN STD_LOGIC_VECTOR(15 downto 0);
Yn :BUFFER STD_LOGIC_VECTOR(15 downto 0)
);
END PI_ctrl;
ARCHITECTURE PI_arch OF PI_ctrl IS
SIGNAL F,angle : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL e1,Un : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mula1,mulb1 : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL mulr1 : STD_LOGIC_VECTOR(31 downto 0);
SIGNAL adda1,addb1,addr1 : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL ui : STD_LOGIC_VECTOR(15 downto 0);
SIGNAL CNT : STD_LOGIC_VECTOR(15 downto 0);
BEGIN
mull: lpm_mult
generic
map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
LPM_REPRESENTATION=>"signed",LPM_PIPELINE=>1)
port map(dataa=> mula1,datab=> mulb1,clock=> clk,result=> mulr1);
adder1: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"signed",lpm_pipeline=>1)
port map(dataa=>adda1,datab=>addb1,clock=> clk,result=>addr1);
57
GEN:block
BEGIN
PROCESS(CLK) Sequential processing using
BEGIN Finite State Machine (FSM)
IF CLK'EVENT and CLK='1' THEN
CNT<=CNT+1;
IF CNT=X"0000" THEN
mula1 <= e1; mulr1(30..15)
mulb1 <= Ki; e1 ui
X + + Yn
ELSIF CNT=X"0002" THEN
e1
adda1 <= mulr1(30 downto 15);
Ki ui
addb1 <= ui; mulr1(30..15)
Xn e
ELSIF CNT=X"0004" THEN + X
ui <= addr1;
adda1 <= Xn; -feed Kp
addb1 <= -feed;
ELSIF CNT=X"0006" THEN S0 S1 S 2 S3 S4 S5 S6 S 7 S8 S 9 S10
e1 <= addr1;
mula1 <= addr1;
mulb1 <= Kp;
ELSIF CNT=X"0008" THEN  PI controller :
adda1 <= mulr1(30 downto 15);
addb1 <= ui; u p (n)  K p e(n)
ELSIF CNT=X"000A" THEN
Yn <= addr1; ui (n)  ui (n - 1)  K i e(n - 1)
ELSIF CNT>X"61A6" THEN --2kHz
CNT <= X"0000"; Yn(n)  u p (n)  ui (n)
END IF;
END IF;
 ui ( n  1 )  K p e( n )  K i e( n  1 )
END PROCESS;
END BLOCK GEN;
END PI_arch;
58
59
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
ENTITY PI IS
port( clk :IN STD_LOGIC:='0';
Xn :IN STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
feed :IN STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
Kp,Ki :IN STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
test1,test2, test3 :OUT STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
Yn :OUT STD_LOGIC_VECTOR(15 downto 0):=(others=>'0'));
END PI;

ARCHITECTURE PI_PLANT of PI IS
SIGNAL e1 : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mula,mulb : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL mulr : STD_LOGIC_VECTOR(31 downto 0):=(others=>'0');
SIGNAL adda,addb,addr : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL ui : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL error : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
SIGNAL CNT : STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');
BEGIN

mul: lpm_mult
generic map(LPM_WIDTHA=>16,LPM_WIDTHB=>16,LPM_WIDTHS=>16,LPM_WIDTHP=>32,
LPM_REPRESENTATION=>"SIGNED",LPM_PIPELINE=>1)
port map(dataa=> mula,datab=> mulb,clock=> clk,result=> mulr);
adder: lpm_add_sub
generic map(lpm_width=>16,LPM_REPRESENTATION=>"SIGNED",lpm_pipeline=>1)
port map(dataa=>adda,datab=>addb,clock=> clk,result=>addr);
60
PROCESS(CLK)
BEGIN
IF CLK'EVENT and CLK='1' THEN
CNT<=CNT+1;
IF CNT=X"0000" THEN
mula <= e1;
mulb <= Ki;
ELSIF CNT=X"0002" THEN
adda <= mulr(30 downto 15);
addb <= ui;
ELSIF CNT=X"0004" THEN
ui <= addr;
adda <= Xn;
addb <= -feed;
ELSIF CNT=X"0006" THEN
e1 <= addr;
mula <= addr;
mulb <= Kp;
ELSIF CNT=X"0008" THEN
adda <= mulr(30 downto 15);
addb <= ui;
ELSIF CNT=X"000A" THEN
Yn <= addr;
ELSIF CNT=2500 THEN -- 100hz
test1 <= e1;
test2 <= mulr(30 downto 15);
test3 <= ui;
CNT <= X"0000";
END IF;
END IF;
END PROCESS;
END PI_PLANT;
61
Kp=0.7, Ki=0.04

Kp=0.7, Ki=0.03

62
library ieee;
VHDL for a ROM chip use ieee.std_logic_1164.all;
using logic gates
entity rom16x7 is
port( address : IN INTEGER range 0 to 15;
data : OUT std_logic_vector (6 downto 0));
end rom16x7;

architecture sevenseg of rom16x7 is

type rom_array is array (0 to 15) of
std_logic_vector (6 downto 0);
constant rom : rom_array := (“1110111”,
“0010010”,
“1011101”,
“1011011”,
“0111010”,
“1101011”,
“1101111”,
“1010010”,
“1111111”,
“1111011”,
“1101101”,
“1101101”,
“1101101”,
“1101101”,
“1101101”,
“1101101”);
begin
data <= rom(address);
end sevenseg;

63
VHDL for a ROM chip
using RAM in FPGA
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
LIBRARY lpm;
USE lpm.LPM_COMPONENTS.ALL;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_signed.all;

ENTITY new_array IS
PORT(clk : in std_logic;
inaddress : in std_logic_vector(7 downto 0);
data : out std_logic_vector(7 downto 0));
end new_array;

ARCHITECTURE new_array_arch OF new_array IS

signal data1 : STD_LOGIC_vector(7 downto 0);
begin
u1: lpm_rom
GENERIC MAP(lpm_width => 8, lpm_widthad => 8, lpm_file => "array.mif",
lpm_address_control => "registered", lpm_outdata => "unregistered")
PORT MAP(ADDRESS => inaddress, inclock => clk, q => data1);

Process(clk)
begin
if clk'event and clk='1' then
data <= data1;
end if;
end process;
end new_array_arch;

64
Simulation results

65
LIBRARY work;
Microcontroller design USE work.all; micro.vhd
In Chapter 14. LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
---------------------------------------------------------------------------------------------------
-Input and Output Define\
----------------------------------------------------------------------------------------------------
entity micro is
port(
start : in std_logic;
x_in : in signed(7 downto 0);
z_out : out signed(7 downto 0);
done : out std_logic;
clk : in std_logic );
end micro;
---------------------------------------------------------------------------------------------------
--------- External Function Define
---------------------------------------------------------------------------------------------------
ARCHITECTURE structural OF micro IS
component microdata IS
PORT( x_in : IN SIGNED(7 DOWNTO 0);
fld_a, fld_b, fld_c : IN UNSIGNED(2 DOWNTO 0);
alu_op : IN UNSIGNED(1 DOWNTO 0);
ldr_in, ldr_out, selr_in : IN STD_LOGIC;
ldrf : IN STD_LOGIC;
zero, neg, cy :: OUT STD_LOGIC;
z_out : OUT SIGNED(7 DOWNTO 0);
clk : IN STD_LOGIC;
control_con : in STD_LOGIC
);
END component; 66
component microctrl IS
PORT(
start,zero,neg,cy : IN STD_LOGIC;
fld_a,fld_b,fld_c : OUT UNSIGNED(2 DOWNTO 0);
alu_op : OUT UNSIGNED(1 DOWNTO 0);
ldr_in,ldr_out : OUT STD_LOGIC;
selr_in,ldrf,done : OUT STD_LOGIC;
clk : IN STD_LOGIC;
control_con : out STD_LOGIC
);
END component;
---------------------------------------------------------------------------------------------------
----- Parameter Define
---------------------------------------------------------------------------------------------------
-- system parameter --
signal fld_a, fld_b, fld_c : unsigned(2 downto 0);
signal alu_op : unsigned(1 downto 0);
signal zero, neg, cy : std_logic;
signal ldr_in, ldr_out : std_logic;
signal selr_in, ldrf : std_logic;
signal control_con : std_logic;
---------------------------------------------------------------------------------------------------
----- Main Program
---------------------------------------------------------------------------------------------------
begin
u1: microdata
port map(x_in, fld_a, fld_b, fld_c, alu_op, ldr_in, ldr_out, selr_in, ldrf, zero, neg, cy, z_out, clk, control_con);
u2: microctrl
port map(start, zero, neg, cy, fld_a, fld_b, fld_c, alu_op, ldr_in, ldr_out, selr_in, ldrf, done, clk, control_con);
end structural ;

67
--microdata -------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all; microdata.vhd
USE ieee.std_logic_arith.all;
-------------------------------------------------------------------------
ENTITY microdata IS
PORT( x_in : IN SIGNED(7 DOWNTO 0);
fld_a, fld_b, fld_c : IN UNSIGNED(2 DOWNTO 0);
alu_op : IN UNSIGNED(1 DOWNTO 0);
ldr_in, ldr_out, selr_in : IN STD_LOGIC;
ldrf : IN STD_LOGIC;
zero, neg, cy : OUT STD_LOGIC;
z_out : OUT SIGNED(7 DOWNTO 0);
clk : IN STD_LOGIC;
control_con : IN STD_LOGIC );
END microdata;
-------------------------------------------------------------------------
ARCHITECTURE behavioral OF microdata IS
TYPE reg_fileT IS ARRAY(0 TO 7) OF SIGNED(7 DOWNTO 0);
SIGNAL RF : reg_fileT;
SIGNAL r_in : SIGNED(7 DOWNTO 0);
BEGIN
PROCESS (clk)
VARIABLE A,B,C : SIGNED(7 DOWNTO 0);
VARIABLE alu_out : SIGNED(7 DOWNTO 0);
VARIABLE zzero,nneg,ccy : STD_LOGIC;
-------------------------------------------------------------------------
procedure alu (
zzero,nneg,ccy : out STD_LOGIC;
alu_out : out SIGNED(7 DOWNTO 0);
a,b : in SIGNED(7 DOWNTO 0);
alu_op : in UNSIGNED(1 DOWNTO 0)
) is
variable alu_out_reg : SIGNED(8 DOWNTO 0); 68
begin
case alu_op is
when "00" => alu_out_reg := ("0" & a) + ("0" & b);
alu_out := alu_out_reg(7 downto 0);
ccy := alu_out_reg(8);
when "01" => alu_out :=a-b;
-- when "10" => alu_out_reg :=("0" & a) xor ("0" & b);
when "11" => alu_out :=a+1;
when others => null;
end case;
end alu;
-------------------------------------------------------------------------
BEGIN
A := RF(CONV_INTEGER(fld_a));
B := RF(CONV_INTEGER(fld_b));

if control_con='0' then
alu(zzero,nneg,ccy,alu_out,A,B,alu_op);
zero <= zzero;
neg <= nneg;
cy <=ccy;
end if;

IF(selr_in = '0') THEN C := alu_out;

ELSE C := r_in;
END IF;

IF(clk'EVENT AND clk = '1') THEN

IF(ldr_in = '1') THEN r_in <= x_in ; END IF;
IF(ldr_out = '1') THEN z_out <= alu_out ; END IF;
IF(ldrf = '1') THEN RF(CONV_INTEGER(fld_c)) <= C ; END IF;
END IF;
END PROCESS;
END behavioral; 69
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; microctrl.vhd
USE ieee.std_logic_arith.ALL;
USE ieee.std_logic_unsigned.ALL;
-------------------------------------------------------------------------
ENTITY microctrl IS
GENERIC(cssize : NATURAL := 12);
PORT(
start,zero,neg,cy : IN STD_LOGIC;
fld_a,fld_b,fld_c : OUT UNSIGNED(2 DOWNTO 0);
alu_op : OUT UNSIGNED(1 DOWNTO 0);
ldr_in,ldr_out : OUT STD_LOGIC;
selr_in,ldrf,done : OUT STD_LOGIC;
clk : IN STD_LOGIC;
control_con : out STD_LOGIC );
END microctrl;
-------------------------------------------------------------------------
ARCHITECTURE behav_microprogr OF microctrl IS
SIGNAL csar : NATURAL;
SIGNAL uinstr : UNSIGNED(17 DOWNTO 0);
ALIAS mode : STD_LOGIC IS uinstr(17);
ALIAS condition : UNSIGNED(1 DOWNTO 0) IS uinstr(16 DOWNTO 15);
ALIAS cond_val : STD_LOGIC IS uinstr(14);
BEGIN

70
PROCESS (clk)
VARIABLE index : UNSIGNED(13 DOWNTO 0);
BEGIN
IF (clk'EVENT AND clk = '1') THEN
IF (mode = '0') THEN csar <= csar+1;
ELSE
CASE condition IS
WHEN "00" => IF (start = cond_val) THEN
index := uinstr(13 DOWNTO 0);
csar <= CONV_INTEGER(index);
ELSE csar <= csar+1;
END IF;
WHEN "01" => IF (zero = cond_val) THEN
index := uinstr(13 DOWNTO 0);
csar <= CONV_INTEGER(index);
ELSE csar <= csar+1;
END IF;
WHEN "10" => IF (neg = cond_val) THEN
index := uinstr(13 DOWNTO 0);
csar <= CONV_INTEGER(index);
ELSE csar <= csar+1;
END IF;
WHEN "11" => IF (cy = cond_val) THEN
index := uinstr(13 DOWNTO 0);
csar <= CONV_INTEGER(index);
ELSE csar <= csar+1;
END IF;
WHEN OTHERS => NULL;
END CASE;
END IF;
END IF;
END PROCESS;
-------------------------------------------------------------------------
71
-- Continued in the next figure.--
PROCESS(csar)
TYPE csarray IS ARRAY(0 TO cssize-1) OF UNSIGNED(17 DOWNTO 0);
VARIABLE cs : csarray
-- Here the microprogram as initial contents of ARRAY cs--
:= (0 => "001000000000100010",
1 => "100000000000000001",
2 => "011000000011110001",
3 => "000000000010100100",
4 => "001000000111100000",
5 => "000010010010100010",
6 => "111000000000001000",
7 => "011111000111100000",
8 => "000011011011100000",
9 => "111000000000000101",
10 => "000111000111101000",
11 => "111000000000000000");
-----------------------------------------------------------------------
BEGIN
uinstr <= cs(csar);
control_con <= uinstr(17);
CASE uinstr(17) IS
WHEN '0' => alu_op <= uinstr(16 DOWNTO 15);
fld_a <= uinstr(14 DOWNTO 12);
fld_b <= uinstr(11 DOWNTO 9);
fld_c <= uinstr( 8 DOWNTO 6);
ldrf <= uinstr(5); ldr_out <= uinstr(3);
ldr_in <= uinstr(4); selr_in <= uinstr(2);
IF (uinstr(1) = '1') THEN done <= '1'; END IF;
IF (uinstr(0) = '1') THEN done <= '0'; END IF;
WHEN '1' => ldrf <= '0'; ldr_out <= '0'; ldr_in <= '0';
WHEN OTHERS => NULL;
END CASE;
END PROCESS; 72
END behav_microprogr;
Final-homework ModelSim

(for 2013) PID controller

up(n) SimuLink
1. Design a simple processor Kp
plant
(CPU) +
+
e(n) K i z 1 ui(n) + u(n) z  1
2. Use this CPU to design x(n) Plant y(n)
1  z 1 1  z 1
the PID controller by - +

software. ud(n)
K d (1  z 1 )
3. simulate it using ModelSim
and SimuLink environment.
Fig.1
Y (s)  n2
Plant: G (s)   2
U (s) s  2  n s   n2
with n  10,   0.5
U ( z 1 ) K i z 1
PID controller: 1
 K  1
 K d (1  z 1 )
1 z
p
E(z )

or u p (n)  K p e(n) u d (n)  K d (e(n) - e(n - 1))

Presentation date:
Jan. 6, 2014 u i (n)  u i (n - 1)  K i e(n - 1)
u(n)  u p (n)  u i (n)  u d (n)
 u i (n  1)  K p e(n )  K i e(n  1)  K d (e(n )  e(n  1))

error: e(n) = x(n)-y(n) Input: x(n) is step command with 0.5 magnitude
73
For your
reference