1.3.

Timing Diagram

Dr.M.N.Vimal Kumar,B.E.,M.E.,Ph.D
Associate Professor
Department of Mechatronics Engineering,
Sona College of Technology
Salem - 636005

1
Timing Diagram of 8085 Microprocessor
 Timing Diagram is a graphical representation.

 It represents the execution time taken by each instruction in a graphical format.

 The execution time is represented in T-states.

Instruction Cycle:
 The time required to execute an instruction is called instruction cycle.
Machine Cycle:

 The time required to access the memory or input/output devices is called machine cycle.

T-State:

 The machine cycle and instruction cycle takes multiple clock periods.

 A portion of an operation carried out in one system clock period is called as T-state.
MACHINE CYCLES OF 8085:

 The 8085 microprocessor has 5 (seven) basic machine cycles. They are
1.Opcode fetch cycle (4T)

2.Memory read cycle (3 T)

3.Memory write cycle (3 T)

4.I/O read cycle (3 T)

5.I/O write cycle (3 T)

 Each instruction of the 8085 processor consists of one to five machine cycles, i.e.,
when the 8085 processor executes an instruction, it will execute some of the
machine cycles in a specific order.

 The processor takes a definite time to execute the machine cycles. The time taken
by the processor to execute a machine cycle is expressed in T-states.

 One T-state is equal to the time period of the internal clock signal of the
processor.

 The T-state starts at the falling edge of a clock.

Opcode fetch machine cycle of 8085 :  The opcodes are stored in memory. So,
 Each instruction of the processor has one byte opcode. the processor executes the opcode fetch
machine cycle to fetch the opcode from
memory.
 Hence, every instruction starts with opcode
fetch machine cycle.

 The time taken by the processor to execute

the opcode fetch cycle is 4T.

 In this time, the first, 3 T-states are used for

fetching the opcode from memory and the
remaining T-states are used for internal
operations by the processor.
Memory Read Machine Cycle of 8085:

 The memory read machine cycle is

executed by the processor to read a data
byte from memory.

 The processor takes 3T states to execute this

cycle.

 The instructions which have more than one

byte word size will use the machine cycle
after the opcode fetch machine cycle
Memory Write Machine Cycle of 8085:

 The memory write machine cycle is

executed by the processor to write a
data byte in a memory location.

 The processor takes,3T states to

execute this machine cycle.
I/O Read Cycle of 8085:
 The I/O Read cycle is executed by the
processor to read a data byte from
I/O port or from the peripheral, which
is I/O, mapped in the system.

 The processor takes 3T states to

execute this machine cycle.

 The IN instruction uses this machine

cycle during the execution
I/O Write Cycle of 8085:

 The I/O write machine cycle is

executed by the processor to write a
data byte in the I/O port or to a
peripheral, which is I/O, mapped in
the system.

 The processor takes, 3T states to

execute this machine cycle.
Timing diagram for STA 526AH.
 STA means Store Accumulator -The contents of the accumulator is stored in
the specified address(526A).

 The opcode of the STA instruction is said to be 32H. It is fetched from the
memory 41FFH(see fig). - OF machine cycle

 Then the lower order memory address is read(6A). – Memory Read

 Read the higher order memory address (52).- Memory Read Machine Cycle

 The combination of both the addresses are considered and the content from
accumulator is written in 526A. – Memory Write Machine Cycle

 Assume the memory address for the instruction and let the content of
accumulator is C7H. So, C7H from accumulator is now stored in 526A
Timing diagram for IN C0H.  Fetching the Opcode DBH from the
memory 4125H.

 Read the port address C0H from 4126H.

 Read the content of port C0H and send

it to the accumulator.

 Let the content of port is 5EH.

INTERRUPT STRUCTURE

 Interrupt is signals send by an external device to the processor, to request the processor to perform a
particular task or work.
 Mainly in the microprocessor based system the interrupts are used for data transfer between the
peripheral and the microprocessor.
 The processor will check the interrupts always at the 2nd T-state of last machine cycle.
 If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.
 The vectored address of particular interrupt is stored in program counter.
 The processor executes an interrupt service routine (ISR) addressed in program counter.
 It returned to main program by RET instruction.
Types of Interrupts:
It supports two types of interrupts

1. Hardware interrupts The Table shows the vector addresses of all interrupts.

2. Software interrupts
Software interrupts:
 The software interrupts are program instructions. These
instructions are inserted at desired locations in a program.

 The 8085 has eight software interrupts from RST 0 to

RST 7. The vector address for these interrupts can be
calculated as follows.
.
Hardware interrupts

 An external device initiates the hardware interrupts and placing an appropriate signal at the
interrupt pin of the processor.
 If the interrupt is accepted then the processor executes an interrupt service routine.

The 8085 has five hardware interrupts

1) TRAP
2) RST 7.5
3) RST 6.5
4) RST 5.5
5) INTR
TRAP:

 This interrupt is a non-maskable interrupt. It is unaffected by any mask or interrupt enable.

 TRAP has the highest priority and vectored interrupt.
 TRAP interrupt is edge and level triggered. This means hat the TRAP must go high and remain
high until it is acknowledged.
 In sudden power failure, it executes a ISR and send the data from main memory to backup
memory.
 The signal, which overrides the TRAP, is HOLD signal. (i.e., If the processor receives HOLD
and TRAP at the same time then HOLD is recognized first and then TRAP is recognized).
RST 7.5:

 The RST 7.5 interrupt is a maskable interrupt.

 It has the second highest priority
 It is edge sensitive. ie. Input goes to high and no need to maintain high state until it
recognized.
 Maskable interrupt.
 Enabled by EI instruction.
RST 6.5 and 5.5:

 The RST 6.5 and RST 5.5 both are level triggered. ie. Inputs goes to high and stay
high until it recognized.
 Maskable interrupt.
 Enabled by EI instruction.
 The RST 6.5 has the third priority whereas RST 5.5 has the fourth priority.
INTR:

 INTR is a maskable interrupt.

 Enabled by EI instruction
 Non- vectored interrupt. After receiving INTA (active low) signal, it has to supply the
address of ISR.
 It has lowest priority
 It is a level sensitive interrupts. ie. Input goes to high and it is necessary to maintain
high state until it recognized.
SIM and RIM for interrupts:

 The 8085 provide additional masking facility for RST 7.5, RST 6.5 and RST 5.5 using
SIM instruction.
 The format of the 8-bit data is shown below.
I/O and Memory interfacing examples

EXAMPLE-1

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the
EPROM with 8085 processor.

 The memory capacity is 64 Kbytes. i.e. 2n = 64 x 1000 bytes where n = address lines. So, n = 16.
 In this system the entire 16 address lines of the processor are connected to address input pins of memory IC
in order to address the internal locations of memory.
 The chip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
 Since the processor is connected to EPROM, the active low RD pin is connected to active low output
enable pin of EPROM.
 The range of address for EPROM is 0000H to FFFFH.
EXAMPLE-2
Consider a system in which the available 64kb memory space is equally divided between EPROM and RAM.
Interface the EPROM and RAM with 8085 processor.

 Implement 32kb memory capacity of EPROM using single IC 27256. 32kb RAM capacity is
implemented using single IC 62256.
 The 32kb memory requires 15 address lines and so the address lines A0 - A14 of the processor are
connected to 15 address pins of both EPROM and RAM.
 The unused address line A15 is used as to chip select. If A15 is 1, it select RAM and If A15 is 0, it
select EPROM.
 Inverter is used for selecting the memory.
 The memory used is both RAM and EPROM, so the low RD and WR pins of processor are connected
to low WE and OE pins of memory respectively.
 The address range of EPROM will be 0000H to 7FFFH and that of RAM will be 8000H to FFFFH.
EXAMPLE-3
Consider a system in which 32kb memory space is implemented using four numbers of 8kb memory. Interface the
EPROM and RAM with 8085 processor.

 The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining
two numbers be RAM.
 Each 8kb memory requires 13 address lines and so the address lines A0- A12 of the processor are
connected to 13 address pins of all the memory.
 The address lines and A13 - A14 can be decoded using a 2-to-4 decoder to generate four chip select
signals.
 These four chip select signals can be used to select one of the four memory IC at any one time.
 The address line A15 is used as enable for decoder.
 The simplified schematic memory organization is shown.
 The address allotted to each memory IC is shown in following table.