River Publishers Series in Circuits and Systems

Introduction to Wireless

Communication Circuits
Introduction to Wireless
Communication Circuits
Introduction to Wireless

2nd Edition
2nd Edition

Forouhar Farzaneh, Ali Fotowat,

Communication Circuits
Mahmoud Kamarei, Ali Nikoofard 2nd Edition
and Mohammad Elmi
Forouhar Farzaneh
Over the past decade the tremendous development of Wireless Ali Fotowat
Communications has changed human life incredibly. Considerable
advancement has been made in the design and architecture of Mahmoud Kamarei
communications related RF and Microwave circuits. This book is focused
on special circuits dedicated to the RF level of wireless Communications.
Ali Nikoofard
From Oscillators to Modulation and Demodulation and from Mixers to Mohammad Elmi I
RF and Power Amplifier Circuits, the topics are presented in a sequential

Mahmoud Kamarei, Ali Nikoofard

Forouhar Farzaneh, Ali Fotowat,
manner. A wealth of analysis is provided in the text alongside various
Q
worked out examples. Related problem sets are given at the end of each
chapter. Basic concepts of RF Analog Circuit Design are developed in π/2

and Mohammad Elmi

÷N VCO
the book.
Technical topics discussed in the book include: PLL ÷M
• Wireless Communication System
• RF Oscillators and Phase Locked Loops
• Modulator and Demodulator Circuits
I
• RF Mixers
• Automatic Gain Control and Limiters +
• Microwave Circuits, Transmission Lines and S-Parameters Q
• Matching networks π/2
PLL

• Linear Amplifier Design and Power Amplifiers

• Linearization Techniques
Foreword by
Behzad Razavi, UCLA, USA

River Publishers River River Publishers

Introduction to
Wireless Communication Circuits
2nd Edition

Forouhar Farzaneh, Ali Fotowat, Mahmoud Kamarei

Ali Nikoofard and Mohammad Elmi
RIVER PUBLISHERS SERIES IN CIRCUITS AND SYSTEMS

Series Editors

MASSIMO ALIOTO KOFI MAKINWA

National University of Singapore Delft University of Technology
Singapore The Netherlands
DENNIS SYLVESTER
University of Michigan
USA

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Introduction to
Wireless Communication Circuits
2nd Edition

Forouhar Farzaneh
Professor
Sharif University of Technology, Iran

Ali Fotowat
Associate Professor
Sharif University of Technology, Iran

Mahmoud Kamarei
Professor
University of Tehran, Iran

Ali Nikoofard
Research Engineer
University of California at San Diego, USA

Mohammad Elmi
Research Engineer
KavoshCom Asia Co., Iran

River Publishers
Published, sold and distributed by:
River Publishers
Alsbjergvej 10
9260 Gistrup
Denmark

River Publishers
Lange Geer 44
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Tel.: +45369953197
www.riverpublishers.com

ISBN: 978-87-7022-140-5 (Hardback)

978-87-7022-139-9 (Ebook)

c 2020 River Publishers

All rights reserved. No part of this publication may be reproduced, stored in a

retrieval system, or transmitted in any form or by any means, mechanical,
photocopying, recording or otherwise, without prior written permission of the
publishers.
Foreword

As wireless technology takes over every aspect of our lives, the university
curricula must keep up with the developments and impart proper skills to their
graduates so as to prepare them for this rapidly-evolving industry. In particular,
the vast body of undergraduate students must be trained in this domain, but
efficiently, as course proliferation is undesirable in most universities.
“Introduction to Wireless Communication Circuits” addresses this need by
selecting the most relevant topics and teaching them in a language that appeals
to undergraduate students. The textbook methodically guides the reader through
the concepts and, using numerous detailed examples, reenforces these concepts.
The reader is then invited to exercise his/her understanding by solving problems
at the end of each chapter.
The contents of the book have been chosen carefully to allow coverage in
one semester or quarter. That is, the book can serve as a self-contained text
that the students can read “cover to cover” in one term without skipping any
major sections. These pedagogical aspects of the book facilitate its use for both
students and instructors.

Behzad Razavi
Professor
University of California, Los Angeles
February 2018

v
Preface to the Second Edition

During the past couple of years where we used this book as our teaching
reference in wireless communication circuits, we encountered a number of
points to be clarified or improved in the text. To this effect, we have prepared
the material for the second edition. Scores of equations and a few figures were
added; therefore, the second edition contains 1161 equations and 505 figures
which help more in the analysis and understanding of the text. We have changed
the text in hundreds of instances to make the material straightforward and more
comprehensible. We hope that this new edition will be more useful for the
students and practicing engineers.

F. Farzaneh, A. Fotowat, M. Kamarei, A. Nikoofard, and M. Elmi

Tehran, November 2019

vii
Preface to the First Edition

The tremendous development of the wireless communications during the past

twenty years has had such a great impact on the human life and the society
that no one can ignore its overwhelming presence in today’s life, let alone
the today’s engineering. Students in Electrical Engineering, nowadays, are
normally exposed to courses in wireless communications, wireless circuits,
and the electromagnetic-wave propagation. The authors have been involved
in teaching and research in the field of wireless circuits during the past thirty
years in the Iranian universities and institutions namely Sharif University
of Technology, University of Tehran, and KavoshCom Asia R&D Company.
During these years we have felt a lack of a comprehensive book which would
cover the needed material for a course coverage at the B.Sc. level of Electrical
Engineering. Furthermore, as engineers at a research institution, we observed
the necessity of a comprehensive text which would help the RF engineers in
their RF circuit design and implementation. As a matter of fact, a number of
circuits and ideas presented in this book were obtained during the development
of new RF transceiver circuits, GPS receivers and wireless communication
systems intended for fleet control in ground transportation at KavoshCom Co.
We have tested or verified the most of the presented circuits in this book
by standard RF simulation tools to be sure of their proper operation. For
materializing this book, we have used most of our course materials especially
intended for the communication circuits course. It took us a long three years of
intensive work to realize this book. Our intention was to make it accessible to
the Electrical Engineering community worldwide, as a result of our efforts in
the field of RF circuits and wireless communication.

ix
x Preface to the First Edition

This book is divided into three parts. In Part I, chapter 1 is dedicated to

the wireless communication systems and the building blocks of a modern radio
transceiver. Chapter 2 describes the major operation and configuration of the
RF oscillators where the major topologies of the modern electronic oscillators
are presented as well as the large signal modeling and evaluation of these
circuits.
Part II of the book is dedicated to the major building circuit blocks of
modern transceivers. Chapter 3 presents PLLs, different PLL topologies, FM
modulators and FM demodulators. Chapter 4 deals with the RF mixer circuits
where different type of mixers from the switching circuits to analog multipliers
are presented. The major concepts of nonlinearity in RF circuits namely
the compression, the intermodulation products, and the intercept point are
introduced in this chapter. Chapter 5 is dedicated to Amplitude and Phase
Modulation. This chapter begins with analog amplitude modulation techniques
and then goes through present day multilevel amplitude and phase digital
modulations. Chapter 6 describes the Limiters and the Automatic Gain Control
circuits. Offset compensation circuits are presented in this chapter followed
by different Automatic Gain Control methods. The amplitude detectors and
methods for increasing the Gain Bandwidth of amplifiers are also described in
this chapter as well.
Part III of the book is dedicated to Transmission Lines, Microwave circuit
modeling, and Microwave Amplifiers using Scattering Parameters as well as
the Power Amplifier description. Chapter 7 describes the fundamentals of RF
Transmission Lines and Impedance Matching Circuits. Chapter 8 is intended to
the introduction of Scattering Parameters as a modern tool for amplifier circuit
design in the microwave range. Chapter 9 presents the analysis and design of
microwave amplifiers using S-parameters. The problem of stability of two-ports
using S-parameters is studied in detail. The simultaneous conjugate matching
of an amplifier using S-parameters is presented alongside the design of Low
Noise Amplifiers using noise parameters. The design of two-stage amplifiers
including the noise and the gain parameters is described at last. In chapter 10
the Power Amplifiers are presented. Different classes of power amplifiers, their
mode of operation, their efficiencies, and their power capabilities are studied in
this chapter. The linearization methods for the power amplifiers as a modern
tool for the present day transmitters are presented in this chapter as well.
We would like to thank all the colleagues and the students for their helpful
discussions and encouragements which was necessary for the materialization
of this book.

F. Farzaneh, A. Fotowat Ahmady, M. Kamarei, A. Nikoofard, M. Elmi

Tehran, Iran
December 2017
Contents

Foreword. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

. . the
Preface to . . . Second
. . . . . . .Edition
. . . . . . . . . . . . . . . . . . . . . . . . . . . vii

. . the
Preface to . . . First
. . . .Edition
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix
List of Figures

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxvii
List of Tables

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxxix
List of Abbreviations

I Part 1
1 The Amazing World of Wireless Systems . . . . . . . . . 3
1.1 Introduction to Communication Circuits . . . . . . . . . . . . . 3
1.2 Signal Levels and Rayleigh Fading . . . . . . . . . . . . . . . . 8
1.3 Calculation of the Sensitivity in Different Standards . . . . . 9
1.4 Considerations in RF System Design . . . . . . . . . . . . . . . 10
1.5 A Basic Understanding of Frequency Synthesizers . . . . . 17
1.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7 References and Further Reading . . . . . . . . . . . . . . . . . 21
1.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

xi
xii Contents

2 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 An Introduction to Oscillators . . . . . . . . . . . . . . . . . . . 27
2.2 First Approach: Positive Feedback . . . . . . . . . . . . . . . 27
2.3 Second Approach: Negative Resistance/
Conductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.4 Oscillator Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.4.1 Common-Emitter Oscillator Circuit . . . . . . . . . . . . . . . 36
2.4.2 Common-Base Oscillator Circuit . . . . . . . . . . . . . . . . . 37
2.4.3 Common-Collector Oscillator Circuit . . . . . . . . . . . . . . 37
2.4.4 Colpitts versus Hartley Oscillators, a New Insight . . . . . . 38
2.5 Crystal Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.5.1 Datasheet of a Family of Crystals . . . . . . . . . . . . . . . . 45
2.6 Calculation of the Oscillation Frequency Including
the Device Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.7 Quality Factor of Reactive Elements . . . . . . . . . . . . . . 47
2.8 Nonlinear Behavior in Amplifiers . . . . . . . . . . . . . . . . . 49
2.9 A Note on the Modified Bessel Functions of the
First Kind . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
2.10 Large-Signal Transconductance and Harmonic Tuned
Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
2.10.1 Case I: Resonant circuit is tuned to the first harmonic
of the input frequency (tuned amplifier case) . . . . . . . 58
2.10.2 Case II: Resonant circuit is tuned to the second
harmonic of the input frequency (frequency multiplier
case) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.11 Differential Bipolar Stage Large-Signal
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . 63
2.12 Inductive and Capacitive Dividers (Impedance
Transformers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
2.12.1 Tapped Capacitive/Inductive Impedance
Transformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
2.13 Analysis of Large-signal Loop Gain of an Oscillator . . . . 74
2.13.1 Increasing the Quality Factor and the Frequency
Stability with a Crystal . . . . . . . . . . . . . . . . . . . . . . . . 77
2.13.2 Oscillator Harmonics Calculation . . . . . . . . . . . . . . . . 81
2.14 Colpitts Oscillator with Emitter Degeneration . . . . . . . . 82
2.15 MOS Stage Large-Signal Transconductance . . . . . . . . . 83
2.16 Differential MOS Stage Large-Signal
Transconductance . . . . . . . . . . . . . . . . . . . . . . . . . . 86
2.17 An Oscillator With a Hypothetical Model . . . . . . . . . . . 89
2.18 A MOS Oscillator with Differential Gain Stage . . . . . . . . 90
Contents xiii

2.19 Voltage-Controlled Oscillators . . . . . . . . . . . . . . . . . . 91

2.19.1 Different Types of Varactors and their Bias . . . . . . . . . . 91
2.20 Special Topic: Nonlinear Device Fed by Sinusoidal
Large-Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
2.21 Datasheet of a Voltage-Controlled Oscillator . . . . . . . 108
2.22 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
2.23 References and Further Reading . . . . . . . . . . . . . . . . 111
2.24 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

II Part 2
3 PLL, FM Modulation, and FM Demodulation . . . . 127
3.1 Frequency Modulation . . . . . . . . . . . . . . . . . . . . . . . 127
3.2 Frequency Demodulation . . . . . . . . . . . . . . . . . . . . . 130
3.2.1 Phase Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
3.2.2 Gilbert Cell as a Phase Detector . . . . . . . . . . . . . . . . 131
3.2.3 Quadrature Phase (FM) Detector . . . . . . . . . . . . . . . 134
3.3 Basics of PLLs and their Application as an FM
Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
3.3.1 The Transfer Function of the First-Order PLL . . . . . . . . . 144
3.4 Further PLL Applications . . . . . . . . . . . . . . . . . . . . . . 152
3.4.1 FM with PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
3.4.2 PLL Application in Frequency Synthesizers and
Its Transfer function . . . . . . . . . . . . . . . . . . . . . . . . . 158
3.5 Advanced Topic: PLL Type II . . . . . . . . . . . . . . . . . . . 161
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
3.7 References and Further Reading . . . . . . . . . . . . . . . . 165
3.8 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

4 Mixers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.1 Mixer Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
4.1.1 The Conceptual Behavior of Single-Diode Mixers . . . . 169
4.1.2 A Nonlinear Circuit as a Mixer . . . . . . . . . . . . . . . . . . 170
4.2 Third Order Intermodulation Concept in a Nonlinear
Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
4.2.1 Characteristic of Third-Order IM and Measurement
Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
4.3 Basic Concept of Third-Order IM in a Basic Mixer . . . . 174
4.3.1 The Desired Channel Blocking with the Third-Order
IM Component . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
xiv Contents

4.3.2 Special Content: IM with Any Nonlinear Circuit

as a Mixer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
4.4 Bipolar Transistor Active Mixer . . . . . . . . . . . . . . . . . . 180
4.5 Mixer types Based on Switching Circuits . . . . . . . . . . 184
4.5.1 Conversion Gain and Local Oscillator Leakage . . . . . 185
4.6 Matching in Mixers . . . . . . . . . . . . . . . . . . . . . . . . . 194
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer . . . . . . . 194
4.7.1 Compression Point and IIP3 in a Nonlinear
Transconductance Mixer . . . . . . . . . . . . . . . . . . . . . 197
4.7.2 IIP3 of Differential Pair Amplifiers . . . . . . . . . . . . . . . . 200
4.8 Linearization Methods in Mixers . . . . . . . . . . . . . . . . 203
4.9 Calculating Third-Order Input Intercept Point
in Cascaded Stages . . . . . . . . . . . . . . . . . . . . . . . . 209
4.9.1 Third-Order Input Intercept Voltage of Cascaded
stages in
Terms of Single-Stage Intercept Voltage . . . . . . . . . . . 209
4.9.2 Combination of Amplifier and Mixer . . . . . . . . . . . . . 210
4.10 Important Point in RF Circuit Simulation . . . . . . . . . . . 212
4.11 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
4.12 References and Further Reading . . . . . . . . . . . . . . . . 213
4.13 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214

5 Modulation/Demodulation of Amplitude/Phase 223

5.1 AM Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
5.2 AM Demodulation . . . . . . . . . . . . . . . . . . . . . . . . . . 224
5.3 Generating AM Signals . . . . . . . . . . . . . . . . . . . . . . 226
5.4 Double-Sideband and Single-Sideband Suppressed
Carrier Generation . . . . . . . . . . . . . . . . . . . . . . . . . 229
5.5 Synchronous AM Detection . . . . . . . . . . . . . . . . . . . 231
5.5.1 A Synchronous AM Detection (with carrier
extraction) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
5.6 Gilbert Cell Applications . . . . . . . . . . . . . . . . . . . . . 234
5.7 Modern Practical Modulations . . . . . . . . . . . . . . . . . 235
5.7.1 Binary Phase Shift Keying . . . . . . . . . . . . . . . . . . . . . 235
5.7.2 Quadrature Phase Shift Keying . . . . . . . . . . . . . . . . . 235
5.7.3 Quadrature Amplitude Modulation (16 – QAM) . . . . . 236
5.7.4 Quadrature Amplitude Modulation (6 – QAM) . . . . . . 237
5.7.5 Generating Binary Phase Shift Keying Signal . . . . . . . . 238
5.7.6 Generating and Detecting the Quadrature Phase
Shift Keying Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 239
Contents xv

5.8 Effect of Phase and Amplitude Mismatch on the

Signal Constellation . . . . . . . . . . . . . . . . . . . . . . . . . 240
5.8.1 Improvement of bandwidth efficiency . . . . . . . . . . . . 243
5.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249
5.10 References and Further Reading . . . . . . . . . . . . . . . . 249
5.11 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

6 Limiters and Automatic Gain Control . . . . . . . . . 257

6.1 Limiting Versus Automatic Gain Control . . . . . . . . . . . 257
6.1.1 Limiting Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
6.1.2 AGC Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
6.2 Total Bandwidth with Multistage . . . . . . . . . . . . . . . . 259
6.3 Offset Compensation Circuits . . . . . . . . . . . . . . . . . . 261
6.3.1 Lower Cut-off Frequency of the Amplifier with Offset
Compensation Loop . . . . . . . . . . . . . . . . . . . . . . . . 263
6.4 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . 265
6.4.1 Gain Control Methods . . . . . . . . . . . . . . . . . . . . . . . 265
6.5 Amplitude Detectors . . . . . . . . . . . . . . . . . . . . . . . . 268
6.5.1 Logarithmic Signal Level Indicator . . . . . . . . . . . . . . . 269
6.6 Amplifier Circuit with Gain Control Based on Analog
Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270
6.7 Increasing Bandwidth Methods . . . . . . . . . . . . . . . . . 273
6.7.1 Employing High-Speed Transistors . . . . . . . . . . . . . . . 273
6.7.2 Increasing Unity Current Gain Frequency . . . . . . . . . . 274
6.7.3 Inductive Load (Shunt Peaking) . . . . . . . . . . . . . . . . 274
6.7.4 Decreasing Input Capacitance by Series
Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276
6.8 Oscillation in Limiting Stages . . . . . . . . . . . . . . . . . . . 277
6.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
6.10 References and Further Reading . . . . . . . . . . . . . . . . 279

III Part 3
7 Transmission Lines and Impedance Matching . . 283
7.1 An Introduction to Radio-Frequency Amplifiers
in Receivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283
7.1.1 Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
7.2 Wave propagation Equations in Transmission Line
for R = 0 and G = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 286
7.2.1 General Wave Propagation Relations in lossy
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
xvi Contents

7.3 Characteristic Impedance of a Line . . . . . . . . . . . . . 291

7.3.1 Lossless Transmission Line . . . . . . . . . . . . . . . . . . . . . 292
7.4 Terminated Transmission Lines . . . . . . . . . . . . . . . . . . 293
7.5 Special Cases of a Terminated Line . . . . . . . . . . . . . . 298
7.5.1 Termination to the Line Characteristic Impedance . . . 298
7.5.2 Short-circuit load impedance . . . . . . . . . . . . . . . . . . 299
7.5.3 Open-circuit load . . . . . . . . . . . . . . . . . . . . . . . . . . 300
7.6 Source and Load Mismatch in Lossless Lines
(A Reflection Coefficient Perspective) . . . . . . . . . . . . 301
7.7 Impedance Transformer Based on λ/4 line
(Impedance Inverter) . . . . . . . . . . . . . . . . . . . . . . . 304
7.7.1 Synthesis of an Inductor and a Capacitor with
a Transmission Line . . . . . . . . . . . . . . . . . . . . . . . . . . 305
7.8 Voltage Standing Wave Ratio . . . . . . . . . . . . . . . . . . 305
7.9 Impedance Matching: The L-Section Approach . . . . . 306
7.9.1 A New Definition of the Quality Factor . . . . . . . . . . . . 311
7.10 Smith Chart Mapping . . . . . . . . . . . . . . . . . . . . . . . . 322
7.10.1 Some simple application rules while using the
Smith chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327
7.11 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339
7.12 References and Further Reading . . . . . . . . . . . . . . . . 340
7.13 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

8 Scattering Parameters . . . . . . . . . . . . . . . . . . . . 349

8.1 Representation of Two-Port Networks . . . . . . . . . . . . . 349
8.1.1 Common Circuit Parameters of Two-Port Networks . . . 349
8.1.2 Scattering Parameters . . . . . . . . . . . . . . . . . . . . . . . 351
8.2 Measuring S-Parameters Using a Network
Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
8.2.1 Operation of a Network Analyzer . . . . . . . . . . . . . . . 357
8.2.2 Calibration Using Electrical Delay . . . . . . . . . . . . . . . 358
8.2.3 Quiescent Point bias Circuit . . . . . . . . . . . . . . . . . . . 358
8.2.4 One-Port and Two-Port Calibration for Short Circuit,
Open Circuit, and the Characteristic Impedance . . . 359
8.3 Conversion of Network Matrices . . . . . . . . . . . . . . . . 369
8.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
8.5 References and Further Reading . . . . . . . . . . . . . . . . 371
8.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372

9 Amplifier Design Using S-parameters . . . . . . . . . 377

9.1 Amplifier Design Using Scattering Parameters . . . . . . 377
9.2 Specification of Amplifiers . . . . . . . . . . . . . . . . . . . . 377
Contents xvii

9.3 Performance Parameters of an Amplifier . . . . . . . . . . 380

9.3.1 Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
9.3.2 Maximum APG . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384
9.4 Power Gain Contours . . . . . . . . . . . . . . . . . . . . . . . . 391
9.4.1 OPG Contours for Bilateral Unconditionally
Stable Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
9.4.2 APG Contours for Bilateral Conditionally
Stable Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
9.5 Noise Behavior of a Two-Port Network . . . . . . . . . . . . 399
9.5.1 Noise in a Two-Port . . . . . . . . . . . . . . . . . . . . . . . . . . 399
9.6 Constant Noise Figure Contours . . . . . . . . . . . . . . . . 403
9.7 Design of a Single-Stage Low-Noise Amplifier . . . . . . . 406
9.8 Design of Two-Stage Amplifiers . . . . . . . . . . . . . . . . . 409
9.9 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
9.10 References and Further Reading . . . . . . . . . . . . . . . . 414
9.11 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

10 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 425

10.1 PA Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
10.1.1 PA Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426
10.1.2 PA Output Power . . . . . . . . . . . . . . . . . . . . . . . . . . . 427
10.1.3 Receive-band Noise . . . . . . . . . . . . . . . . . . . . . . . . 429
10.1.4 PA Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430
10.1.5 Linearity Considerations in PA . . . . . . . . . . . . . . . . . . 431
10.1.6 PA Stability Considerations . . . . . . . . . . . . . . . . . . . . 440
10.2 PA Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
10.2.1 Class A Power Amplifier . . . . . . . . . . . . . . . . . . . . . . 441
10.2.2 Class B Power Amplifier . . . . . . . . . . . . . . . . . . . . . . 443
10.2.3 Class AB Power Amplifier . . . . . . . . . . . . . . . . . . . . . 445
10.2.4 Class C Power Amplifier . . . . . . . . . . . . . . . . . . . . . . 446
10.2.5 Comparison Between Class A, Class B, Class AB,
and Class C Amplifiers . . . . . . . . . . . . . . . . . . . . . . . 448
10.2.6 Class D Power Amplifier . . . . . . . . . . . . . . . . . . . . . . 448
10.2.7 Class E Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 451
10.2.8 Class F Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 452
10.2.9 Class S Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . 454
10.2.10 PA’s Performance Comparison . . . . . . . . . . . . . . . . . 455
10.3 Linearization Techniques in Power Amplifiers . . . . . . . 455
10.3.1 Back-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455
10.3.2 Predistortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
10.3.3 Polar Modulation Feedback . . . . . . . . . . . . . . . . . . . 458
10.3.4 Cartesian Modulation Feedback . . . . . . . . . . . . . . . 459
10.3.5 Feedforward Method . . . . . . . . . . . . . . . . . . . . . . . . 459
xviii Contents

10.3.6 Linear amplification with nonlinear components . . . . 460

10.3.7 Envelope Elimination and Restoration . . . . . . . . . . . . 461
10.3.8 Pulse Amplitude and Width Modulation . . . . . . . . . . . 461
10.3.9 Switching Parallel Amplifiers . . . . . . . . . . . . . . . . . . . 462
10.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
10.5 References and Further Reading . . . . . . . . . . . . . . . . 464
10.6 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469

Authors Biographies . . . . . . . . . . . . . . . . . . . . . . 491

List of Figures

Figure 1.1 The general block diagram of a transceiver (radio transmitter

plus receiver) . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 1.2 The spectrum of DAMPS showing two simultaneous
subscribers . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 1.3 The DAMPS channel spacing stipulates one empty channel
between two adjacent channels in every cell (30 kHz guard
band is considered between two adjacent channels) . . . . 7
Figure 1.4 Three clusters of seven cell frequency distribution for
DAMPS or GSM . . . . . . . . . . . . . . . . . . . . . . 7
Figure 1.5 Concept of Rayleigh fading . . . . . . . . . . . . . . . . . 9
Figure 1.6 System-level schematic of the DAMPS receiver
(the analog portion) . . . . . . . . . . . . . . . . . . . . . 11
Figure 1.7 The desired channel, the adjacent channel, and the
neighboring channel in a typical DAMPS radio signal . . . 13
Figure 1.8 Typical received DAMPS signal levels after the third
band-pass filter at 90 MHz . . . . . . . . . . . . . . . . . 13
Figure 1.9 Typical received DAMPS signal levels after the fourth
band-pass filter at 455 kHz . . . . . . . . . . . . . . . . . 14
Figure 1.10 Typical received DAMPS signal levels after the fifth
band-pass filter at 455 kHz . . . . . . . . . . . . . . . . . 15
Figure 1.11 Typical received DAMPS signal levels at the input of the
frequency demodulator . . . . . . . . . . . . . . . . . . . 15
Figure 1.12 Typical integer N frequency synthesizer for the DAMPS
receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 1.13 A complete block diagram of a DAMPS transceiver . . . . 18
Figure 1.14 A typical heterodyne digital radio receiver . . . . . . . . . 19
Figure 1.15 Triple downconversion wideband receiver . . . . . . . . . 22
Figure 1.16 Frequency response of filters . . . . . . . . . . . . . . . . 22

xix
xx List of Figures

Figure 1.17 A typical GSM900 transceiver . . . . . . . . . . . . . . . 22

Figure 1.18 A VHF FM transceiver block diagram . . . . . . . . . . . 23
Figure 1.19 A dual conversion wideband receiver . . . . . . . . . . . . 23
Figure 1.20 An I/Q double conversion WiMax receiver . . . . . . . . . 24
Figure 1.21 A simplified GSM900 receiver . . . . . . . . . . . . . . . 25
Figure 2.1 Block diagram of a typical oscillator . . . . . . . . . . . . 28
Figure 2.2 Typical white noise samples, (a) in time and (b) in frequency
domain . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 2.3 The output signal of the resonance circuit for different quality
factor values . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 2.4 Input/output phasor voltage characteristic of a typical
limiting amplifier . . . . . . . . . . . . . . . . . . . . . . 30
Figure 2.5 Typical variations of the large-signal gain of a nonlinear
amplifier as a function of input voltage . . . . . . . . . . . 31
Figure 2.6 Typical oscillations’ start-up of an oscillator as a function
of time (oscillation frequency is about 2 MHz ) . . . . . . 31
Figure 2.7 Negative and positive resistors in a simple circuit . . . . . 32
Figure 2.8 Energy generation in resonant circuit with no external
excitation . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 2.9 Negative resistance model of an oscillator . . . . . . . . . 34
Figure 2.10 General oscillator topology with three reactive elements . 34
Figure 2.11 Two possible oscillator topologies with negative voltage gain
(Av < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 2.12 Two possible oscillator topologies with positive voltage gain
greater than unity (Av > 1) . . . . . . . . . . . . . . . . . 36
Figure 2.13 Two possible oscillator topologies with positive voltage gain
less than unity (0 < Av < 1) . . . . . . . . . . . . . . . . . 36
Figure 2.14 The common-emitter oscillator circuit with 180◦ phase shift
through the LC circuit . . . . . . . . . . . . . . . . . . . 37
Figure 2.15 The common-base oscillator circuit . . . . . . . . . . . . 37
Figure 2.16 The common-collector oscillator circuit . . . . . . . . . . 38
Figure 2.17 The Colpitts and the Hartley oscillators (in common-emitter,
common-collector, and common-base configurations) and
their corresponding main core circuits . . . . . . . . . . . 39
Figure 2.18 A Colpitts oscillator core including the parasitic elements of
the transistor . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 2.19 The equivalent circuit of the Colpitts oscillator . . . . . . 40
Figure 2.20 Electrical model of a crystal and its impedance behavior . 41
Figure 2.21 Simulation of crystal impedance . . . . . . . . . . . . . . 42
Figure 2.22 Three different Colpitts-like crystal oscillator configurations
with a bipolar transistor . . . . . . . . . . . . . . . . . . . 43
Figure 2.23 A complete model of a crystal . . . . . . . . . . . . . . . 44
Figure 2.24 Equivalent series resistance of HC-49/U . . . . . . . . . . 46
Figure 2.25 Colpitts oscillator with parasitic capacitances . . . . . . . 46
Figure 2.26 Magnitude response of a band-pass filter . . . . . . . . . . 47
Figure 2.27 Equivalent circuit of an inductor . . . . . . . . . . . . . . 48
Figure 2.28 Equivalent circuit of a capacitor . . . . . . . . . . . . . . 48
List of Figures xxi

Figure 2.29 Common-emitter amplifier circuit . . . . . . . . . . . . . 49

Figure 2.30 The collector voltage, for different values of input voltage,
as a function of time . . . . . . . . . . . . . . . . . . . . 50
Figure 2.31 Common-emitter amplifier with a current source . . . . . 50
Figure 2.32 Output collector voltage with 100 mV input at 1 MHz
frequency . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 2.33 Tuned amplifier with implemented emitter current source . 51
Figure 2.34 Output voltage waveform of the tuned amplifier for a
50 mV sinusoidal input (RL = 1 kΩ, C = 3.2 nF, and
L = 7.93 µH) . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 2.35 Typical variations of the modified Bessel functions with
respect to their arguments . . . . . . . . . . . . . . . . . . 53
Figure 2.36 Harmonics of output and selecting behavior of the band-pass
filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2.37 Resonant circuit . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 2.38 Typical frequency response of a parallel resonant circuit . 56
Figure 2.39 Typical output harmonics as well as load impedance
variations for cases I and II . . . . . . . . . . . . . . . . . 59
Figure 2.40 Ratio of large-signal transconductance normalized to
small-signal transconductance as well as the conversion
transconductances for the second and the third harmonics . 60
Figure 2.41 Typical matching network for filtering undesired harmonics 61
Figure 2.42 A common-base tuned circuit oscillator . . . . . . . . . . 62
Figure 2.43 The equivalent circuit for the common-base tuned circuit
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 2.44 A differential pair tuned amplifier . . . . . . . . . . . . . 63
Figure 2.45 The evolution of the large-signal transconductance of a
differential pair tuned amplifier as a function of the
normalized input voltage amplitude . . . . . . . . . . . . 65
Figure 2.46 An ideal inductive transformer . . . . . . . . . . . . . . . 66
Figure 2.47 Inductive transformer with its loss and a capacitive load . . 66
Figure 2.48 A model of the inductive transformer with its loss . . . . . 67
Figure 2.49 Applying signal source to the inductive transformer . . . . 67
Figure 2.50 Capacitive impedance transformer with a parallel
inductance . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 2.51 Circuit models for inductive and capacitive impedance
transformers . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 2.52 Step-up capacitive voltage transformer . . . . . . . . . . . 69
Figure 2.53 Step-up capacitive voltage transformer with loaded input . 70
Figure 2.54 Step-up inductive voltage transformer . . . . . . . . . . . 71
Figure 2.55 Step-up inductive voltage transformer with loaded input . 72
Figure 2.56 Calculation of the output impedance of the loaded capacitive
transformer . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 2.57 A Colpitts oscillator core circuit . . . . . . . . . . . . . . 74
Figure 2.58 An AC model of the oscillator core of Figure 2.57 . . . . . 75
Figure 2.59 Equivalent circuit of the Colpitts oscillator . . . . . . . . . 75
Figure 2.60 A Colpitts oscillator with parasitic capacitances . . . . . . 76
xxii List of Figures

Figure 2.61 A Colpitts oscillator with series crystal . . . . . . . . . . . 78

Figure 2.62 An equivalent model for series crystal . . . . . . . . . . . 78
Figure 2.63 Impedance behavior of the crystal about its series resonance 79
Figure 2.64 Variations of the impedance of the parallel resonant circuit
about the resonance frequency . . . . . . . . . . . . . . . 79
Figure 2.65 Colpitts-like crystal oscillator; the crystal operates in an
inductive mode . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 2.66 Extracting the output signal of an oscillator without
degrading its quality factor . . . . . . . . . . . . . . . . . 81
Figure 2.67 Common-emitter amplifier with emitter degeneration . . . 82
Figure 2.68 The evolution of the large-signal transconductance of a bipo-
lar transistor biased with an emitter resistor instead of a cur-
rent source (normalized DC voltage drop across the emitter
resistor as the parameter) . . . . . . . . . . . . . . . . . . 83
Figure 2.69 Typical I−V characteristic of MOS transistor (ṼGS is the
gate–source’s AC voltage phasor) . . . . . . . . . . . . . 83
Figure 2.70 Constant current MOS stage tuned amplifier for computation
of the large-signal transconductance . . . . . . . . . . . . 84
Figure 2.71 Normalized transconductance variations of a MOS
tuned amplifier stage as a function of the normalized
input voltage . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 2.72 A differential MOS pair tuned amplifier . . . . . . . . . . 86
Figure 2.73 Variations of the differential pair drain currents as a function
of the normalized differential voltage in a MOS differential
pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 2.74 Normalized transconductance variations of a MOS
differential tuned amplifier stage as a function of the
normalized input voltage . . . . . . . . . . . . . . . . . . 88
Figure 2.75 Oscillator with a hypothetical amplifier . . . . . . . . . . 89
Figure 2.76 Differential amplifier for the oscillator . . . . . . . . . . . 91
Figure 2.77 Mechanically variable capacitor . . . . . . . . . . . . . . 92
Figure 2.78 Cross-coupled VCO with voltage variable MOS capacitors 92
Figure 2.79 Capacitance variations of a diode as a function
of its voltage . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2.80 A Colpitts voltage-controlled oscillator using a pair
of varactors . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 2.81 Voltage-controlled oscillators with different kinds of varactor
implementations . . . . . . . . . . . . . . . . . . . . . . 94
Figure 2.82 Differential MOS pair circuit . . . . . . . . . . . . . . . . 95
Figure 2.83 A differential pair MOS oscillator . . . . . . . . . . . . . 96
Figure 2.84 A VCO based on a differential pair . . . . . . . . . . . . . 96
Figure 2.85 Varactor characteristics . . . . . . . . . . . . . . . . . . . 96
Figure 2.86 A voltage-controlled oscillator with a power series nonlinear
amplifier characteristics . . . . . . . . . . . . . . . . . . . 99
Figure 2.87 Varactor characteristics . . . . . . . . . . . . . . . . . . . 99
Figure 2.88 A crystal Colpitts oscillator (Butler oscillator) where the
input current at the emitter is approximately sinusoidal . . 103
List of Figures xxiii

Figure 2.89 Variations of the normalized inverse large-signal input

resistance as a function of the input current amplitude . . . 104
Figure 2.90 Crystal Colpitts oscillator . . . . . . . . . . . . . . . . . . 104
Figure 2.91 Crystal Colpitts oscillator equivalent circuit seen through
the emitter . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Figure 2.92 Oscillation frequency, output power, and harmonic levels
of the ZX95 VCO as a function of the tuning voltage . . . 109
Figure 2.93 Oscillation frequency, output power, and harmonic levels
of the POS-100 VCO as a function of the tuning voltage . 111
Figure 2.94 Clapp-type resonant circuit . . . . . . . . . . . . . . . . . 113
Figure 2.95 Common-drain Clapp oscillator . . . . . . . . . . . . . . 113
Figure 2.96 Bipolar Colpitts oscillator . . . . . . . . . . . . . . . . . 114
Figure 2.97 MOS common-gate Colpitts oscillator . . . . . . . . . . . 114
Figure 2.98 Bipolar common-collector Colpitts oscillator with
corresponding Cµ and Cπ parasitic capacitances . . . . . . 115
Figure 2.99 Bipolar common-base Colpitts oscillator . . . . . . . . . . 115
Figure 2.100 A hypothetical oscillator block diagram . . . . . . . . . . 116
Figure 2.101 Different types of the MOS Colpitts oscillators,
common-source, common-gate, and common-drain . . . . 116
Figure 2.102 MOS tuned amplifier driven by a large signal . . . . . . . 117
Figure 2.103 Driscoll oscillator . . . . . . . . . . . . . . . . . . . . . . 117
Figure 2.104 MOS differential oscillator . . . . . . . . . . . . . . . . . 118
Figure 2.105 A BiCMOS VCO . . . . . . . . . . . . . . . . . . . . . . 118
Figure 2.106 Variable capacitance characteristics . . . . . . . . . . . . 119
Figure 2.107 Feedback amplitude control loop . . . . . . . . . . . . . . 119
Figure 2.108 An oscillator with a nonlinear amplifier in feedback . . . . 120
Figure 2.109 Colpitts oscillator . . . . . . . . . . . . . . . . . . . . . . 120
Figure 2.110 Reference Driscoll oscillator . . . . . . . . . . . . . . . . 121
Figure 2.111 Common-collector crystal oscillator . . . . . . . . . . . . 121
Figure 2.112 Differential pair tuned circuit oscillator . . . . . . . . . . 122
Figure 2.113 Pierce-like oscillator using an ideal amplifier . . . . . . . 122
Figure 2.114 Pierce crystal oscillator with a nonlinear transconductance 123
Figure 3.1 A typical voltage-controlled oscillator (VCO) with voice
input for frequency modulation . . . . . . . . . . . . . . . 128
Figure 3.2 Typical baseband and the corresponding FM signal variations
with time . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Figure 3.3 XOR (phase detection) characteristics driven by two signals
with a common frequency and a fixed phase shift . . . . . 131
Figure 3.4 Gilbert cell (analog multiplier), (a) by bipolar transistor pairs
and (b) by MOS transistor pairs, used as a phase detector . 131
Figure 3.5 Gilbert cell function as a phase detector. (a) The phase
detector output characteristics. (b) Signal waveforms for
phase detector operation . . . . . . . . . . . . . . . . . . 132
Figure 3.6 Signal receiver for FM . . . . . . . . . . . . . . . . . . . 135
Figure 3.7 Frequency response of the phase detector . . . . . . . . . 136
Figure 3.8 Phase characteristics of the quadrature tank by different
quality factors . . . . . . . . . . . . . . . . . . . . . . . . 137
xxiv List of Figures

Figure 3.9 A linear approximation for phase characteristic of the

quadrature tank . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 3.10 Frequency demodulator by quadrature phase detector using
a Sallen–key filter . . . . . . . . . . . . . . . . . . . . . . 139
Figure 3.11 Frequency demodulation with PLL . . . . . . . . . . . . . 142
Figure 3.12 PLL schematic diagram . . . . . . . . . . . . . . . . . . . 143
Figure 3.13 PLL model . . . . . . . . . . . . . . . . . . . . . . . . . 144
Figure 3.14 Overshoot in the frequency response of the PLL near the
natural frequency . . . . . . . . . . . . . . . . . . . . . . 145
Figure 3.15 The Gilbert cell used as the phase detector . . . . . . . . . 146
Figure 3.16 The desired transfer function of the phase detector . . . . 146
Figure 3.17 Simple PLL (Type I) . . . . . . . . . . . . . . . . . . . . 146
Figure 3.18 Time response of the PLL Frequency . . . . . . . . . . . 148
Figure 3.19 The control voltage of the PLL as a function of time . . . 148
Figure 3.20 Quadrature FM demodulator . . . . . . . . . . . . . . . . 149
Figure 3.21 Gilbert cell phase detector . . . . . . . . . . . . . . . . . 149
Figure 3.22 VCO characteristics . . . . . . . . . . . . . . . . . . . . . 151
Figure 3.23 PLL response for different input signals . . . . . . . . . . 152
Figure 3.24 Type I PLL . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 3.25 Time variations depicting a frequency step . . . . . . . . . 154
Figure 3.26 The signal vanishes in short step . . . . . . . . . . . . . . 155
Figure 3.27 Desired signals . . . . . . . . . . . . . . . . . . . . . . . 155
Figure 3.28 Cross-coupled oscillator . . . . . . . . . . . . . . . . . . 156
Figure 3.29 Characteristics of the nonlinear MOSFET varactor . . . . 156
Figure 3.30 Frequency modulation and demodulation with PLL . . . . 157
Figure 3.31 VCO characteristics for a 10.7 MHz carrier . . . . . . . . 157
Figure 3.32 Frequency synthesizer block diagram for a frequency
modulation scheme . . . . . . . . . . . . . . . . . . . . . 158
Figure 3.33 System- and circuit-level implementation of frequency
modulation using a PLL . . . . . . . . . . . . . . . . . . 160
Figure 3.34 System-level implementation of PFD using two D flip-flops
and an AND gate . . . . . . . . . . . . . . . . . . . . . . 162
Figure 3.35 A typical charge-pump circuit using two current sources and
two switches . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 3.36 Operation of the charge-pump circuit under the excitation
of the PFD . . . . . . . . . . . . . . . . . . . . . . . . . 162
Figure 3.37 Type-II PLL block diagram including a PFD, a charge pump,
and a VCO . . . . . . . . . . . . . . . . . . . . . . . . . 163
Figure 3.38 Type I frequency synthesizer . . . . . . . . . . . . . . . . 166
Figure 3.39 Frequency modulator using a PLL . . . . . . . . . . . . . 166
Figure 3.40 The equivalent circuit of the part of the PLL used as the
FM modulator . . . . . . . . . . . . . . . . . . . . . . . . 167
Figure 3.41 Frequency synthesizer using type I PLL . . . . . . . . . . 167
Figure 3.42 MOS-based FM modulator/VCO . . . . . . . . . . . . . . 168
Figure 4.1 Basic mixer schematic with a single diode . . . . . . . . . 169
Figure 4.2 Input and output signals for Figure 4.1 . . . . . . . . . . . 170
Figure 4.3 Polynomial model for a nonlinear current source . . . . . 171
List of Figures xxv

Figure 4.4 Representation of mixing products for two input adjacent

channels . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 4.5 Intercept point of first harmonic and third-order
intermodulation . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 4.6 An approximation of a mixer with three input signals . . . 175
Figure 4.7 Input/output signal spectrums at the mixer ports . . . . . . 176
Figure 4.8 IM3 product problem in DAMPS . . . . . . . . . . . . . . 176
Figure 4.9 The spectrum of signals for the mixer of Fig. 4.8 . . . . . 177
Figure 4.10 Implementation of signals’ sum to be applied to a
mixer input . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 4.11 Interpolation of the output signal and the intermodulation
curves to obtain third-order intercept point (IIP3 ) . . . . . 178
Figure 4.12 Typical heterodyne conventional receiver block diagram . 179
Figure 4.13 Typical conventional quadrature transmitter block diagram 179
Figure 4.14 Wide-band spectrum standard for GSM and ACPR effect . 179
Figure 4.15 A typical bipolar transistor mixer in its active region . . . 180
Figure 4.16 The normalized large-signal transconductance of a single
bipolar transistor stage as a function of the normalized local
oscillator voltage . . . . . . . . . . . . . . . . . . . . . . 182
Figure 4.17 The normalized conversion conductance of a single
bipolar transistor stage as a function of normalized
input LO voltage . . . . . . . . . . . . . . . . . . . . . . 183
Figure 4.18 Different mixer circuit topologies, (a) bipolar unbalanced,
(b) bipolar balanced, (c) bipolar double-balanced, (d) MOS
unbalanced, (e) MOS balanced, and (f) MOS
double-balanced . . . . . . . . . . . . . . . . . . . . . . 184
Figure 4.19 Passive switching mixer circuits . . . . . . . . . . . . . . 186
Figure 4.20 Differential implementation of passive mixer circuits . . . 186
Figure 4.21 Bipolar unbalanced mixer functioning on the LO switching
basis (downconverter) . . . . . . . . . . . . . . . . . . . . 188
Figure 4.22 A rough approximation of the output signal of Figure 4.21 188
Figure 4.23 Bipolar unbalanced mixer based on time-varying
transconductance (upconverter) . . . . . . . . . . . . . . . 189
Figure 4.24 Single-balanced bipolar mixer . . . . . . . . . . . . . . . 191
Figure 4.25 Double-balanced mixer . . . . . . . . . . . . . . . . . . . 192
Figure 4.26 Mixer circuit . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 4.27 Employing a band-pass filter to suppress input blockers in
order to avoid the resulting IM3 component . . . . . . . . 193
Figure 4.28 Typical matching circuit for a mixer, step-up capacitive input
matching, and step-down capacitive output matching . . . 194
Figure 4.29 Applying two large signals to a nonlinear device (bipolar or
MOS transistors) to compute the compression point and the
third-order intercept point . . . . . . . . . . . . . . . . . 195
Figure 4.30 Output current of the amplifier versus its input signals’
amplitudes . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 4.31 The locus of the saturation voltages in the VS -V1 plane . . . 198
xxvi List of Figures

Figure 4.32 A typical differential bipolar stage and its corresponding

nonlinear transfer characteristics . . . . . . . . . . . . . . 200
Figure 4.33 A typical differential MOS stage and its corresponding
nonlinear transfer characteristics . . . . . . . . . . . . . . 201
Figure 4.34 Input–output voltage characteristic of MOS and
bipolar devices . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 4.35 Degeneration resistor implementation to achieve
linear behavior . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 4.36 The transfer characteristics of a differential stage with
degeneration resistors . . . . . . . . . . . . . . . . . . . . 204
Figure 4.37 The transfer characteristics of a differential MOS stage with
degeneration resistors . . . . . . . . . . . . . . . . . . . . 205
Figure 4.38 Degeneration resistor implementation without
voltage-headroom usage . . . . . . . . . . . . . . . . . . 205
Figure 4.39 Single-balanced mixer . . . . . . . . . . . . . . . . . . . 206
Figure 4.40 Single-balanced mixer . . . . . . . . . . . . . . . . . . . 207
Figure 4.41 MOS double-balanced mixer . . . . . . . . . . . . . . . . 208
Figure 4.42 Typical GPS receiver architecture and the neighboring
interfering signals . . . . . . . . . . . . . . . . . . . . . . 210
Figure 4.43 Single-balanced differential pair mixer . . . . . . . . . . . 214
Figure 4.44 Single-transistor mixer with corresponding matching
circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 4.45 Gilbert cell double-balanced mixer . . . . . . . . . . . . . 215
Figure 4.46 Gilbert cell double-balanced mixer with a degenerative
resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 4.47 Differential pair MOS balanced mixer . . . . . . . . . . . 216
Figure 4.48 Gilbert cell double-balanced mixer with input matching . . 217
Figure 4.49 A matched Gilbert cell double-balanced mixer to test
the IIP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 4.50 LO bias implementation, (a) practical implementation,
and (b) LO and bias application in the simulations . . . . . 218
Figure 4.51 IIP3 point determination through computer simulation . . 218
Figure 4.52 The receiver chain intended for IM3 computation . . . . . 219
Figure 4.53 Receiver chain for determination of the overall noise
figure and overall IIP3 . . . . . . . . . . . . . . . . . . . 220
Figure 4.54 A mixer used as a synchronous detector . . . . . . . . . . 220
Figure 4.55 A transconductance harmonic mixer . . . . . . . . . . . . 221
Figure 4.56 A switching upconverting mixer . . . . . . . . . . . . . . 221
Figure 4.57 A downconverting mixer using a series nonlinear device . 222
Figure 4.58 A harmonic upconverting mixer . . . . . . . . . . . . . . 222
Figure 5.1 Sinusoidal AM-modulated signal . . . . . . . . . . . . . . 224
Figure 5.2 Typical baseband and AM modulator output spectrum . . . 224
Figure 5.3 Simple AM demodulator . . . . . . . . . . . . . . . . . . 225
Figure 5.4 The concept of AM demodulation using a diode with
R–C circuit . . . . . . . . . . . . . . . . . . . . . . . . . 225
Figure 5.5 A failure-to-follow distortion once the modulation
index is at its maximum . . . . . . . . . . . . . . . . . . . 225
List of Figures xxvii

Figure 5.6 Implementation of the AM modulator . . . . . . . . . . . 226

Figure 5.7 The input baseband spectrum and the output spectrum
of an AM modulator (the two sidebands and the carrier are
distinct in the output spectrum) . . . . . . . . . . . . . . . 228
Figure 5.8 Block diagram implementation of the SSBSC AM signal . 229
Figure 5.9 Block diagram implementation of the SSBSC AM signal
with phase shifters at the carrier frequency . . . . . . . . . 230
Figure 5.10 Circuit implementation of the DSBSC AM modulator . . . 231
Figure 5.11 AM signal demodulator . . . . . . . . . . . . . . . . . . . 231
Figure 5.12 AM demodulation alongside low-pass filtering of
the output . . . . . . . . . . . . . . . . . . . . . . . . . . 233
Figure 5.13 Synchronous AM demodulation using a limiting
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 234
Figure 5.14 64-QAM signal constellation . . . . . . . . . . . . . . . . 235
Figure 5.15 Signal constellation of BPSK modulation and its
corresponding time-domain waveform . . . . . . . . . . . 236
Figure 5.16 Constellation of QPSK modulation . . . . . . . . . . . . . 236
Figure 5.17 Signal waveform in QPSK modulation and the corresponding
assigned bits . . . . . . . . . . . . . . . . . . . . . . . . 237
Figure 5.18 16 − QAM constellation . . . . . . . . . . . . . . . . . . 237
Figure 5.19 64 − QAM constellation . . . . . . . . . . . . . . . . . . 238
Figure 5.20 Circuit implementation of a BPSK modulator using a
differential pair . . . . . . . . . . . . . . . . . . . . . . . 238
Figure 5.21 Implementation of a QPSK generator . . . . . . . . . . . 239
Figure 5.22 QPSK receiver architecture . . . . . . . . . . . . . . . . . 240
Figure 5.23 Direct-conversion transmitter architecture . . . . . . . . . 241
Figure 5.24 Phase and amplitude error effect in QPSK modulation
due to noise, in two cases, low SNR and high SNR . . . . 241
Figure 5.25 Quadrature receiver’s architecture . . . . . . . . . . . . . 242
Figure 5.26 Rectangular constellation distortion due to ∆G/2
gain mismatch in each path of the quadrature receiver . . . 242
Figure 5.27 Parallelogram constellation distortion due to ∆ϕ/2 phase
mismatch in each path of quadrature receiver . . . . . . . 242
Figure 5.28 Signals in quadrature phase modulation, (a) a QPSK
signal pair with a 180◦ phase change, and (b) an OQPSK
signal pair where the 180◦ phase shift is avoided . . . . . 243
Figure 5.29 Frequency response of a Gaussian filter (magnitude
and phase) . . . . . . . . . . . . . . . . . . . . . . . . . . 243
Figure 5.30 GMSK transmitter architecture . . . . . . . . . . . . . . . 244
Figure 5.31 The comparison of the spectra of QPSK, OQPSK,
and GMSK signals . . . . . . . . . . . . . . . . . . . . . 244
Figure 5.32 Quadrature FM demodulator . . . . . . . . . . . . . . . . 245
Figure 5.33 Zero IF quadrature receiver . . . . . . . . . . . . . . . . . 246
Figure 5.34 Zero IF synchronous detector . . . . . . . . . . . . . . . . 247
Figure 5.35 The input AM signal waveform (v2 ) . . . . . . . . . . . . 247
Figure 5.36 QPSK 90 MHz trnsmitter/receiver system . . . . . . . . . 251
Figure 5.37 Double-balanced synchronous detector . . . . . . . . . . . 251
xxviii List of Figures

Figure 5.38 A typical 16QAM modulator using two balanced analog

multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . 252
Figure 5.39 A balanced MOS differential pair AM modulator . . . . . 253
Figure 5.40 AM Ge envelope detector . . . . . . . . . . . . . . . . . . 253
Figure 5.41 Self-carrier generating balanced synchronous
AM detector . . . . . . . . . . . . . . . . . . . . . . . . . 254
Figure 5.42 A double-balanced amplitude modulator . . . . . . . . . . 254
Figure 5.43 An envelope detector with the input RF amplifier . . . . . 255
Figure 6.1 (a) A typical limiting differential amplifier. (b) Input–output
characteristics of a limiting amplifier . . . . . . . . . . . . 258
Figure 6.2 Input–output characteristics of an AGC . . . . . . . . . . 258
Figure 6.3 Magnitude of frequency response of the cascaded
amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . 260
Figure 6.4 Offset voltage at the input of the limiting amplifiers . . . . 261
Figure 6.5 Offset cancellation loop with negative feedback, where
R0 = 300 Ω, C1 = 0.1 µF, and R1 = 20 kΩ . . . . . . . . . 261
Figure 6.6 Offset cancellation loop with active negative feedback,
where R0 = 50 Ω . . . . . . . . . . . . . . . . . . . . . . 262
Figure 6.7 Offset cancellation loop with negative active feedback
and two differential inputs, where R0 = 50 Ω . . . . . . . 263
Figure 6.8 Offset cancellation loop with negative feedback and use
of a Miller capacitance (instead of a large capacitance)
in the feedback amplifier . . . . . . . . . . . . . . . . . . 264
Figure 6.9 Automatic gain control structure . . . . . . . . . . . . . . 265
Figure 6.10 Variable-gain stage with gm variation, (a) Through tail
current variations, and (b) Through second gate voltage
variations . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Figure 6.11 Variable-gain stage with (a) load resistor, and
(b) series feedback . . . . . . . . . . . . . . . . . . . . . 267
Figure 6.12 Implementation of automatic gain control circuit
using multiple switches . . . . . . . . . . . . . . . . . . . 267
Figure 6.13 (a) Single-ended peak detector and (b) Full-wave peak
detector . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Figure 6.14 The implementation of a peak detector, (a) single-ended
peak detector, and (b) full-wave peak detector . . . . . . . 269
Figure 6.15 The configuration of a signal strength indicator . . . . . . 270
Figure 6.16 Typical indicator output as a function of the input
RF power . . . . . . . . . . . . . . . . . . . . . . . . . . 270
Figure 6.17 Amplifier implementation with gain control based on
a multiplier . . . . . . . . . . . . . . . . . . . . . . . . . 271
Figure 6.18 Modified amplifier with gain control based on a multiplier 271
Figure 6.19 Automatic gain control circuit without degeneration resistors
(without the high-pass response) . . . . . . . . . . . . . . 272
Figure 6.20 fT doubler, (a) single-ended, and (b) differential
implementation . . . . . . . . . . . . . . . . . . . . . . . 274
Figure 6.21 Inductive peaking in the common-source amplifier
with the corresponding frequency response . . . . . . . . 275
List of Figures xxix

Figure 6.22 (a) Passive (spiral) inductor model. (b) The active
MOS inductor topology and its equivalent circuit . . . . . 275
Figure 6.23 Decreasing device input capacitance via series feedback . 277
Figure 6.24 The possible feedback leakage path and the oscillation
issue in multistage amplifiers . . . . . . . . . . . . . . . . 278
Figure 7.1 A generic RF front-end . . . . . . . . . . . . . . . . . . . 284
Figure 7.2 The model of a high-frequency amplifier . . . . . . . . . . 284
Figure 7.3 The phase and gain response of a lossless T-line . . . . . . 285
Figure 7.4 Impedance transformation property of the T-line, (a) The line
terminated by 50 Ω exhibits an impedance of 50 Ω through-
out the line, (b) The line terminated by an unmatched load
can exhibit both an inductive or capacitive impedance seen
through it depending on the position, (c) Transformation of
a short circuit to an open circuit using a quarter wavelength
T-line, and (d) Load impedance inversion using a quarter
wavelength T-line . . . . . . . . . . . . . . . . . . . . . . 285
Figure 7.5 The lumped model of a differential transmission line for a
differential length ∆Z . . . . . . . . . . . . . . . . . . . . 286
Figure 7.6 A transmission line divided into consecutive differential
lumped sections . . . . . . . . . . . . . . . . . . . . . . . 289
Figure 7.7 Characteristic impedance of a line . . . . . . . . . . . . . 292
Figure 7.8 A terminated transmission line . . . . . . . . . . . . . . . 294
Figure 7.9 The terminated T-line . . . . . . . . . . . . . . . . . . . . 296
Figure 7.10 A terminated T-line to the intrinsic impedance . . . . . . . 298
Figure 7.11 A short-terminated T-line . . . . . . . . . . . . . . . . . . 299
Figure 7.12 The input impedance of a short-terminated T-line . . . . . 299
Figure 7.13 The input impedance of an open-terminated T-line . . . . 300
Figure 7.14 The input impedance of an open-terminated T-line . . . . 301
Figure 7.15 A T-line with its load and source impedances . . . . . . . 301
Figure 7.16 Equivalent model of Figure 7.15 for input impedance
calculation . . . . . . . . . . . . . . . . . . . . . . . . . 302
Figure 7.17 (a) Demonstration of a T-line with its load and source
impedances, and (b) transmission of the wave back and forth
on the line . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Figure 7.18 Implementation of a narrowband inductor and a narrowband
capacitor using a short and an open-terminated line . . . . 305
Figure 7.19 (a) Implementation of a parallel inductor and a parallel capac-
itor using short-circuit and open-circuit stubs, respectively,
(b) Implementation of a series inductor using a short-length
high-impedance transmission line, (c) Implementation of a
parallel capacitor using a short-length low-impedance stub,
all in microstrip technology . . . . . . . . . . . . . . . . . 306
Figure 7.20 A loaded resonant circuit . . . . . . . . . . . . . . . . . . 307
Figure 7.21 The effect of source impedance on Q . . . . . . . . . . . . 308
Figure 7.22 The effect of inductance on Q . . . . . . . . . . . . . . . 308
Figure 7.23 Output power characteristic for a DC circuit . . . . . . . . 308
Figure 7.24 The general case of maximum power transmission to the load 309
xxx List of Figures

Figure 7.25 Four possible variants of an L-section matching network . 309

Figure 7.26 An example of an L-section matching network . . . . . . 309
Figure 7.27 The equivalent circuit of the network shown in Figure 7.26
at the operating frequency . . . . . . . . . . . . . . . . . 310
Figure 7.28 Impedance matching by adding an inductor . . . . . . . . 310
Figure 7.29 The equivalent circuit of a reactance with a limited quality
factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311
Figure 7.30 The definition of Q in a matching network . . . . . . . . . 312
Figure 7.31 An L-section matching network . . . . . . . . . . . . . . 312
Figure 7.32 Impedance matching at the source and the load . . . . . . 313
Figure 7.33 The proper matching network for complex source and
complex load matching . . . . . . . . . . . . . . . . . . . 314
Figure 7.34 Impedance matching using resonance . . . . . . . . . . . 314
Figure 7.35 Impedance matching network using a resonating load . . . 315
Figure 7.36 A part of the matching network . . . . . . . . . . . . . . . 315
Figure 7.37 The designed matching network . . . . . . . . . . . . . . 316
Figure 7.38 The final matching network in Example 7.11 . . . . . . . 316
Figure 7.39 π and T matching networks . . . . . . . . . . . . . . . . 316
Figure 7.40 π matching network . . . . . . . . . . . . . . . . . . . . 317
Figure 7.41 The right-hand equivalent half-circuit of the π matching
network . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
Figure 7.42 The left-hand equivalent half-circuit of the π matching
network . . . . . . . . . . . . . . . . . . . . . . . . . . . 318
Figure 7.43 π matching network . . . . . . . . . . . . . . . . . . . . 318
Figure 7.44 Low-pass version of the π matching network . . . . . . . 319
Figure 7.45 Variants of the matching network with inductors and
capacitors in a π structure . . . . . . . . . . . . . . . . . 319
Figure 7.46 T matching network . . . . . . . . . . . . . . . . . . . . 320
Figure 7.47 The left-hand equivalent half-circuit of the T matching
network . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 7.48 The right-hand equivalent half-circuit of the T matching
network . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Figure 7.49 Variants of T matching network . . . . . . . . . . . . . . 322
Figure 7.50 Constant-resistance and constant-reactance circles within
|Γ| ≤ 1 plane . . . . . . . . . . . . . . . . . . . . . . . . 324
Figure 7.51 Representation of the two impedances in the Smith chart . 325
Figure 7.52 Representation of the effect of adding a series capacitive
reactance in the Smith chart . . . . . . . . . . . . . . . . 326
Figure 7.53 The complete Smith chart . . . . . . . . . . . . . . . . . 328
Figure 7.54 The Smith chart rules and applications . . . . . . . . . . . 329
Figure 7.55 Matching on the Smith chart . . . . . . . . . . . . . . . . 330
Figure 7.56 The load impedance of Example 7.12 . . . . . . . . . . . 330
Figure 7.57 Representation of the load admittance on the Smith chart . 331
Figure 7.58 Matching based on an L-section . . . . . . . . . . . . . . 331
Figure 7.59 Adding an inductor to the load . . . . . . . . . . . . . . . 331
Figure 7.60 Adding a capacitor to the load to reach the point 3 from
point 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332
List of Figures xxxi

Figure 7.61 The matching network in Example 7.13 . . . . . . . . . . 333

Figure 7.62 The steps of matching in the circuit shown in Figure 7.61 . 335
Figure 7.63 Impedance matching using three sections of quarter wave
transformers . . . . . . . . . . . . . . . . . . . . . . . . . 335
Figure 7.64 The contours of impedance matching on the Smith chart
using three sections of quarter wave transformers . . . . . 336
Figure 7.65 Half-circle contour showing the quarter wave impedance
transformation on the Smith chart . . . . . . . . √ . . . . . 337
Figure 7.66 The impedance transformation contours and Q = 22 locus
on the Smith chart . . . . . . . . . . . . . . . . . . . . . 337
Figure 7.67 The lumped matching network at 1 GHz . . . . . . . . . . 338
Figure 7.68 The frequency response and the bandwidth of the matching
network (ADS simulation result) . . . . . . . . . . . . . . 339
Figure 7.69 A transmission line with the source and the load
terminations . . . . . . . . . . . . . . . . . . . . . . . . . 341
Figure 7.70 The circuit model for the amplifier . . . . . . . . . . . . . 341
Figure 7.71 The circuits for input impedance evaluation . . . . . . . . 342
Figure 7.72 Two possible matching circuits for the specified load . . . 342
Figure 7.73 The λ /8 single stub matching for a complex source
impedance . . . . . . . . . . . . . . . . . . . . . . . . . . 342
Figure 7.74 The matching circuit for the ceramic filter . . . . . . . . . 343
Figure 7.75 The single stub matching circuit . . . . . . . . . . . . . . 344
Figure 7.76 The double stub matching circuit . . . . . . . . . . . . . . 344
Figure 7.77 Determination of the delivered power to the load through
a T-line . . . . . . . . . . . . . . . . . . . . . . . . . . . 344
Figure 7.78 The characteristic impedance determination through the
current and the voltage phasors . . . . . . . . . . . . . . . 345
Figure 7.79 The circuit for determination of the incident and the
reflected voltage phasors . . . . . . . . . . . . . . . . . . 345
Figure 7.80 The circuit for reflection coefficient computation . . . . . 346
Figure 7.81 The circuit for L-section impedance matching . . . . . . . 346
Figure 7.82 The π matching network . . . . . . . . . . . . . . . . . . 346
Figure 7.83 The circuit for transient voltage determination . . . . . . . 346
Figure 7.84 The circuit for impedance inversion . . . . . . . . . . . . 347
Figure 8.1 A generic two-port network . . . . . . . . . . . . . . . . 350
Figure 8.2 A resistive two-port and Z-parameters measurement . . . . 350
Figure 8.3 Two port S-parameter matrix concept . . . . . . . . . . . 351
Figure 8.4 Illustration of a 5-port network . . . . . . . . . . . . . . . 352
Figure 8.5 A resistive two-port network . . . . . . . . . . . . . . . . 353
Figure 8.6 A low-pass filter for S-parameter
calculation . . . . . . . . . . . . . . . . . . . . . . . . . 354
Figure 8.7 An oscillator with source impedance for S-parameter
calculation . . . . . . . . . . . . . . . . . . . . . . . . . 355
Figure 8.8 Conceptual block diagram of a network analyzer . . . . . 358
Figure 8.9 Calibration circuits needed in the calibration process for
a network analyzer to measure the two-port S-parameters
of the DUT . . . . . . . . . . . . . . . . . . . . . . . . . 359
xxxii List of Figures

Figure 8.10 S-parameter measurement . . . . . . . . . . . . . . . . . 360

Figure 8.11 The proposed model for the Device Under Test . . . . . . 361
Figure 8.12 Impedance matching on Smith chart . . . . . . . . . . . . 362
Figure 8.13 The proposed equivalent circuit for the measured
S-parameters of the transistor . . . . . . . . . . . . . . . . 363
Figure 8.14 The effect of transmission line on the S-parameters . . . . 364
Figure 8.15 Small-signal model of the transistor for S11 calculation . . 365
Figure 8.16 The plot of S11 of the transistor model from 50 MHz to
1000 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . 366
Figure 8.17 Equivalent circuit for S22 modeling . . . . . . . . . . . . . 367
Figure 8.18 The amplitude and phase of S22 of the transistor . . . . . . 367
Figure 8.19 The circuit used in Example 8.10 . . . . . . . . . . . . . . 368
Figure 8.20 The input reflection coefficient, depicted on the Smith chart
0
[(1): S11 , (2): S11 ] . . . . . . . . . . . . . . . . . . . . . . 368
Figure 8.21 The output reflection coefficient, depicted on the Smith chart
0
[(1): S22 , (2): S22 ] . . . . . . . . . . . . . . . . . . . . . . 369
Figure 8.22 The resistive/transmission line circuit for S-parameters deter-
mination . . . . . . . . . . . . . . . . . . . . . . . . . . . 372
Figure 8.23 The circuit model for a transistor to compute S11 . . . . . 372
Figure 8.24 The input circuit for a BJT amplifier . . . . . . . . . . . . 372
Figure 8.25 Two T-section attenuator circuits . . . . . . . . . . . . . . 373
Figure 8.26 The transistors’ input equivalent circuits . . . . . . . . . . 373
Figure 8.27 The equivalent circuit of the transistor to determine the
S-parameters . . . . . . . . . . . . . . . . . . . . . . . . 373
Figure 8.28 The RC section for S-parameters’ determination . . . . . . 374
Figure 8.29 The delay cell for S-parameters’ determination . . . . . . 374
Figure 8.30 The transistor S-parameters for de-embedding . . . . . . . 374
Figure 8.31 The cascaded chain of three unilateral amplifiers . . . . . 375
Figure 8.32 A pair of balanced amplifiers cascaded by two 90◦ , 3 dB
couplers . . . . . . . . . . . . . . . . . . . . . . . . . . . 375
Figure 9.1 Illustration of the general case of a microwave amplifier with
input and output matching circuits . . . . . . . . . . . . . 378
Figure 9.2 Input stability circles on the load plane Smith chart for five
cases (the shaded areas correspond to the stable region), (a)
for |S11 | > 1 and conditional stability, (b) for |S11 | < 1, the
stability circle intersecting the chart while not comprising
the chart center, and consequently, conditional stability, (c)
for |S11 | < 1, the stability circle intersecting the chart while
comprising the chart center, and consequently, conditional
stability, (d) for |S11 | < 1, the stability circle does not in-
tersect the chart, and consequently, unconditional stability,
and (e) for |S11 | < 1, the stability circle comprises the whole
chart, and consequently, unconditional stability . . . . . . 382
List of Figures xxxiii

Figure 9.3 Output stability circles on the source plane Smith chart for
five cases (the shaded areas correspond to the stable region),
(a) for |S22 | > 1 and conditional stability, (b) for |S22 | < 1,
the stability circle intersecting the chart while not comprising
the chart center, and consequently, conditional stability, (c)
for |S22 | < 1, the stability circle intersecting the chart while
comprising the chart center, and consequently, conditional
stability, (d) for |S22 | < 1, the stability circle does not in-
tersect the chart and consequently, unconditional stability,
and (e) for |S22 | < 1, the stability circle comprises the whole
chart, and consequently, unconditional stability . . . . . . 383
Figure 9.4 Input and output reflection coefficients on the Smith chart . 388
Figure 9.5 Steps for input matching on the Smith chart . . . . . . . . 389
Figure 9.6 Steps for output matching on the Smith chart . . . . . . . 390
Figure 9.7 The overall matching network . . . . . . . . . . . . . . . 390
Figure 9.8 The load matching using a series capacitor and a parallel
inductor to achieve 9 dB gain . . . . . . . . . . . . . . . . 393
Figure 9.9 Source matching . . . . . . . . . . . . . . . . . . . . . . 394
Figure 9.10 The input and output matching networks for complex source
and load impedances . . . . . . . . . . . . . . . . . . . . 395
Figure 9.11 (a) The input stability circle and the corresponding source
reflection coefficient. (b) The output stability circle and the
chosen load reflection coefficient . . . . . . . . . . . . . . 397
Figure 9.12 The noise model of a two-port amplifier . . . . . . . . . . 399
Figure 9.13 Model for noise figure calculation in a cascade of
two stages . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Figure 9.14 Constant NF contours on the plane of input reflection
coefficient . . . . . . . . . . . . . . . . . . . . . . . . . . 405
Figure 9.15 Constant NF and the normalized available power gain
contours on the input reflection coefficient plane at 6 GHz 406
Figure 9.16 Input matching on the Smith chart . . . . . . . . . . . . . 407
Figure 9.17 Output matching on the Smith chart . . . . . . . . . . . . 408
Figure 9.18 The overall matching network . . . . . . . . . . . . . . . 409
Figure 9.19 Constant power gain and constant NF contours for the given
transistor on the Smith chart . . . . . . . . . . . . . . . . 411
Figure 9.20 Equivalent circuit model of the transistor in Example 9.8 . 412
Figure 9.21 The π matching network employed in Example 9.8 . . . . 412
Figure 9.22 The amplifier circuit for determining various power gains . 416
Figure 9.23 Cascaded amplifiers to determine the overall S-parameters 416
Figure 9.24 A transistor cascaded by either of series or parallel
resistances . . . . . . . . . . . . . . . . . . . . . . . . . . 417
Figure 9.25 A transistor amplifier with corresponding load and source
impedances and the bias circuitry . . . . . . . . . . . . . 417
Figure 9.26 The Smith chart to design an amplifier with specific NF
and GA . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
Figure 9.27 The cascade amplifiers/mixer for determination of the overall
noise figure . . . . . . . . . . . . . . . . . . . . . . . . . 419
xxxiv List of Figures

Figure 9.28 A cascade of amplifiers for the output power calculations . 419
Figure 9.29 The transistor MOS amplifier for input and output matching 419
Figure 9.30 The two-stage amplifier to be designed using a BGU7007
internally matched LNA . . . . . . . . . . . . . . . . . . 420
Figure 9.31 The constant noise and the constant available gain circles at
the source plane of the transistor at 4 GHz . . . . . . . . . 421
Figure 9.32 The equivalent circuit of a FET transistor and the associated
matching circuits . . . . . . . . . . . . . . . . . . . . . . 422
Figure 9.33 A cascode MOS stage amplifier . . . . . . . . . . . . . . 422
Figure 9.34 The low-noise amplifier with the corresponding input and
output matching circuits . . . . . . . . . . . . . . . . . . 423
Figure 9.35 The measured source admittances for a noise figure F = 3
(source admittance plane) . . . . . . . . . . . . . . . . . . 423
Figure 10.1 A graphical representation of the compromise between the
linearity and the efficiency in a typical power amplifier . . 426
Figure 10.2 Typical compression curve of a power amplifier . . . . . . 427
Figure 10.3 Compression curve of the PAE of an amplifier . . . . . . . 428
Figure 10.4 Power amplifier followed by a matching network . . . . . 428
Figure 10.5 PDF of the transmitted power of the PA for a mobile set
in an urban or suburban area . . . . . . . . . . . . . . . . 429
Figure 10.6 The effect of the TX-band noise at the receiver in a
full-duplex system . . . . . . . . . . . . . . . . . . . . . 430
Figure 10.7 A PA with the PA driver and the interstage matching
networks . . . . . . . . . . . . . . . . . . . . . . . . . . 431
Figure 10.8 Typical compression of the output power versus the input
power of a PA . . . . . . . . . . . . . . . . . . . . . . . . 431
Figure 10.9 Typical gain compression in a PA . . . . . . . . . . . . . 431
Figure 10.10 (a) P1dB and IP3 points in a nonlinear system, (b) Output
spectrum in a nonlinear system with a two-tone input . . . 432
Figure 10.11 An amplifier with a nonlinear capacitance at its load . . . 433
Figure 10.12 A typical AM to PM characteristics for a nonlinear
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 434
Figure 10.13 Output spectrum of Figure 10.11 due to PM conversion,
(a) k 1, and (b) k < 1 or k ≈ 1 . . . . . . . . . . . . . . 434
Figure 10.14 Generation of undesired harmonic and intermodulation com-
ponents at the output of a nonlinear PA . . . . . . . . . . . 435
Figure 10.15 A nonlinear tuned amplifier corresponding to its nonlinear
transconductance . . . . . . . . . . . . . . . . . . . . . . 436
Figure 10.16 Spectral regrowth in a nonlinear PA as seen in the frequency
domain . . . . . . . . . . . . . . . . . . . . . . . . . . . 437
Figure 10.17 Spectral regrowth in a nonlinear PA, single tone shown in
the time domain . . . . . . . . . . . . . . . . . . . . . . . 437
Figure 10.18 ACPR definition in CDMA (IS-95) standard . . . . . . . . 438
Figure 10.19 Degradation of in-band SNR due to nonlinearity . . . . . . 439
Figure 10.20 Representation of error vector magnitude (EVM) in a
sampling I − Q constellation . . . . . . . . . . . . . . . . 440
List of Figures xxxv

Figure 10.21 A comparison of the input and the output constellation for
a 16-QAM modulation for a nonlinear power amplifier in
between . . . . . . . . . . . . . . . . . . . . . . . . . . . 440
Figure 10.22 Class A power amplifier . . . . . . . . . . . . . . . . . . 441
Figure 10.23 (a) Quiescent point determination in class A power amplifiers
and (b) Drain voltage, drain current, and device power loss
of the circuit depicted in Figure 10.22 . . . . . . . . . . . 442
Figure 10.24 A class B power amplifier with the corresponding output
current waveform . . . . . . . . . . . . . . . . . . . . . . 443
Figure 10.25 (a) The quiescent operating point and the corresponding
waveforms for the class B PA and (b) The output current, the
output voltage, and the power loss waveforms for a single-
device class B power amplifier . . . . . . . . . . . . . . . 444
Figure 10.26 A class B push–pull power amplifier with the output
current shown as a summation of the positive and the negative
half-cycle currents . . . . . . . . . . . . . . . . . . . . . 445
Figure 10.27 Class AB PA’s quiescent point and the corresponding current
waveform . . . . . . . . . . . . . . . . . . . . . . . . . . 446
Figure 10.28 A class C power amplifier and its corresponding output
current waveform . . . . . . . . . . . . . . . . . . . . . . 447
Figure 10.29 The quiescent point of a class C amplifier and the
corresponding output current, output voltage, and the
power loss waveforms . . . . . . . . . . . . . . . . . . . 447
Figure 10.30 The output current waveforms alongside the efficiencies
and the power capabilities corresponding to different
classes of power amplifiers as a function of the conduction
angle, α . . . . . . . . . . . . . . . . . . . . . . . . . . . 449
Figure 10.31 A typical class D power amplifier topology and the
corresponding voltage and current waveforms . . . . . . . 449
Figure 10.32 A typical circuit topology and current waveforms of a
class 1/D power amplifier . . . . . . . . . . . . . . . . . . 451
Figure 10.33 A typical class E power amplifier topology and the
corresponding voltage and current waveforms . . . . . . . 452
Figure 10.34 A typical class F power amplifier topology and the
corresponding voltage and current waveforms . . . . . . . 453
Figure 10.35 A typical class F power amplifier topology using a
quarter-wavelength transmission line . . . . . . . . . . . . 453
Figure 10.36 Block diagram of a class S power amplifier and its
corresponding waveforms . . . . . . . . . . . . . . . . . 454
Figure 10.37 A typical class sinusoidal to PWM signal converter . . . . 454
Figure 10.38 Different linearization methods in power amplifiers . . . . 456
Figure 10.39 A typical output power versus input power curve in decibels
depicting the input back-off and the output back-off with
respect to the saturation point . . . . . . . . . . . . . . . . 456
Figure 10.40 A schematic view of predistortion technique . . . . . . . 457
Figure 10.41 The block diagram of an adaptive predistorter technique . 457
xxxvi List of Figures

Figure 10.42 Amplitude and phase representation of a signal in the I–Q

plane . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458
Figure 10.43 Block diagram of linearization with polar feedback . . . . 458
Figure 10.44 Block diagram of linearization with Cartesian feedback . . 459
Figure 10.45 Block diagram of linearization with feedforward . . . . . 460
Figure 10.46 Block diagram of the LINC linearization method . . . . . 460
Figure 10.47 Block diagram of envelope elimination and restoration
linearization method . . . . . . . . . . . . . . . . . . . . 462
Figure 10.48 Pulse amplitude and width modulation circuit . . . . . . . 462
Figure 10.49 Block diagram of a switchable parallel amplifier array used
for power control . . . . . . . . . . . . . . . . . . . . . . 463
Figure 10.50 Block diagram of the handheld transceiver RF front-end . 465
Figure 10.51 The equivalent circuit of the MOS stage with a nonlinear
gate–source capacitance . . . . . . . . . . . . . . . . . . 466
Figure 10.52 A MOSFET class B or class C power amplifier with bias and
matching circuits . . . . . . . . . . . . . . . . . . . . . . 467
List of Tables

Table 1.1 Specifications of AMPS, GSM, and WiFi 802.11a/g . . . . 10

Table 2.1 Effective gain with input and output signal of a saturating
amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 2.2 The specifications of HC-49/U family of crystals . . . . . . 45
Table 2.3 Numerical values of the first four modified Bessel functions
of the first kind as a function of their argument . . . . . . . 53
Table 2.4 Values of large-signal Gm normalized to small-signal gm as
well as the conversion transconductances for the second and
the third harmonics . . . . . . . . . . . . . . . . . . . . . . 60
Table 2.5 Normalized values of the first and the third harmonic
voltages for the output tuned to either of the first or the third
harmonics . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 5.1 Gilbert cell applications (BJT) . . . . . . . . . . . . . . . . 234
Table 8.1 Conversion between two-port network matrices . . . . . . . 370
Table 9.1 Part of MRF962 datasheet . . . . . . . . . . . . . . . . . . 421
Table 10.1 Output power specifications for a few communication systems
in their different classes . . . . . . . . . . . . . . . . . . . 429
Table 10.2 Performance comparison among different classes of power
amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . 455

xxxvii
List of Abbreviations

2G (Mobile Network) Second Generation

4G LTE (Mobile Fourth Generation, Long Term Evolution
Network)
A/D Analog to Digital (converter)
AC Alternating Current
ACPR Adjacent Channel Power Ratio
ADC Analog to Digital Converter
ADS Advanced Design System (Software Tool)
AGC Automatic Gain Control
AM Amplitude Modulation
AMPS Advanced Mobile Phone System
APG Available Power Gain
BiCMOS Bipolar Complementary Metal Oxide Semiconductor
BJT Bipolar Junction Transistor
BPF Band-Pass Filter
BPSK Binary Phase Shift Keying
BW Bandwidth
C/I Carrier to Intermodulation (Ratio)
CB (Amplifier) Common-Base
CC (Amplifier) Common-Collector
CD (Amplifier) Common-Drain
CDMA Code-Division Multiple Access
CE (Amplifier) Common-Emitter
CG (Amplifier) Common-Gate
CMOS Complementary Metal Oxide Semiconductor
CS (Amplifier) Common-Source
DAMPS Digital Advanced Mobile Phone System
DC Direct Current

xxxix
xl List of Abbreviations

DCS Digital Cellular System

DDS Direct Digital Synthesis
DFF D Flip-Flop
DSBSC Double-SideBand Suppressed Carrier
DSP Digital Signal Processing
DUT Device Under Test
EER Envelope Elimination and Restoration
EIRP Effective Isotropic Radiated Power
ERP Effective Radiated Power
EVM Error Vector Magnitude
FFT Fast Fourier Transform
FLL Frequency-Locked Loop
FM Frequency Modulation
FSK Frequency-Shift Keying
GBW (GBWP) Gain Bandwidth Product
GF Gaussian Filter
GMSK Gaussian Minimum Shift Keying
GPS Global Positioning System
GSM Global System for Mobile communication, originally
Groupe Spécial Mobile
HPF High-Pass Filter
IF Intermediate Frequency
IIP3 Input third-order Intercept Point
IM Intermodulation
IM3 Third-order Intermodulation
IM5 Fifth-order Intermodulation
IMD Intermodulation Distortion
IP3 third-order Intercept Point
IS-95 Interim Standard 95
KCL Kirchhoff’s Current Law
KVL Kirchhoff’s Voltage Law
LINC Linear Amplification with Nonlinear Components
LNA Low Noise Amplifier
LO Local Oscillator
LPF Low-Pass Filter
LSB Lower SideBand
MOS Metal Oxide Semiconductor
MOSFET Metal Oxide Semiconductor Field Effect Transistor
NF Noise Figure
NMOS N-channel Metal Oxide Semiconductor
NPR Noise Power Ratio
OIP3 Output third-order Intercept Point
OPG Operational Power Gain
OQPSK Offset Quadrature Phase-Shift Keying
PA Power Amplifier
PAE Power Added Efficiency
PAR Peak to Average Ratio
List of Abbreviations xli

PCB Printed Circuit Board

PCS Personal Communications Service
PD Phase Detector
PDF Probability Density Function
PDM Pulse Deletion Modulation
PFD Phase Frequency Detector
PLL Phase-Locked Loop
PM Phase Modulation
PMOS P-channel Metal Oxide Semiconductor
PSD Power Spectral Density
PSK Phase-Shift Keying
PWM Pulse Width Modulation
QAM Quadrature Amplitude Modulation
QPSK Quadrature Phase-Shift Keying
RBSG Random Bit Sequence Generator
RF Radio Frequency
RFC Radio Frequency Choke
RSSI Received Signal Strength Indicator
RX Receiver
S/N Signal to Noise (Ratio)
S/P Serial to Parallel (Converter)
SMA SubMiniature version A (Connector)
SNR Signal-to-Noise Ratio
S-parameter Scattering Parameter
SSB Single-SideBand
SSBSC Single-SideBand Suppressed Carrier
SWR Standing Wave Ratio
TCXO Temperature Compensated Crystal Oscillator
TDMA Time Division Multiple Access
TEM Transverse ElectroMagnetic
THD Total Harmonic Distortion
T-line Transmission line
TPG Transducer Power Gain
TRX Transceiver
TX Transmitter
UHF Ultra High Frequency
USB Upper SideBand
VCO Voltage Controlled Oscillator
VGA Variable Gain Amplifier
VSWR Voltage Standing Wave Ratio
WCDMA Wideband Code Division Multiple Access
WiFi Wireless Fidelity
XOR Exclusive-OR
I
Part 1

1 The Amazing World of Wireless Systems .... 3

1.1 Introduction to Communication Circuits
1.2 Signal Levels and Rayleigh Fading
1.3 Calculation of the Sensitivity in Different Standards
1.4 Considerations in RF System Design
1.5 A Basic Understanding of Frequency Synthesizers
1.6 Conclusion
1.7 References and Further Reading
1.8 Problems

2 Oscillators . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 An Introduction to Oscillators
2.2 First Approach: Positive Feedback
2.3 Second Approach: Negative Resistance/Conductance
2.4 Oscillator Topologies
2.5 Crystal Oscillators
2.6 Calculation of the Oscillation Frequency Including
the Device Parasitics
2.7 Quality Factor of Reactive Elements
2.8 Nonlinear Behavior in Amplifiers
2.9 A Note on the Modified Bessel Functions of the First Kind
2.10 Large-Signal Transconductance and Harmonic Tuned
Amplifiers
2.11 Differential Bipolar Stage Large-Signal Transconductance
2.12 Inductive and Capacitive Dividers (Impedance Trans-
formers)
2.13 Analysis of Large-signal Loop Gain of an Oscillator
2.14 Colpitts Oscillator with Emitter Degeneration
2.15 MOS Stage Large-Signal Transconductance
2.16 Differential MOS Stage Large-Signal Transconductance
2.17 An Oscillator With a Hypothetical Model
2.18 A MOS Oscillator with Differential Gain Stage
2.19 Voltage-Controlled Oscillators
2.20 Special Topic: Nonlinear Device Fed by Sinusoidal Large-
Signal
2.21 Datasheet of a Voltage-Controlled Oscillator
2.22 Conclusion
2.23 References and Further Reading
2.24 Problems
ʌ/2
÷N VCO

÷M

1. The Amazing World of Wireless Systems

Wireless system and circuit design is one of the most interesting fields in electrical
engineering. From the economic point of view, wireless applications can be categorized
into cellular/smart phones, cordless phones, wireless data networks, sensor networks,
global positioning systems, and digital television broadcasting (terrestrial or satellite
based). A huge investment has already been made in this sector and experts project
further growth in the years to come. From the engineering point of view, the design
of wireless systems has different levels of abstraction which are relevant to radio
frequency (RF) antennas, wave propagation phenomena, RF and microwave circuit
design, evaluation of noise and intermodulation phenomena, digital modulation, coding,
and digital signal processing.

1.1 Introduction to Communication Circuits

Communication circuits is a comprehensive course which is normally taught for senior-
level undergraduate students. This course is an aggregation of a number of materials
including analog circuits, digital circuits, and digital signal processors. One of the
most important technological developments which have thoroughly changed lifestyle
of the people in the past two decades has been undoubtedly the inventions pertaining
to wireless systems. In this section, we discuss the design of a basic radio transceiver
(transmitter plus receiver) and analyze its system-level behavior. Furthermore, we focus
on the behavior of each building block of a reciever/transmitter chain and investigate
the mutual interactions of these building blocks on the overall signal performance.
Figure 1.1 shows a general transceiver block diagram. Here we briefly describe
the function of each block in the receiver and the transmitter. Through the following
chapters, we describe more precisely the functions and the analysis of each of the
blocks. It should be noted that as the frequency spectrum is crowded with many
transceivers for wireless applications ranging from AM/FM radios to TV transmitters,
cellular phones, air transport communications, police and fire stations, emergency
4 Chapter 1. The Amazing World of Wireless Systems

Receiver 5 7
I
1 2 3 4

Q
9 10 11 12 13
π/2 6 8
÷N VCO

15
PLL ÷M

14

16 18 Transmitter
I 26
21 22 23 24 25
20
+
Q
PLL
17 π/2 19

Figure 1.1: The general block diagram of a transceiver (radio transmitter plus
receiver).

aid radios, and WiFi networks, we need to select the frequency channel of interest
properly (i.e., reception) while interferences from all the other systems may be present.
Similarly, we must transmit a channel in the frequency allocated to an application
without causing excessive interference for other applications (i.e., transmission).
To start after the receiving antenna, we normally use a band-pass filter, block (1),
to preselect the spectrum of our application (e.g., the full 25 MHz bandwidth in the
869.2–893.8 MHz receive band of GSM). In block (2), the weakly received signal
will be amplified, usually by about 5 to 20 dB. This block normally consumes several
milli-amps of current because it is normally operating in class A and at the highest
frequency. In block (3), the amplified signal is downconverted through a mixer which
brings the signal to a lower frequency for further processing. Block (3) is symbolized
by a multiplication sign because the multiplication of two sinusoids is known to result
1.1 Introduction to Communication Circuits 5

in two new frequency components at the sum and the difference frequencies. Block
(4) is a band-pass filter that usually eliminates the undesired frequencies and selects
one of the two output signals. The frequency at block (4) is called the intermediate
frequency (IF). The channel selection in radios is performed by changing the local
oscillator (LO) frequency applied to block (3). The frequency from block (4) onward
is fixed, making its processing more simple. Blocks (5) and (6) downconvert the IF to
the baseband (in modern radios, where blocks (3) and (4) are suppressed and the RF
frequency is directly converted to the baseband, they are called zero-IF downconverter).
Blocks (7) and (8) are low-pass filters that are narrow enough to select the desired
information. The I and Q outputs go to a DSP (digital signal processing) block for
further digital processing intended for the display or the speaker for example. The
difference between filters (1), (4), (7), and (8) is that as we go through the receiving
chain, the filters become narrower, eliminating undesired frequency components. To
generate the LO signal used to derive block (3), we start with a crystal oscillator in
(9) whose frequency is usually between 5 MHz and 50 MHz. Block (10) divides the
crystal oscillator frequency by integer N to provide a lower stable frequency. Block
(13) is a voltage-controlled oscillator (VCO) whose output frequency is divided by
integer M in block (14). The resulting two frequencies out of block (10) and (14) are
compared in block (11). The output of block (11) is low-pass filtered by block (12)
which provides an error voltage to drive the VCO. The ratio M is digitally controlled.
When the loop is settled, the frequency of the VCO will be set to M/N of the frequency
of the crystal oscillator. We describe these blocks in more detail in the upcoming
chapters. It is important to note at this point that the first LO generates the signal
required by block (3) to select the desired channel. Block (15) is a fixed oscillator that
supplies the second LO for blocks (5) and (6).
For the transmitter portion in modern receivers, the baseband signals (either voice,
video, or data), after analog-to-digital conversion, form the I and Q signals which are
low-pass filtered by blocks (16) and (17). The outputs are upconverted by blocks (18)
and (19) mixers and summed in block (20). The resulting signal is band-pass filtered
in block (21) which is called the IF of the transmitter, then applied to a second mixer
of block (22), and is upconverted to the desired RF channel. Filter (23) is a band-pass
filter that selects the desired radio frequency and leaves out the undesired components.
Block (24) is a power amplifier that may amplify the output to the desired wattage.
Block (25) is the final stage filtering that will guarantee proper compliance with the
regulatory standard preventing undesired frequency components (here, the harmonics
or the intermodulation) for other systems or subscribers. The LO frequencies needed
for the transmit path might be generated by the same scheme as the receiver. The
difference between filters (16), (17), (21), (23), and (25) is that as we move forward in
the transmit path, they become wider to allow the transmission of the full spectrum of
the application to be used. For example, in GSM 850, the final filter (25) is a band-pass
filter in the range of 824.2 MHz–849.2 MHz.
As an example for a transceiver, we investigate the block diagram of the second
generation (2G) Digital AMPS system (DAMPS1 ). We have deliberately chosen this
system because it includes both analog and digital modulations. In this system, the
channel spacing is 30 kHz. The AMPS standard was fully analog, but evolved to
1 Digital advanced mobile phone system.
6 Chapter 1. The Amazing World of Wireless Systems

contain digital modulation in DAMPS. The analog modulation in this system is based
on frequency modulation with a maximum frequency deviation of 12 kHz (and given the
3 kHz baseband, consequently a total bandwidth of 30 KHz). The digital modulation
is based on π/4 QPSK. Considering a possible bit rate of about 60 kb/s in each
channel with a bandwidth of 30 KHz, three users can be present. The increased number
of subscribers is due to digital modulation and the time division among them, and
consequently sequential transmission of digital information. The procedure of sharing
one channel between three users is based on three time slots (time division multiple
access or TDMA). Each subscriber’s speech data are recorded and transmitted in
its time slot. This is accomplished at the cost of a maximum of three time slots
delay. The speech data are also compressed with advanced algorithms to reduce
its bit rate (to less than 20 kb/s). It is possible that the subscribers are in different
geographical positions, and as a result, we need a base station for management and
control of the three time slots allocated to different subscribers in different places. In
this system, the frequencies of the receive and the transmit have 45 MHz difference.
The frequency allocation for this system is in the range of 824 MHz−849 MHz which
is used for transmission of the mobile set and is called uplink. Similarly, the downlink
for this system (the reception frequency of the mobile set) is defined in the range of
869 MHz−894 MHz that is used by the base station. As it is evident, the difference
between the center frequencies of the downlink and the uplink bands is 45 MHz and
each has a 25 MHz bandwidth. In Figure 1.2, the spectrum usage and the frequency
allocation of this system are shown.
In Figure 1.2, two simultaneous subscribers are shown. In Figure 1.3, it is shown
that there is a free 30 kHz channel between two adjacent channels.
As illustrated in Figure 1.3 even though the bandwidth of each channel is 30 kHz,
in the same cell, 60 kHz channel spacing is considered. This is due to maintaining
an interference-free reception that is discussed in the following chapters. What was
described earlier for DAMPS can be similarly applied for GSM2 assuming a 200 kHz
bandwidth and digital performance. It is recommended that in mobile networks there
be always an empty channel between two adjacent channels.

6SHFWUXP
7UDQVPLW 5HFHLYH
EDQG EDQG

I0+]

Figure 1.2: The spectrum of DAMPS showing two simultaneous subscribers.

2 Groupe Speciale Mobile.

1.1 Introduction to Communication Circuits 7

6SHFWUXP

N+]
N+]
5HFHLYH
EDQG

I0+]

1HLJKERULQJ
8VHU
$GMDFHQW
Figure 1.3: The DAMPS channel spacing stipulates one empty channel between
two adjacent channels in every cell (30 kHz guard band is considered between
two adjacent channels).

While receiving a subscriber channel, it is possible that the adjacent or neighboring

channels might be stronger up to 60 dB. The adjacent, neighboring, and other channels
which lie in the receiving band are called in-band interferes. As the total receive
bandwidth is 25 MHz, with a channel bandwidth of 30 kHz, we have 833 channels.
Assuming a frequency reuse pattern of seven (see Figure 1.4), there will be about 119
channels (833/7 = 119) available for allocation in one cell. With the ever increasing
number of mobile phone usage, it should be clearly obvious that 119 simultaneous calls
do not satisfy the requirements of a dense urban area. So digital TDMA is provided in
DAMPS to increase the capacity by a factor of three with respect to AMPS.
It is usually common to compare the voltage or the power of signals with logarith-
mic ratio as follows
 2 
V1
P1 2Z0  V1
Ratio(dB) = 10 log | | = 10 log  = 20 log | | (1.1)
P2 V22 V2
2Z0

where Z0 is the reference impedance. It is observed that once both signals have the

2 2
7 3 2 7 3
1 7 3 1
6 4 1 6 4
5 6 4 5
5

Figure 1.4: Three clusters of seven cell frequency distribution for DAMPS or
GSM.
8 Chapter 1. The Amazing World of Wireless Systems

same reference impedance, the power ratio and the voltage ratio in dB (decibels) would
have the same value. Another popularly used definition in radio engineering is dBm
which is used for describing the absolute power of the signals and is defined as the
ratio of the power in milli-watts to a 1 mW reference power and defined as

PmW
P( dBm) = 10 log (1.2)
1 mW

We now explain the difference between dB and dBm. When we use the term dB, we are
expressing the logarithmic ratio of two signal amplitudes; once we are using dBm, we
are expressing the logarithmic power ratio of the signal with respect to a 1 milli-watt
reference or describing the power in dBm. Here are a few conversion examples in
Equation 1.3.

5 dBm = 3 mW (1.3a)
0 dBm = 1 mW (1.3b)
− 10 dBm = 0.1 mW (1.3c)
− 100 dBm = 0.1 pW (1.3d)

With the above definitions, the sensitivity in the GSM system implying the minimum
signal which could be properly detected is about −103 dBm, and for DAMPS, the
sensitivity is −114 dBm.

1.2 Signal Levels and Rayleigh Fading

The signal levels from the base station transmitter to the mobile phone receiver may
experience an attenuation of several tens of dBs up to 100 dB. Now consider two users
who receive mobile signals, due to the fact that these signals come from different paths,
the received signal strength may vary from one user to another because of constructive
or destructive interference of rays coming from different paths. As an example, the
wavelength of a 1 GHz carrier signal is just 30 cm. Thus, one by moving 7.5 cm (quarter
wavelength) may go through the signal deep point from its peak point in the space, as
such the signal level might change dramatically. One may ask despite the fact that one
particular channel can go through multipaths and cause variation in the signal level,
how does a receiver detect the desired signal level with all the interferes that come
from other sources. Before answering the aforementioned question, we introduce the
concept of Rayleigh fading. This phenomenon is a statistical model for radio wave
propagation in a multipath medium. As the waves have multiple reflections on hills,
buildings, and trees, calculating the exact signal level is extremely complex. Figure 1.5
exhibits the typical level of the received signal propagating from a base station to the
mobile set receiver. It is clear that when the subscribers’ distance to the base station
antenna increases, the received signal becomes generally weaker. On the other hand,
the signal power level seems to peak and dip as the user increases his/her distance
with the base station. These variations come about from the superposition of different
waves propagating and reflecting through different paths. In radio engineering, it is
convenient to use a statistical model instead of an exact model for estimation of the
1.3 Calculation of the Sensitivity in Different Standards 9

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field strength. This model predicts the amplitude of the signal which experiences
changes or fading by passing through the multipath media. The distribution of this
statistical model is based on Rayleigh distribution. The received signal strength in
general is dependent on the base station’s transmitted power, its antenna gain, and
the fading phenomenon in the propagation medium. In general, the received signal
strength diminishes with distance plus or minus some local variations. In large cities,
the above-mentioned problem becomes more acute because of the reflections from the
ground, and reflections or diffractions from the multiple buildings on the propagation
path. Due to higher traffic in large cities and higher population density, the number of
cells is increased which in turn results in lower cells’ radii. In suburban or rural areas,
where there are not too many base stations, the radius of the cell may increase and the
RF power coming from the base station may be as high as 43 dBm and the minimum
detectable signal may be as low as −103 dBm. The difference between the transmitted
and the received signal being as high as 146 dB implies the complexity of design at
radio frequencies. Handling the large dynamic range required in the rural or suburban
areas and the significant Rayleigh fading phenomenon encountered in urban areas is
one of the main challenges encountered in radio systems.

1.3 Calculation of the Sensitivity in Different Standards

In this section, we intend to calculate the sensitivity of the each of the radio transmission
standards defined for AMPS, GSM, and WiFi 802.11a/g. In general, the sensitivity of
each standard is determined by its bandwidth (bit rate and modulation scheme), noise
figure or noise temperature, and the minimum required signal-to-noise ratio:

Smin = K(Te + T0 )B(S/N)minimum (1.4)

where K is the Boltzmann constant, Te is the equivalent receiver’s noise temperature

(Te = (F − 1) T0 ), B is the bandwidth in Hertz, and Smin is the minimum acceptable
10 Chapter 1. The Amazing World of Wireless Systems

Table 1.1: Specifications of AMPS, GSM, and WiFi 802.11a/g.

Min. Acceptable Max.

Bandwidth Signal-to-Noise Acceptable Sensitivity
Ratio Noise Figure
Wi-Fi
(802.11a/g, BPSK) 20 MHz 14 dB 5 dB −82 dBm
GSM 200 kHz 9 dB 10 dB −102 dBm
AMPS 30 kHz 12 dB 5 dB −112 dBm

signal-to-noise ratio. Now rewriting Equation 1.4 in decibels, one (at the standard
temperature of 290◦ k) obtains

Smin (dBm) = −174 + 10 log(F) + 10 log(BW ) + (S/N) (1.5)

As such, the sensitivity in these three standards will become as what is demonstrated
in Table 1.1.

1.4 Considerations in RF System Design

Let’s start by studying, as an example, the operation of the DAMPS receiver in
Figure 1.6. The antenna is the first element in the front-end of a receiver that absorbs
the electromagnetic energy propagating through the air and converts it to electrical
signals, voltage, and current. Radio receivers usually are designed for extremely weak
signal reception. In many applications, these weak signals may be accompanied by
strong interference from nearby transmitters. In order to attenuate the unwanted signals,
a band-pass filter is placed after the antenna to pass the whole 25 MHz bandwidth of
the DAMPS receiver with a center frequency of 882 MHz. Note that the other signals
like UHF band television or microwave links will be eliminated to some extent. It is a
common practice in a receiver design to make the bandwidth of the filters narrower
as we move forward to the back-end to select the desired signal bandwidth. Right
after the band-pass filter, an amplifier is placed to provide a RF gain for the whole
bandwidth. The received signal might be about 0.5 µV rms, and goes through a gain of
12 dB (or the voltage will be multiplied by four). In many cases, the interferer might
be 60 dB larger than the desired signal (for instance, consider the desired signal with
power of −113 dBm and the interferer level of −53 dBm at other UHF frequencies).
With the mentioned condition, the first filter may introduce a 40 dB loss for the out-
of-band signal which may not be adequate and therefore the second band-pass filter
may attenuate the interferer signal for another 40 dB such that the interferer signal is
attenuated about 80 dB in total. These filters are made of passive components and based
on their materials, these resonators may vary in size from near a couple of millimeters
to one to two centimeters. Next, the amplified band enters a mixer circuit. Here the RF
frequency of 882 MHz is downconverted to an IF of 90 MHz. It is common in most
of the receivers, to have the IF frequency much lower than the input RF. This entails
1.4 Considerations in RF System Design 11

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a few advantages as follows. First of all, achieving high gain is much easier at low
frequencies rather than high frequencies. Secondly, in most receivers the IF frequency
is held constant allowing for more accurate narrowband filter/amplifier design. Up
to the mixer, the signal has experienced 4 dB loss in the passband of the filters and
12 dB gain of the RF amplifier (8 dB total gain) which for an input of 0.5 µVrms
brings the signal to 1.25 µVrms level. In a mixer circuit, the analog multiplication
occurs for which we assume an ideal multiplier. Therefore, the sum and difference
components of 882 + 972 = 1854 MHz and 972 − 882 = 90 MHz are generated. The
former component is eliminated in the first band-pass filter, while the latter reaches the
next stage. At this point, the desired signal is further amplified by 7 dB in the active
mixer and then injected into the filter with 60 kHz bandwidth.
The desired channel passes alongside adjacent channels that are now attenuated.
Finally, the second mixer with an LO frequency of 90.455 MHz brings the 90 MHz
signal to 455 kHz with, say, 12 dB gain. The 455 kHz signal goes through two 30 kHz
filters plus a chain of amplifiers with 40 dB and 60 dB gain. It is instructive to note that
most of the gain is obtained at low frequency and with a small current consumption. In
addition, the design of narrowband band-pass filters is generally much easier at lower
frequencies rather than high frequencies.
A receiver which exploits one downconversion is traditionally called heterodyne
receiver and if more than one downconversion occurs, it is called superheterodyne
receiver. The words heterodyne and superheterodyne, while having historical signifi-
cance, imply one mixing stage, and two or more mixing stages, respectively, and the
prefix hetero- stands for mixing of different frequencies and the word dyne stands
for analog multiplication or mixing. In the full receiver chain of Figure 1.6, the over-
all gain is of the order of 121 dB (the point in the superheterodyne receiver is that
the total amplification is performed in three different frequency ranges, and there-
12 Chapter 1. The Amazing World of Wireless Systems

fore the probability of instability is reduced). If the effective input signal is of the
order of 0.5 µVrms, the overall chain gain of 121 dB brings the low signal level up
to 562 mVrms. The detector shown is a frequency demodulator which detects the
frequency deviation and extracts the voice signal which is applied to the speaker after
audio amplification. The values shown in this example are typical values in the receiver.
Although the lowest gain was placed at the front-end in the low-noise amplifier, it
draws the highest current from the supply voltage (typically near 3 mA). However, the
high gain of 100 dB in the second IF can be achieved with only 750 µA bias current.
This point indicates one of the challenges of high-frequency amplifier design.
It should be noted, however, that the last audio amplifier stage draws a high current
of several tens of milliamperes for the power amplification of the audio signal as
well.
Example 1.1 Is it possible to add more low-noise amplifier stages at the front-
end instead of filtering in order to have a better noise performance?
Answer:
The answer is no. In fact, placing more low-noise amplifiers at the front-end
results in a better noise performance if there were no strong out-of-band interferers.
However, the strong blocker signals without filtering will bring the last low-noise
amplifier stages into saturation which results in decreased effective gain and pos-
sibly the mixing of the desired channel signal with the amplified blocker ones
(this is discussed in more detail in Chapter 4). In addition, the power consumption
cost of high-frequency amplification and the possibility of parasitic feedback may
jeopardize the stability of the front-end (in case of high gain at a single frequency).

The first band-pass filters attenuate out-of-band blocker signals and the first image
signal (2 f0 − fs ), while fs is the RF signal frequency and f0 is the first LO frequency.
As such, the frequency of the first image is 1062 MHz, i.e., 90 MHz above the first LO
frequency. Thus, the importance of those front-end band-pass filters is now obvious.
The third filter after the mixer passes the desired channel, but will attenuate the adjacent
and neighboring channels to some extent. Figure 1.7 shows a possible condition of
the received signals. The two adjacent channels shown in Figure 1.7 will produce
another signal which is due to the mixer nonlinearity and is called the third-order
intermodulation product (IM3 ) which is thoroughly discussed in Chapter 4. The IM3
component will fall on the desired signal; if the IM3 signal is larger than the desired
signal, signal detection will not be possible. Therefore, the third filter mitigates this
issue by attenuating the adjacent and neighboring channels.

Example 1.2 Is it possible to insert a band-pass filter with a bandwidth of 60 kHz

at the front-end of the receiver? Then we will receive the desired channel much
more easily without the blocking signals.
Answer:
The answer is no. The design of such a filter with the carrier frequency of the
order of Gigahertz and such narrow bandwidth needs a very high quality factor of
the order of 15000. Available passive elements, inductors, and capacitors, at the
Gigahertz frequency range do not have such quality factors.
1.4 Considerations in RF System Design 13

Now, we discuss the spectral behavior of the receiver described earlier. As stated
earlier, the importance of the third filter in the receiver is the attenuation of the two
adjacent channels that lie in 60 kHz and 120 kHz away from the desired channel.
This issue is demonstrated in Figure 1.7 in which the weak desired signal lies at the
882 MHz frequency.
Now, consider the frequency response of the third band-pass filter which is shown
in Figure 1.8. Our goal is to calculate the attenuation of the adjacent and the neighbor-
ing channels’ signals if the filter has a second-order behavior.
One may remember that with two poles in the transfer function, the magnitude
of the signal will decrease by 40 dB/decade or 12 dB/octave, or in other words, the
magnitude response will fall by 12 dB once the relative frequency is doubled. Actually,
the attenuation of the filter is calculated based on the relative offset from the center
frequency. For instance, in Figure 1.8, the adjacent channel is just one octave above the
3 dB cut-off frequency; thus, it experiences 12 dB attenuation. Similarly, the neighbor-
ing channel is 120 kHz offset from the desired channel frequency; thus, it experiences

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Figure 1.7: The desired channel, the adjacent channel, and the neighboring
channel in a typical DAMPS radio signal.

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Figure 1.8: Typical received DAMPS signal levels after the third band-pass
filter at 90 MHz .
14 Chapter 1. The Amazing World of Wireless Systems

24 dB attenuation. It can be shown that the attenuation for an nth order filter can be
calculated as

2( f − f0 )
L = 20n log
(1.6)
BW

In Equation 1.6, f0 is the center frequency of the filter, and BW = fU,3 dB − fL,3 dB is
the frequency that the magnitude response of the filter will experience 3 dB attenuation.
In fact, this filter acts as a first channel selection filter. It also attenuates the adjacent
and the neighboring channels; nonetheless, those unwanted channels could be still
stronger than our desired channel. The fourth band-pass filter bandwidth is precisely
equal to one channel bandwidth. Thus, by the second downconversion, both channel
selection and amplification are realized at the second IF. The effect of the fourth filter
is illustrated in Figure 1.9.
Now, consider the attenuation of the fourth filter. The frequency content residing
at 515 kHz and its counterpart residing at 575 kHz will experience 24 dB and 36 dB
attenuation, respectively. Thus, the unwanted adjacent and neighboring channels are
further attenuated. Then, the linear power amplification at low frequency can be
performed by a small current (e.g., 300 µA for 40 dB gain). The fifth filter has the
same behavior as the fourth one. The signal after the fifth filter is demonstrated in
Figure 1.10.
Finally, by the fifth filter, the adjacent channel will be attenuated by 24 dB and
the neighboring channel experiences by another 36 dB attenuation. The spectra of the
wanted and unwanted signals at the FM detector input are depicted in Figure 1.11.
As it is obvious from Figure 1.11, the power of the adjacent channel is below the
desired channel and the neighboring channel has been practically suppressed. Note
that the effect of the additional gains of the second IF amplifiers has been included
in the computation of the final signal levels and the amplifiers are considered to be
linear. In Figure 1.11, we have assumed the total IF gain (90 MHz and 455 kHz)
as G2 = −2 + 12 − 2 + 40 − 2 + 60 = 106 dB which is the sum of gains starting
from the 90 MHz IF all the way to the end of the receiver’s second IF. If we add
G1 = −2 + 12 − 2 + 7 = 15 dB which is the gain of the RF front-end, a total gain of
121 dB for the desired channel is achieved.

N+] N+]
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N+]

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Figure 1.9: Typical received DAMPS signal levels after the fourth band-pass
filter at 455 kHz.
1.4 Considerations in RF System Design 15

N+] N+]
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N+]

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Figure 1.10: Typical received DAMPS signal levels after the fifth band-pass
filter at 455 kHz.

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Figure 1.11: Typical received DAMPS signal levels at the input of the frequency
demodulator.

One of the most important parameters in RF reactive components is the quality

factor (Q). The concept of the quality factor for a reactive element or a resonant circuit,
is the ratio of the stored energy to the dissipated energy. This dimensionless parameter
describes how much lossy a component is. The general definition of the quality factor
is as follows
Average energy stored Average energy stored
Q , 2π × = 2π f0 × (1.7)
Energy dissipated per cycle Power loss
where f0 is the operating frequency. For a reactive element or a resonant circuit, it can
be shown that the quality factor could be calculated as
Center frequency
Q= (1.8)
Bandwidth
16 Chapter 1. The Amazing World of Wireless Systems

By bandwidth, we mean 3 dB bandwidth of a circuit. Now with this definition of

quality factor, we calculate them for the band-pass filters in our receiver chain as
follows
882 MHz
Q1 = = 35.28 → for the RF filter (1.9a)
25 MHz
90 MHz
Q2 = = 1500 → for the first IF filter (1.9b)
60 KHz
455 KHz
Q3 = = 15.1 → for the second IF filter (1.9c)
30 KHz
The first one is a ceramic front-end filter, the second one is a crystal filter, and the third
one is a ceramic IF filter. The high quality factor is a measure of the sharpness or the
selectivity of a band-pass filter. Depending on the material used in a filter, its quality
factor may change. The quality factor of crystal filters is better than other devices.
When we reach the second IF, we put most of the gain of the receiver at the second IF.
If we consider that the manufacturing cost of a filter is proportional to its Q, we would
have all the interest for the cost and power consumption reduction to put the gain at
lower frequencies. As such, we have succeeded to realize most of the filtering for the
channel selection at the second IF frequency at a lower cost.
In this superheterodyne receiver that has two downconverting mixers and two IF
frequencies, we observe the use of three types of filters. The filters become narrower as
we proceed in the receiver chain. The first set of filters at the RF input frequency pass
the full DAMPS 25 MHz band. The second filter’s bandwidth (at the first IF frequency)
is wide as to pass two or three DAMPS channels, in this example 60 kHz. The third set
of filters (at the second IF frequency) are wide enough just for a single channel, here,
30 kHz.
On the other hand, the gain distribution is such that the RF front-end has 10 to
20 dB gain and about the same amount in the first IF, and most of the gain realize at
the second IF frequency, here, of the order of 100 dB.
In our receiver example, the first filter selects the whole 25 MHz bandwidth and
rejects the image signal to some extent. Actually, the image frequency which is at
2 fLO − fRF is a signal which would be equally transferred to the IF frequency by the
mixer (if it is present at the RF input) and therefore, it will appear as an interference at
the first IF output. To avoid this inconvenience, it is mandatory that the image signal
to be rejected at the RF input. This function should be materialized by the first set of
filters. As such, while the input RF filter passes the whole DAMPS service band, it
rejects the unwanted image frequency which is at 1062 MHz in this example.
There are two problems in high-frequency filters, the first one is their loss and
the second one is their tunability. How can we switch from one channel to another
in the front end of the receiver? The simplest way is to change the frequency of the
first LO. After the first LO, the frequency of the first IF does not change. Therefore,
the front-end filter must be able to accommodate all the frequencies of the desired
spectrum (e.g.„ the whole GSM spectrum), if it is not subject to tuning.
Many years ago, the tuning of the oscillator frequency was manual. Nowadays
using standard frequency synthesizers, this process is performed precisely and auto-
matically upon a digital command word. In the next section, we briefly discuss the
basic concept of the frequency synthesizers.
1.5 A Basic Understanding of Frequency Synthesizers 17

1.5 A Basic Understanding of Frequency Synthesizers

To understand the behavior of frequency synthesizers, we must first introduce the
concept of voltage-controlled oscillators (VCO). The input of a VCO is a voltage that
makes the output frequency change monotonically or possibly linearly with respect
to it. The frequency range of a VCO in our receiver example is 959.5 MHz ≤ fOSC ≤
984.5 MHz which covers the whole 25 MHz input band. The channel spacing in
the DAMPS standard is 30 kHz. The integer N frequency synthesizer is shown in
Figure 1.12.
The frequency of the output signal is divided by a counter M which generates a
pulse after receiving M pulses at its input. This process can also be done by cascading
a few digital dividers. The divided signal is then injected to the phase detector to
be compared with the reference signal coming from the crystal oscillator divider.
The phase detector measures the phase difference between the two incoming signals.
The resonant frequency of the crystal is usually between 5 MHz and 50 MHz. The
frequency of the crystal oscillator in Figure 1.12 is 14.4 MHz. For 30 kHz channel
spacing, the input signal to the phase detector must be 30 kHz (that is N should be
480). It can be shown that the VCO frequency in this structure can be derived as

M
fVCO = fcrystal (1.10)
N

The circuit in Figure 1.12 is a negative feedback loop. If the input of the phase detector
is a signal with 30 kHz fundamental, the other input must have the same frequency
component at the steady state. By allowing enough loop gain, the error signal will
tend to zero. This system is called a phase-locked loop frequency synthesizer. We will
go over the concept of the PLL in Chapter 3. It is noteworthy that in a PLL at locked
state, not only will the two input frequencies be the same, but also the phases of the
two signals will track each other with a constant phase offset. Using a programmable
counter, one may change the oscillation frequency to receive the desired channels. For
instance, with a VCO frequency of 972 MHz, we calculate the division ratio as

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Figure 1.12: Typical integer N frequency synthesizer for the DAMPS receiver.
18 Chapter 1. The Amazing World of Wireless Systems

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14.4 × 106
N= = 480 (1.11)
30 × 103
972 × 106
M= = 32400 (1.12)
30 × 103
To tune to a desired frequency, usually the divider N is constant and the desired channel
is obtained by changing the value of M.
Let’s now proceed to investigate a more complete DAMPS radio as shown in
Figure 1.13.
As depicted in the red portion of Figure 1.13, the signal is received via an antenna.
It is amplified by a low-noise amplifier and the whole band goes through the band-pass
filter. It also attenuates the first image signal. Next, the signal is downconverted by a
mixer to the first IF. Channel selection filter attenuates side-band channels, and by a
second mixer, the signal is translated to a second IF. The LO frequency for a second
mixer comes from a multiplier circuit which makes multiple 6 of crystal frequency.
In the second IF, the signal again is filtered and via two paths goes for digital and
analog demodulation. In the upper path, the signal is demodulated digitally through
an AGC and an I/Q demodulator, and the other path demodulates signal by an FM
1.5 A Basic Understanding of Frequency Synthesizers 19

quadrature detector. Frequency synthesizer of the receiver has a frequency range of

953.5 MHz−978.5 MHz, and by dividing by 128 or 129 followed by more division,
a 30 kHz signal is obtained and the loop will be locked. As it is evident in frequency
synthesizer of the receiver, the output signal of the oscillator is buffered and then by
passing through a band-pass filter drives the first mixer.
A similar procedure is realized at the phase-locked loop of the transmitter. Its PLL
generates proper LO frequency for driving the upconverter mixer. The high-frequency
signal then passes through the band-pass filter and reaches the power amplifier. Finally,
the amplified signal is coupled to the antenna for radiation into the air. The signal
modulation is frequency modulation (FM); however, one may use quadrature digital
phase modulation.
Nowadays, the radio receivers employ frequency translation to zero-IF which is called
zero-IF receiver where there is no image signal.

Example 1.3 A radio receiver has the block diagram shown in Figure 1.14 and
its specifications are denoted on the figure.

625kHz
G=-2dB G=-2dB I
BW=25MHz BW=25MHz BW=6.25MHz
fc=912.5MHz fc=912.5MHz fc=182.5MHz

900-925MHz 625kHz
1.25MHz step G=12dB Q
Wideband 720-740MHz
1MHz step
π/2

÷15 VCO ÷2 ÷2 180-185MHz

0.25MHz step
15MHz
÷M

Figure 1.14: A typical heterodyne digital radio receiver.

(a) The input filters’ specifications are the same. If the desired signal has a
power level of −100 dBm and an image signal accompanies it with a power of
−45 dBm (both at the input of the first RF filter), calculate the out of band atten-
uation of the RF filters, for the image frequency, such that the image signal goes
10 dB below the desired signal at the first mixer input.
(b) Calculate M for channel spacing of 1.25 MHz in the desired band. Note that the
second LO frequency is not fixed.
(c) If at the receiving channel of 912.5 MHz there exists an adjacent channel signal
at 915 MHz, determine the order of the low-pass filters such that the adjacent
channel is rejected by 40 dB. Assume that f3 dB for the low-pass filter is 625 kHz.

Solution:
(a) The image frequency can be obtained as follows

fIm = 2 fLO − fRF (1.13)

20 Chapter 1. The Amazing World of Wireless Systems

As the RF frequency can be varied between 900 and 925 MHz, then the lower edge
of the receive band is downconverted by 720 MHz. The image frequency would be

fIm 1 = 2 × 720 − 900 = 540 MHz (1.14)

Now, consider the upper edge of the receive band. In this case, 925 MHz signal is
downconverted by 740 MHz LO. Thus, the image frequency can be written as

fIm 2 = 2 × 740 − 920 = 560 MHz (1.15)

As we desire that the image frequency to be 10 dB lower than the desired signal,
it must be attenuated by 65 dB (55 + 10 = 65 dB). As a result for the identical RF
filters, each one must have an out-of-band attenuation of 32.5 dB at least. The
normalized frequency difference of the image signal will be

fRF − fIm 912.5 − 560

BW
= = 28.2 (1.16)
2
12.5

The normalized frequency difference in octaves becomes

log 28.2
D= = 4.81 octaves (1.17)
log 2

The bandpass filter order becomes

32.5
n= = 1.12 (1.18)
6×D
Therefore, we choose n = 2 for the RF filters. This will satisfy the required
attenuation for the other image frequency (540 MHz ) as well.
(b) The channel spacing at the RF frequency in this receiver is 1.25 MHz ; however,
in this architecture 1 MHz spacing is realized by the first mixer (because the crystal
frequency is divided by 15) and 250 kHz is realized by the second mixer (because
the VCO frequency is divided by 4). Thus, the frequency synthesizer will have
a 1 MHz frequency step. As a result, the minimum value of M is 720 and its
maximum value is 740.
(c) As the adjacent channel is 915 − 912.5 = 2.5 MHz above the desired channel,
the attenuation for the nth order low-pass filter can be written as

2.5 MHz
20n log = 40 (1.19)
625 KHz

Then, n = 3.32. So we choose n = 4 as an integer and the filter will be a 4th order
one.
1.6 Conclusion 21

1.6 Conclusion
The world of wireless communications has conquered many aspects of the modern
human life. The technical aspects of this field are of great importance for an electri-
cal/electronic engineer. In this chapter, we made a general presentation for the RF
communication systems. We surveyed the general architecture of an RF transmitter
and an RF receiver. Specifically, we briefly studied the architecture of a superhetero-
dyne receiver which consists of two frequency conversion (mixer) stages as well as a
zero-IF receiver which consists of a receiver with the same LO and RF frequencies.
Furthermore, we observed how in a superheterodyne receiver the large interfering
signals in the adjacent and the neighboring channels are suppressed (or attenuated)
with respect to the desired signal along the receiver chain. In addition, we saw how
using a phase-locked loop and frequency dividers we can synthesize the desired local
frequencies in a receiver. A DAMPS transceiver block diagram was studied as an
example. We deliberately ignored some more complex issues such as the nonlinearity
of the mixers, VCOs, or amplifier circuits here. But as the reader goes forward through
the text, he/she would gain more understanding about the nonlinearity issues. Then the
reader is urged to return back to this chapter to gain more understanding of the related
problems.

1.7 References and Further Reading

1. T.S. Rappaport, Wireless Communications: Principles and Practice, second
edition, New York, NY: Prentice-Hall, 2002.
2. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
3. L.W. Couch, Digital and Analog Communication systems, eighth edition, New
Jersey: Prentice-Hall, 2013.

1.8 Problems
Problem 1.1 Figure 1.15 shows a triple downconversion receiver in which the input
signal range at the antenna is from 0.02 GHz to 5 GHz. If the first VCO with its initial
control voltage is oscillating at 7.5 GHz,
1. Find the values of M and N in such a way that desired frequencies are provided
for the corresponding mixers.
2. What is the frequency of the image signal at the first mixer’s input? How this
component is eliminated in this structure? What is the frequency of the second
image at the second mixer’s input, and what is the corresponding values at the
input of the antenna. Moreover, find the third image frequency at the third
mixer’s input and its corresponding frequencies alongside the structure.
3. Suppose that the input frequency is 3.5 GHz, then find the first VCO frequency.
In this situation, if the input low-pass filter is a second-order one with 3 dB
frequency of 5 GHz, and if the three subsequent band-pass filters’ frequency
response are as those depicted in Figure 1.16, and if a strong blocker signal
emerges at 100 MHz above the input signal, how much it will be attenuated
through the receiver chain?
22 Chapter 1. The Amazing World of Wireless Systems

G=-2dB G=-2dB G=-2dB

0.02-5GHz G=-2dB BW=100MHz BW=5MHz BW=2MHz
G=10dB 5GHz 3dB fc=2.5GHz 3dB fc=100MHz 3dB fc=20MHz G=80dB

LPF BPF1 BPF2 BPF3

VCO VCO ×4

20.0MHz
÷N ÷M

Figure 1.15: Triple downconversion wideband receiver.

|HLPF| |HBPF1| |HBPF2| |HBPF3|

-2dB -2dB -2dB -2dB

-40dB/dec -40dB/dec -40dB/dec -40dB/dec

0 5GHz
f 2.5GHz
f 100MHz
f 20.0
f
MHz
100MHz 5MHz
2MHz

Figure 1.16: Frequency response of filters.

Problem 1.2 In the transceiver depicted in Figure 1.17, first IF frequency resides at
90.1 MHz and the second IF is at 455 kHz. If fVCO1 = 966.3 MHz, find the receiving
channel frequency. In this situation, find the frequency of the second VCO such that
the transmitted carrier signal is 45 MHz lower than the received signal.

BW=25MHz BW=60kHz BW=30kHz BW=30kHz

fc=881MHz fc=90.1MHz fc=455kHz fc=455kHz G=80dB
BW=25MHz
fc=836MHz

Amp.

90.555MHz
BW=25MHz
fc=836MHz

Input data
Mod.

VCO1
VCO2
966.3MHz

Figure 1.17: A typical GSM900 transceiver.

1.8 Problems 23

Problem 1.3 In the FM transceiver depicted in Figure 1.18, determine the unknown
VCO frequencies alongside with division ratio M2 . If fVCO2 and M2 have two different
possible values each, discuss the advantages and disadvantages of either of the values
if the transceiver has a tuning bandwidth of 15 MHz.

IF 0+] IF 0+]
)0LQSXW
PRGXODWLQJ
VLJQDO

IF 0+]
9&2
1
·1

·0 IF 0+]
%DVHEDQG

·1 9&2
1
0+]

4XDGUDWXUH
)0GHWHFWRU
·0
0

Figure 1.18: A VHF FM transceiver block diagram.

Problem 1.4 In the wideband receiver depicted in Figure 1.19, the first VCO is tuned
at 3.5 GHz,
(a) Find the received signal frequency.
(b) What is the first image frequency of the first mixer? Is it in the receive band? In
this situation, the image frequency in the second mixer can be emanated from two RF
components. Determine those components’ frequencies at the antenna RF input.
(c) If the input low-pass filter is a first-order one with a 3 dB corner frequency of 1 GHz
and the other two bandpass filters have a frequency response given in Figure 1.19,
determine the attenuation values of the first image and those two RF components which
could result in the second image in this circuit.

BW=10MHz BW=2MHz
1GHz fc=3GHz fc=21.4MHz

LPF BPF1 BPF2

|HLPF| VCO |HBPF1| |HBPF2|
3-4GHz 3.0214GHz

-6dB/oct -6dB/oct -6dB/oct

0
log(f) 3GHz
log(f) 21.4
log(f)
MHz
1GHz 10MHz
2MHz

Figure 1.19: A dual conversion wideband receiver.

24 Chapter 1. The Amazing World of Wireless Systems

Problem 1.5 In the WiMax receiver depicted in Figure 1.20, the input frequency
range is between 3.4 GHz and 3.6 GHz with 20 MHz channel spacing. The input
band-pass filter is of second order with the bandwidth of 400 MHz and the center
frequency of 3.5 GHz. The first IF signal is at fin /5 where fin is the input signal
frequency. The second IF frequency is zero. The output low-pass filters are of third
order with a corner frequency of 10 MHz. Moreover, the frequency response of the
amplifier A and the mixers are constant.
(a) What is the image frequency at the receiver input which experiences the maximum
attenuation, in dB?
(b) Find the division ratio M for the receiver for the input frequency range.
(c) If the input frequency is 3.5 GHz, what is the attenuation of the unwanted adjacent
and the unwanted neighboring channels? (channel spacing is about 20 MHz )

10MHz
I
A
fc=3.3-3.7GHz

A IF1
10MHz
Q
A

π/2

÷16 VCO ÷4

16MHz
÷M

Figure 1.20: An I/Q double conversion WiMax receiver.

Problem 1.6 In a radio receiver depicted in Figure 1.21, we have cascaded the blocks
with the given specifications.
(a) If at the input two signals (the main channel and the adjacent channel, respectively)
with a power of −60 dBm each at frequencies of 900.060 MHz and 900.120 MHz are
present, what is the power of IM3 components at the output of the mixer?
(b) If the 45 MHz band-pass filter has a passband of 60 kHz and is of second order,
then what is the output of the 45 MHz filter emanating from the IM3 component at
900 MHz. (See IM3 concept in Chapter 4.)

Block LNA Filter Mixer Filter VGA

Gain(dB) 15 −3 10 −3 43
IIP3 (dBm) −8.5 ∞ 5.5 ∞ 10
1.8 Problems 25

G=15dB G=10dB G=43dB

IIP3=-8.5dBm IIP3=5.5dBm IIP3=10dBm

LNA G=-3dB G=-3dB VGA

fC=900MHz fC=45MHz
BW=25MHz BW=60kHz
VCO
fVCO=fin+45MHZ

Figure 1.21: A simplified GSM900 receiver.

ZL
Ga

ȕ:1

2. Oscillators

2.1 An Introduction to Oscillators

Oscillators are of most important blocks in RF circuit design because they generate
the fundamental RF signals required in the transceiver systems. As we have seen a
complete radio in Chapter 1, oscillators are integral parts of each system. These circuits
which generally behave in a large-signal regime mandate specific considerations for
proper analysis and design. Furthermore, they are one of the most power hungry blocks
whose figure of merit depends on the signal purity and stability. The basic behavior
of every oscillator is due to interaction of the noise with the circuit nonlinearity that
should be examined in detail; however, in this chapter, we introduce simple methods
which are based on linear systems to better understand the oscillator behavior. This
block is one of the first blocks in the receiver which provides the driving signal for
a downconverting mixer. In this chapter, we introduce two different methods for
analysis of an oscillator, namely, positive feedback in a loop and negative resistance in
a resonant circuit.

2.2 First Approach: Positive Feedback

Consider Figure 2.1 where a tuned amplifier output is fed back to its input through a
divider circuit.
The important point in oscillator’s behavior is that there is no external excitation
except for the bias. The input of these circuits is noise which is fed at the input of the
loop amplifier. Different blocks as depicted in Figure 2.1 are the amplifier, the resonant
circuit or the frequency selection tank, and the divider. As one might recall from the
feedback control systems, one may write the transfer function for a positive feedback
loop as

Ga (s)
H (s) = (2.1)
1 − β Ga (s)
28 Chapter 2. Oscillators

)UHTXHQF\
1RQOLQHDU VHOHFWLRQ
DPSOLILHU

=/
*D

ȕ

'LYLGHU

Figure 2.1: Block diagram of a typical oscillator.

The loop will be unstable (the oscillation will occur) once β Ga (s) = 1 which is called
the Barkhausen condition. Consider the noise at the input of the amplifier which is
amplified and passed through the tank circuit and is fed back through the divider to
the input of the amplifier
√ (in this example, we have the resonant frequency of the tank
which is f0 = 1/(2π LC)), and by means of a nonlinear amplifier, the returning signal
would be in phase at the input. Typical white noise samples in the frequency domain
and in the time domain are shown in Figure 2.2.
Thermal noise has a white spectrum; in other words, it has a fixed power spectral
density at least in the RF range. The power spectral density (in W/Hz) can be expressed
as N0 = kT and the RMS voltage across a resistance R can be expressed as

Vn 2 = 4 kTBR (2.2)

The available power of this noisy resistance could be described as N = kT B in watts

where in Equation 2.2, Vn is the RMS noise voltage, k is the Boltzmann constant equal
to 1.38 × 10−23 J/K, T is temperature in Kelvin, and B is the noise bandwidth in hertz.
Noise is a random process and it is not possible to determine its instantaneous value

V W/Hz

0 t
f
0
(a) (b)
Figure 2.2: Typical white noise samples, (a) in time and (b) in frequency
domain.
2.2 First Approach: Positive Feedback 29

at a specific time. Thus, the noise level is usually specified by its power spectral
density or its RMS value. Now considering the noise shown in Figure 2.2 passes
through a frequency selective circuit, the noise spectrum will be changed according to
the resonant circuit response. This will result in rejection of the noise in frequencies
out of the passband of the resonant circuit. White noise is transformed to colored
noise with a selective skirt shaped spectral density. Its time-domain waveform would
resemble approximately a sinusoid, if the resonant circuit has a high quality factor.
Then, the shaped noise passes through the divider and the amplifier, and the amplifier
amplifies it and once again it is applied to the amplifier input after the division. If
the loop gain of the system is larger than unity, the fed back noise would build up
until the nonlinearity of the amplifier compresses the gain and the loop gain of the
system approaches unity. It should be noted that the larger the fed back signal becomes
through this process, the more it will approach a pure sinusoid. Thus, when looking
at the output, there is approximately an amplified noisy sinusoid whose spectrum
approaches a pseudo-impulse-shaped spectrum in the frequency domain. The larger
the quality factor of the frequency selective circuit, the better the spectral purity of the
output signal. That is, the output signal would approach the sinusoidal form. That is
because of better rejection of the noise sidebands by a sharper filter. This process is
shown in Figure 2.3.
As depicted in Figure 2.3, for high quality factor tank circuit, the output signal is
more similar to a sinusoid; however, degrading the quality factor will result in more
phase/amplitude noise and higher harmonics level.

Vout Vout

f t

Vout Vout

f t

Figure 2.3: The output signal of the resonance circuit for different quality factor
values.
30 Chapter 2. Oscillators

Now let’s consider the amplifier nonlinearity. We would now investigate the
definition of the gain in a large-signal/limiting regime. Table 2.1 shows the output
voltage versus the input voltage of a saturating amplifier.
The large-signal gain of the amplifier is defined as the ratio of the output fundamen-
tal to the input fundamental voltage of the circuit. As Table 2.1 suggests, increasing
the signal level will result in decrease in the large-signal gain. This limiting behavior
of this circuit will stabilize the oscillation amplitude eventually. Furthermore, charac-
teristic of a typical nonlinear amplifier is illustrated in Figure 2.4 and Figure 2.5 which
demonstrates the limiting behavior of the amplifier for large signals.
We have assumed an implicit approximation in our above descriptions. By entering
the large-signal regime due to the nonlinear behavior of the circuit, a number of
harmonic frequencies of the fundamental signal will be generated as well. We can
define a more precise definition for an effective large-signal gain of the amplifier as
the ratio of the first harmonic amplitude at the output to the fundamental input voltage
amplitude, while neglecting the other harmonics at the output.
How does a positive feedback loop for an oscillator stabilize? With respect to the
definition of the effective large-signal gain of an amplifier, the Barkhausen’s criterion
suggests that the loop should have a unity gain with zero phase at the oscillation
frequency (Ga β = 1∠0), as such the loop will be stabilized. It should be noted that
the feedback in any oscillator is positive which results in initial noise amplification
and consequent oscillation. There are a number of important parameters in oscillator

Table 2.1: Effective gain with input and output signal of a saturating amplifier.

Input Voltage(V) Effective Gain Output Voltage(V)

0.25 14 3.5
0.5 10 5
1 5.2 5.2

Vo
5.2
3.5

0 Vi
0.25
0.5

Figure 2.4: Input/output phasor voltage characteristic of a typical limiting

amplifier.
2.2 First Approach: Positive Feedback 31

Figure 2.5: Typical variations of the large-signal gain of a nonlinear amplifier

as a function of input voltage.

design, such as topology, resonant circuit, small-signal loop gain, large-signal loop
gain, signal amplitude, and phase noise. Phase noise in the oscillators is one of the
most interesting and challenging issues. We briefly discuss about the phase noise
here. Phase noise is the result of the interaction of baseband white noise signal with
the sinusoidal oscillation signal in the nonlinear circuit of the oscillator, in the sense
that the amplitude and the phase of the sinusoidal oscillation signal are modulated by
the random noise signal. As such, we can describe the general output of a sinusoidal
oscillator as V (t) = (A + an (t)) cos (ω0t + φ0 + φn (t)), where dφ n an
dt ω0 and A 1.
Here A is the amplitude of the oscillations, an (t) represents the random amplitude
modulation, ω0 is the radian frequency of oscillation, φ0 is the phase of the oscillation,
and φn (t) represents the random phase modulation. In Figure 2.6, the oscillations’
start-up of a typical oscillator as a function of time is depicted.

Amplitude

100mV

-100mV Time(µs)
0 1 2 3 4 5 6 7 8

Figure 2.6: Typical oscillations’ start-up of an oscillator as a function of time

(oscillation frequency is about 2 MHz).
32 Chapter 2. Oscillators

If one computes the auto correlation function of this signal, and takes the Fourier
transform of it, he/she will obtain the spectral density of the oscillator signal. This
signal would be in the form of a narrow skirt around the sinusoidal carrier. The
importance of the phase noise is in the coherent receivers. In the sense that one intends
to detect, for example, different phase modulating levels on the carrier signal, the
random phase noise of the carrier induces a random phase shift at the output of the
detector. This exacerbates the signal detection process. We refer the interested reader
to more advanced texts regarding sinusoidal oscillators and the phase noise for further
investigation [5].

2.3 Second Approach: Negative Resistance/Conductance

The concept of negative resistance is useful for oscillators using two-terminal devices
and/or two-terminal resonators. It is obvious that the positive resistor (passive resistor)
dissipates energy. In contrast to it, one can imagine a negative resistor which generates
electrical energy. Now, consider the circuit depicted in Figure 2.7.
In Figure 2.7, positive resistors dissipate energy; however, the source and the
negative resistors generate electrical energy. In other words, the negative resistor acts
as an active load in generating energy. As an example, consider the output voltage in
this circuit

RL
VO = VS = −10VS (2.3)
RL + RS + R1

As it is obvious, the output voltage is larger than the input voltage and excess power is
generated indeed. A similar concept is shown in Figure 2.8.
As it is obvious, there is no external excitation in the circuit in Figure 2.8 except
the noise current. The existing thermal noise in the resistor (random movement of
electrons) may be amplified in the circuit by means of positive feedback.

IL GL
= (2.4)
In GL + GS + jCω − Lωj

(QHUJ\ 5
GLVVLSDWRU
ȍ 92

(QHUJ\ 56
JHQHUDWRU
(QHUJ\

GLVVLSDWRU ȍ 5/
(QHUJ\ ȍ
JHQHUDWRU
96

Figure 2.7: Negative and positive resistors in a simple circuit.

2.3 Second Approach: Negative Resistance/Conductance 33

IL

GL L C GS
-25mƱ 20mƱ In

In2 =4kTBGS

Figure 2.8: Energy generation in resonant circuit with no external excitation.

At the resonant frequency, the imaginary part vanishes, and consequently, the above
equation reduces to
IL −25
= =5 (2.5)
In −25 + 20
As such, the noise current will be obviously amplified. If one calculates the overall
tank, conductance will reach to the total Geq = −5 mf, and thus there will be a net
energy generator in the circuit. This negative conductance will amplify the noise and
the frequency response of the tank shapes its spectrum in a way as described in the
previous section. Once the large-signal oscillation is established, one can neglect the
noise current source and writing the KCL at the common node of the circuit, one would
obtain
YL (V )V +Y ( jω)V = 0 (2.6)
As V has a nonzero value, therefore,

YT (V, ω) = YL (V ) +Y ( jω) = 0 (2.7)

This is the oscillation condition of a two-terminal device oscillator. The process of
amplification of noise by the negative resistance and its frequency selection by the tank
circuit continues till the nonlinear behavior of negative conductance decreases the abso-
lute value of the negative conductance down to 20 mf. In other words, increasing the
amplitude of oscillations results in decreasing of the negative conductance’s absolute
value till the dissipated energy in the load resistance and the generated energy of the
negative conductance are equal. This is the point of stable oscillations. The negative
conductance is normally dependent on the oscillation voltage amplitude. When its
conductance decreases to −20 mf, the amplitude of oscillation can be calculated
precisely from the nonlinear characteristics of the negative conductance. The oscillator
based on negative resistance/conductance can be demonstrated in Figure 2.9 where
a selective two-terminal resonator is connected to a negative resistance device. This
configuration can be a potential sinusoidal oscillator depending on the value of the
negative resistance and the resonator loss resistance.
Writing the KVL in the circuit, one obtains

1
−R(A) + jLω − j + RL I = 0 (2.8)
Cω
34 Chapter 2. Oscillators

-R(A) L C RS

Figure 2.9: Negative resistance model of an oscillator.

where A is the amplitude of the current phasor. I having a nonzero value, we would
have

1
−R(A) + RL + j Lω − =0 (2.9)
Cω
As such, the oscillation condition simplifies to
ZT ( jω, A) = 0 (2.10)
where ZT ( jω, A) stands for the total loop impedance.

Example 2.1 Is it possible to replace the negative conductance in Figure 2.8

equal to −20 mf at first? Will the circuit stabilize immediately, then?

Solution:
No, because the oscillator will never start. We have stated that for starting the
oscillations the net negative conductance must be less than zero and the circuit by
its nonlinear behavior will decrease the net negative conductance to zero, and the
oscillation will be stabilized.

It can be asserted that most types of oscillators can be analyzed by either of the two
methods presented in the previous sections.

2.4 Oscillator Topologies

In this section, we describe the basic oscillator circuit topologies. Here the active
device could be either a bipolar transistor or a MOSFET, with proper bias with the
same topologies. We start with a general oscillator topology as depicted in Figure 2.10
with a fictive ideal amplifier (with infinite input impedance and zero output impedance)
which has a real gain Av .

Z2

+
Vi AV
- +
Z1 Z3 Vo
-

Figure 2.10: General oscillator topology with three reactive elements.

2.4 Oscillator Topologies 35

In this topology, the positive feedback is realized by the voltage division through
Z1 and Z2 . Normally, the three external elements in the oscillator circuit are purely
reactive elements. Now, consider Z1 ≈ jX1 , Z2 ≈ jX2 , and Z3 ≈ jX3 . The three reactive
elements should resonate at the oscillation frequency. For the oscillation condition,
one can write
X1
Av = 1 Unity loop gain condition (2.11)
X1 + X2
X1 + X2 + X3 = 0 Resonance condition (2.12)

Since X1 + X2 = −X3 , then for satisfying the Barkhausen oscillation condition, we

should have
X1
−Av =1 (2.13)
X3
Now, we consider three distinct cases depending on the value of Av .
Case 1 (common source/common-emitter amplifiers): Av < 0 then given Equa-
tion 2.13, it is imposed that XX13 > 0. In this case, if X1 is chosen to be inductive, then
X3 should be inductive as well, and considering the resonance condition X2 should
be necessarily capacitive, (Figure 2.11(a)). On the other hand, if X1 is chosen to
be capacitive, then X3 should be capacitive as well, and considering the resonance
condition X2 should be necessarily inductive (Figure 2.11(b)).
Case 2 (common gate/common-base amplifiers): Av > 1 then given Equa-
tion 2.13, it is imposed that XX13 < 0. In this case, if X1 is chosen to be inductive,
then X3 should be capacitive, and since Av > 1, then it is imposed that X1X+X 1
2
< 1,
therefore, X2 should be necessarily inductive (Figure 2.12(a)). On the other hand, if
X1 is chosen to be capacitive, then X3 should be inductive, and since Av > 1, then it is
imposed that X1X+X
1
2
< 1, therefore, X2 should be necessarily capacitive (Figure 2.12(b)).
Case 3 (common drain/common-collector amplifiers): 0 < Av < 1 then given
Equation 2.13, it is imposed that XX13 < 0. In this case, if X1 is chosen to be inductive,
then X3 should be capacitive, and since Av < 1, then it is imposed that X1X+X1
2
> 1,
therefore, X2 should be necessarily capacitive as well (Figure 2.13(a)). On the other

C2 L2
Vo Vo

Vi Vi
L3 C3
L1 C1

(a) (b)

Figure 2.11: Two possible oscillator topologies with negative voltage gain
(Av < 0).
36 Chapter 2. Oscillators

L2 C2

Vi Vo Vi Vo

L1 C3 C1 L3

(a) (b)

Figure 2.12: Two possible oscillator topologies with positive voltage gain
greater than unity (Av > 1).

/ &
9L & 9L /
& / 9R
9R

D E

Figure 2.13: Two possible oscillator topologies with positive voltage gain less
than unity (0 < Av < 1).

hand, if X1 is chosen to be capacitive then X3 should be inductive, and since Av < 1,

then it is imposed that X1X+X
1
2
> 1, therefore, X2 should be necessarily inductive as
well (Figure 2.13(b)). In the above-mentioned, circuits and the corresponding figures,
we used MOSFET transistors as the active element to show the implementation of
different oscillator topologies. In those figures, all the MOSFET transistors can be
literally replaced by bipolar transistors without any alteration. To demonstrate these
implementations, in the following sections, we use the bipolar transistor as the active
element, including the bias circuitry.

2.4.1 Common-Emitter Oscillator Circuit

The oscillator with grounded emitter is shown in Figure 2.14.

As depicted in Figure 2.14, if one considers the noise voltage across the base–
emitter of the transistor, the signal is amplified through the base to the collector by a
small-signal gain of Ass = −gm RL . At the oscillation frequency where another 180◦
phase shift is materialized by the passive LC circuit (note that CB is AC short-circuit),
the criterion of oscillation which is the positive feedback is realized. The other criterion
which is the unity closed-loop gain will be materialized after the amplitude growth of
the oscillator, through the nonlinearity of the transistor, the gain is compressed to its
large-signal value Als = −Gm RL .
2.4 Oscillator Topologies 37

VCC
RFC
R1 L
L
Q
CB
Q C2 C1
C2
R2 C1
RE CE

Figure 2.14: The common-emitter oscillator circuit with 180◦ phase shift
through the LC circuit.

VCC
RFC
R1 L
Q C2
CB L
Q C2
RE C1
C1
CB R2
RE

Figure 2.15: The common-base oscillator circuit.

2.4.2 Common-Base Oscillator Circuit

The oscillator with grounded base is shown in Figure 2.15.
Here both CB capacitors have large capacitances which are approximately short-
circuit at the operating frequency and the RFC is a large inductor which is considered as
open-circuit at the operating frequency. As depicted in Figure 2.15, if one considers the
noise voltage at the base–emitter junction of the transistor, this signal will be amplified
by a small-signal gain of Ass = gm RL at the collector in phase with the input. Then,
the signal is fed back to the base by the capacitive divider and as such provides the
necessary positive feedback at the oscillation frequency. Again due to the nonlinearity
of the transistor, the stabilization of the oscillation amplitude will occur by the gain
compression through the feedback loop.

2.4.3 Common-Collector Oscillator Circuit

The oscillator with grounded collector is shown in Figure 2.16.
Here CB is a large capacitor whose RF impedance is considered to be as a short-
circuit. As depicted in Figure 2.16, the noise voltage at the transistor’s base appears at
38 Chapter 2. Oscillators

VCC

R1 L
Q
CB C1
Q L
C1 C2
C2 RE
R2
RE

Figure 2.16: The common-collector oscillator circuit.

the emitter by the common-collector voltage gain. This gain is slightly less than but
near to unity and the output is in phase with the input. The output voltage is fed back
to the base by the capacitive step-up transformer. At the frequency where the positive
feedback is realized and once the loop gain is compressed to unity, the oscillations will
materialize. Note that here the transistor amplifier has a voltage gain of less than unity
but a current gain larger than unity and consequently a power gain greater than unity.
Note that in all the above oscillators, there is a resonant and dividing circuit which
consists of an inductor and two capacitors which is called the Colpitts oscillator. The
dual of these circuits could be used as an oscillator as well, that is, with a resonant
circuit of a single capacitor and two inductors which is called the Hartley oscillator.

2.4.4 Colpitts versus Hartley Oscillators, a New Insight

The oscillators shown in Figs. 2.14, 2.15, and 2.16 are called Colpitts family of
oscillators. If one omits the bias circuitry from those oscillators and draws an AC
model for them (considering RE is sufficiently large in the common-base and the
common-collector configurations), he/she would arrive at a common core circuit which
is depicted in Figure 2.17(a). If one replaces all the RF capacitors by inductors, and all
the RF inductors by capacitors, he/she has made a dual circuit of Colpitts oscillators
which is called Hartley family of oscillators (Figure 2.17(b)). It is instructive to observe
that all these oscillators have the same concept (considering RE is sufficiently large in
the common-base and the common-collector configurations). It is noteworthy that all
the oscillator topologies described in section 2.4 can be reduced to either of these two
core oscillators.
If one computes the closed-loop gain in either of Colpitts or Hartley oscillators, ne-
glecting the transistor parasitic reactances, he/she would reach the following resonance
criteria for the oscillations:

C1 +C2
Lω − = 0 for Colpitts oscillators (2.14a)
C1C2 ω
1
Cω − = 0 for Hartley oscillators (2.14b)
(L1 + L2 ) ω
VCC VCC VCC
L
RFC RFC
R1 L R1 L R1 L

CB CB CB Q
C2 C2
Q Q Q
C2 C1 C2 C1 C1
R2 C1 R2 CB R2
RE CE
RE RE Colpitts
2.4 Oscillator Topologies

Core

(a)

VCC VCC VCC

L2 RFC
R1 R1 R1 C
C C C

Q
Q Q Q L2
CB CB L2 CB L2 L1

R2 L1 R2 L1 CE R2 L1 CE
CB Hartley
RE CE Core
RE RE

(b)

Figure 2.17: The Colpitts and the Hartley oscillators (in common-emitter, common-collector, and common-base configura-
tions) and their corresponding main core circuits.
39
40 Chapter 2. Oscillators

Either of these two equations show a parallel resonance condition (why?) in the
reactive elements surrounding the transistors. Furthermore, there is a positive feedback
from the output to the input (180◦ phase of the voltage gain and 180◦ phase of the
voltage division for CE case, and zero-degree phase of the voltage gain and zero-degree
phase of the voltage division for the CB and CC cases).

Example 2.2 Determine the oscillation condition in the following common-

emitter transistor oscillator considering the parasitic elements of the transistor.

M;

9 &I 9R

M; UL &L *P9 &R UR M;

Figure 2.18: A Colpitts oscillator core including the parasitic elements of

the transistor.

Solution:
For determining the oscillation condition, we just absorb the parasitic elements of
the transistor into the surrounding reactances as follows
−1
1 1
Z1 = + + jCi ω (2.15)
jX1 ri
−1
1
Z2 = + jωCf (2.16)
jX2
1 −1

1
Z3 = + jωCo + (2.17)
ro jX3

As such, we can consider the following equivalent circuit for this oscillator.

Z2
+ +

Vo GmV1 Z3 Z1 V1

- -

Figure 2.19: The equivalent circuit of the Colpitts oscillator.

2.5 Crystal Oscillators 41

The output voltage can be easily computed as

−GmV1
Vo = 1
(2.18)
Y3 + Z2 +Z 1

Then, the input feedback voltage can be written as

−GmV1 Z1
V1 = 1
× (2.19)
Y3 + Z2 +Z1 Z1 + Z2

As such, the complex oscillation condition becomes

−Gm Z1
=1 (2.20)
1 +Y3 (Z2 + Z1 )

Or
−Gm Z1 Z3
=1 (2.21)
Z1 + Z2 + Z3

2.5 Crystal Oscillators

Quartz crystal is a piece of a wafer of crystalline silicon dioxide mineral which is cut at
certain angles to give electro-acoustic resonances at the required frequency range. Two
metallic surfaces cover the two faces of the quartz wafer. These two surfaces constitute
the electric terminals of the crystal. The quartz crystal has a piezoelectric property.
In piezoelectric materials, mechanical pressure is transduced to the electric voltage
and electric voltage is transduced to mechanical pressure. As such, the mechanical
vibrations in the crystal are transformed to electric vibrations by the virtue of its
piezoelectric property. A typical crystal’s electric model is shown in Figure 2.20. It
is noteworthy that the natural resonances of a piece of quartz crystal are of a very
high quality factor and a very good temperature stability, the points which are the
advantages of the use of quartz crystals in the oscillators.

CS

CP rS

LS
f
fS fP

Figure 2.20: Electrical model of a crystal and its impedance behavior.

42 Chapter 2. Oscillators

As it is obvious from the crystal model in Figure 2.20, there exists a series and
a parallel resonance for the crystal. That is the crystal impedance, at first, falls to a
very small value at its series resonance frequency ( fS ) and then changes to a very high
impedance at its parallel resonance frequency ( fP ). Then, its impedance due to the
parallel capacitor falls gradually to a low impedance value at frequencies much higher
than fP . The values of the equivalent circuit element of the crystal are such that the
difference between the series and the parallel resonance frequencies is quite small
while the difference between the impedances at these two frequencies is quite large.
The input impedance of the crystal can be easily computed as

1 − ω 2 LsCs + jωrsCs
Z( jω) = (2.22)
jωCp 1 +Cs /Cp − ω 2 LsCs + jωrsCs
1
Given the fact that rs ωsCp , the crystal impedance value at ωs with a very good
approximation would be

Z( jωs ) ≈ rs (2.23)

This is a quite small value for the crystal impedance. On the other hand by the fact that
Q = Lsrωs s has a very large value and CCps 1, then the crystal impedance value at ωp
with a very good approximation would be
QCs
Z( jωp ) ≈ (2.24)
ωpCp 2

This impedance value is normally quite large. Interestingly, the crystal impedance
above fs and under fp is inductive (with a large inductive reactance derivative, ∂∂ ωX ) and
its impedance for frequencies under fs is capacitive (with a large capacitive reactance
derivative, − ∂∂ ωX ). This is the phenomenon which stabilizes the oscillation frequency in
the crystal oscillators. Figure 2.21 shows the computational results of a typical 10 MHz
crystal impedance with Cs = 9.1 fF, rs = 35 Ω, Ls = 27 mH, and Cp = 2 pF. The series
resonant frequency of the crystal would be 10.153542 MHz and the parallel resonant
frequency would be 10.176615 MHz. The quality factor of the crystal would be 49200.
As such, the crystal impedance goes from 35 Ω to 1.75 MΩ within a frequency span
of 23 kHz only. At low frequencies, the capacitors are open circuit, and therefore
the impedance will be high. The first resonance frequency in the circuit is due to the

120 90

120 100
110 80 75 0

100 50
|Z|(dBΩ)

Z(Deg.)

90 40
10 10.2 10.4
25 -90
10.1 10.2 10.3
80 0
70 -25
60 -50
50 -75
40 -100
2 4 6 8 10 12 14 16 18 20 2 4 6 8 10 12 14 16 18 20
Frequency (MHz) Frequency (MHz)

Figure 2.21: Simulation of crystal impedance.

2.5 Crystal Oscillators 43

resonance of the series inductor Ls and the series capacitor Cs which is called the series
resonance fs . At this frequency, the inductor and the capacitor will tune out and make
approximately a short circuit (very low impedance) at the right-hand branch. Thus,
the overall impedance of the crystal will be equal to rs k jωCp . By increasing the
frequency, Cs goes low impedance and the right-hand branch becomes inductive, the
next resonance will occur approximately due to the resonance of Ls and Cp which we
call the parallel resonance and show it by fp . Finally, if we continue increasing the
frequency, the parallel capacitor will short out the whole crystal impedance at high
frequencies. The series resonance frequency can be calculated from Equation 2.25:
1
fs = √ (2.25)
2π LsCs
The parallel resonance frequency can be calculated from Equation 2.26:
q
fp = fs 1 +Cs /Cp (2.26)

The crystal’s quality factor can be computed as

Q = Ls ωs /rs = 1/ωsCs rs (2.27)

Crystal is generally used in oscillators where the acoustic vibration occurs in the body
of the crystal, and by the virtue of the piezoelectricity of the crystal, those oscillations
are transformed into electrical oscillations. A crystal has a very high quality factor
which will result in the purity of the oscillator signal spectrum. This quality factor for
crystal in Figure 2.20 is equal to 49200. As stated in Equation 2.24, the maximum
impedance of the crystal occurs at the parallel resonant frequency and it has a very
high value described by this equation.
A number of crystal oscillator topologies are shown in Figure 2.22.
In Figure 2.22(a) which is a common-collector Colpitts-like oscillator, the crystal
acts as an inductor. That is the inductive reactance of the crystal resonates with the
capacitances of C1 and C2 . The feedback voltage across RE appears through the step-up
capacitive transformer across the crystal terminals. The oscillation frequency would be
slightly above fs .
In Figure 2.22(b) which is a common-base Colpitts-like oscillator, CB is a large
(short-circuit) capacitor. The crystal is in series within the feedback loop. The resonant

9&& 9&& 9&&

&
/ 5/ 5)& 5/
3DUDOOHO 5 &
5 5
UHVRQDQFH
4
4 4 3DUDOOHO
& & UHVRQDQFH
5
& 5( &% 5 5( 6HULHV &% 5 5( &
UHVRQDQFH

D E F

Figure 2.22: Three different Colpitts-like crystal oscillator configurations with

a bipolar transistor.
44 Chapter 2. Oscillators

CS1 CS2 CS3

CP rS1 rS2 rS3

LS1 LS2 LS3

Figure 2.23: A complete model of a crystal.

frequency of the LC circuit should be approximately the same as the series resonance
frequency of the crystal. the oscillation frequency would be approximately fs .
In Figure 2.22(c) which is a common-base Colpitts-like oscillator, CB is a large
(short-circuit) capacitor. The crystal is put in parallel with the capacitive divider and it
resonates with these capacitors at the oscillation frequency. The inductive reactance of
the crystal is tuned out by the capacitors. The oscillation frequency would be slightly
above fs .
Normally, a piece of quartz crystal has several electro-acoustic resonant modes.
These modes are called overtones which occur approximately at the odd multiples of
the fundamental resonant frequency. A more generalized circuit model of a crystal is
shown in Figure 2.22. In this model, the higher order resonances (overtones) of the
crystal are shown by the additional parallel RLC branches in the circuit. Normally, the
higher order modes resonances have a lower Q than the fundamental mode resonance.
As depicted in Figure 2.23, a crystal may have a number of higher order resonant
frequencies. Thus, by choosing the main oscillation frequency in the crystal circuit
meticulously, one may use it for higher desired overtone. For instance, in Figure 2.22(c)
where there is no inductor, the circuit is forced to oscillate at the fundamental fre-
quency of the crystal. That is to say the crystal will become purely inductive near
the fundamental resonant frequency. It is possible to design a frequency selection
circuit whose frequency is a multiple of the fundamental frequency of the crystal.
For example, if one designs an LC tank with 75 MHz resonance frequency, with the
fundamental frequency of 15 MHz of the crystal, the oscillator finally will oscillate at
75 MHz. However, the price of higher oscillation frequency is injecting more energy
and as a result more power loss and therefore lower quality factor. In reality, one may
order the manufacturer to make a crystal with a specific parallel resonance frequency
by realizing specific parallel capacitor. As a rule of thumb, a parallel capacitor is
usually near a few pFs or a few tenths of pFs (this value can be adjusted by the crystal
manufacturer to have a precise oscillation frequency using the crystal). Moreover, the
resonance frequency variations of a crystal with temperature for a range of 0 − 70◦
Celsius is just about 50 ppm. In other words, if the oscillation frequency is 1 MHz,
by those temperature variations, the oscillator may have about 50 Hz frequency drift.

Example 2.3 Is it possible to choose the fundamental frequency of a crystal

resonance frequency at a very high value? Therefore, surpassing the need for
overtone driving.
2.5 Crystal Oscillators 45

Answer:
No, because there is a technical manufacturing problem in the design of very high
frequency crystals. As a matter of fact, the crystal disc will become too thin to
fabricate, the package capacitance would increase, microphonic issues would arise,
and unwanted frequency modulation might happen. (Microphonic effect is an
acoustic frequency modulation effect once the crystal is physically shaken).

Now, assume that we have a transmitter with a carrier frequency of 900 MHz. With
50 ppm frequency variations in the reference crystal, there will be 45 kHz frequency
variation at the carrier, which in GSM with 200 kHz channel bandwidth is too much.
Thus, we need a more precise frequency for this kind of application. A temperature-
compensated crystal oscillator (TCXO) might be a solution, where by microtuning
and using temperature-dependent biasing, the temperature variations of the oscillation
frequency is compensated. Therefore, the frequency will be stabilized within a range
of few ppm’s, e.g., a frequency variation of 3 ppm here will result in a variation of
2.7 kHz in the carrier frequency. If this range of variation is not yet acceptable, a
PLL-based synthesizer carrier might be employed. We discuss more about this subject
in the next chapter.

2.5.1 Datasheet of a Family of Crystals

For better understanding of a crystal performance, the datasheet of a family of crystals,
namely, Unit HC-49/U, is presented in Table 2.2.
The variations of series resistance (impedance of the crystals at the resonance
frequency) of the family HC-49/U crystals are depicted in Figure 2.24. As it is seen
in this figure, the series resistance of the crystal might change between 28 dBΩ and
70 dBΩ (25 Ω to 3000 Ω) depending on the chosen resonance frequency of the crystal.
Notably, the crystals with a resonance frequency in the range of few tens of MHz have
a relatively low series resistance (in the range of few tens of ohms) while the crystals

Table 2.2: The specifications of HC-49/U family of crystals.

Nominal Frequency Range 1.8 to 32 MHz-24 to 75 MHz-75 to 200 MHz

Vibration Mode Fundamental-3rd Overtone-5th Overtone
Frequency Tolerance@25◦ C ±20 or ±30 ppm
Temperature Stability ±30 or ±50 ppm
Operating Temperature Range −10◦ C to +60◦ C (Option: −20◦ C to +70◦ C)
Storage Temperature Range −20◦ C to +70◦ C (Option: −30◦ C to +80◦ C)
Load Capacitance 8 pF to 32 pF or series
Equivalent Series Resistance See Figure 2.24
Shunt Capacitance 5 pF max(≤18 MHz) or 7 pF max(>18 MHz)
Drive Level 200 µW max(≤5 MHz) 100 µW max (>5 MHz)
Insulation Resistance 500 MΩ min @ 100 V DC
Aging ±5 ppm per year
46 Chapter 2. Oscillators

70
65

ESR(dBΩ)
60
55
50
45
40
35
30
25
1 10 100
Frequency (MHz)

Figure 2.24: Equivalent series resistance of HC-49/U.

with a resonance frequency in the range of few MHz have a relatively higher series
resistance (about few hundreds of ohms to few thousands ohms), and the crystals with
a resonance frequency of few hundred MHz have a series resistance of the order of a
hundred ohms.

2.6 Calculation of the Oscillation Frequency Including

the Device Parasitics
As an example, consider Figure 2.25 where a Colpitts-like oscillator is shown.
The oscillator with its parasitic capacitances is shown in Figure 2.25. The gain
can be computed by calculating the impedance seen at the collector times the transcon-
ductance. As it is obvious in Figure 2.25, the parasitic capacitances can be absorbed in
the oscillator’s circuit capacitors. Thus, the resonance frequency of the oscillator can
be calculated as
1
f0 = r (2.28)
2π L C(C11+C
+Cbe )C2
+C2 +Ccs +Cbc
be

VCC

L
R1
Cbc

Q C2
Ccs
CB R2 Cbe RE C1

Figure 2.25: Colpitts oscillator with parasitic capacitances.

2.7 Quality Factor of Reactive Elements 47

By absorbtion of the parasitic capacitances in the surrounding circuit capacitors, one

can always simplify the oscillator circuit into the common core oscillators as described
earlier. This will eventually result in a precise calculation of the oscillation frequency.

2.7 Quality Factor of Reactive Elements

The quality factor has an important role in the RF components applications. Very
roughly one can consider it as a ratio of stored energy per cycle to the power loss in
the component, or one can consider it as a ratio of a reactance to the resistance loss, or
as a ratio of a susceptance to the conductance loss. All of them have the same meaning.
A transfer function of a second-order band-pass filter can be written as
Vo 1
= (2.29)
Vi 1 + jQ ωω0 − ωω0

Or for the amplitude response, one can write

Vo
= r 1
Vi 2 (2.30)
1 + Q2 ωω0 − ωω0

where ω0 is the resonant frequency of the LC tank, and Q is the quality factor of the
circuit. Q is a parameter which describes the ratio of the energy stored per cycle to the
power dissipation, i.e., higher Q means lower power dissipation compared to the stored
energy. The magnitude of the fraction in Equation 2.29 becomes equal to unity at the
resonance frequency ω0 . Moreover, in the magnitude response of the filter, the same
parameter Q shows the sharpness of the frequency response near the center frequency.
Now consider the frequency response of the band-pass filter as shown in Figure 2.26.
By computing the upper and the lower frequency 3 dB points in the frequency
response of the filter, it can be shown that the quality factor for Figure 2.26 can be
written as
ω0 f0
Q= = (2.31)
BW ∆f
Here, the bandwidth is described in radian frequency where BW = 2π∆ f . Here, Q is
the quality factor of the bandpass filter.

|H(jω)|
ω0-ω0/2Q ω0+ω0/2Q

ω0 ω

BW

Figure 2.26: Magnitude response of a band-pass filter.

48 Chapter 2. Oscillators

The quality factor can also be defined for lossy elements such as inductors and
capacitors. For a lossless inductor, Q will be infinite; however, in reality, due to
different sources of loss in the inductors (series resistance, skin effect, and magnetic
core loss), they will have a finite Q. An inductor and its equivalent circuit are shown in
Figure 2.27. The quality factor of an inductor is defined as in 2.32:
1 2
2 LI Lω Rp
Q = 2π 1 2
= = (2.32)
2 rs I T
rs Lω

Note that for a specified inductor, the values of rs and Rp are quite different. As a
rule of thumb, the quality factor of a discrete inductor is between 50 and 100 and for
an on-chip inductor due to its two-dimensional structure is about 3 to 5. The other
reactive lossy element in circuits is a capacitor. For an ideal capacitor, the quality
factor is infinite. Nonetheless, for a real capacitor due to dielectric losses or its series
resistance, the quality factor is finite. The quality factor for a capacitor can be given by
Equation 2.33:
1 2
2 CV 1
Q = 2π 2 = RpCω = (2.33)
1V rsCω
2 Rp T

Note that for a specified capacitor, the values of rs and Rp are also quite different. The
equivalent circuit of a capacitor is shown in Figure 2.28.
As a rule of thumb, for a discrete capacitor, the quality factor is between 50 and
200 and for integrated capacitors, this value is roughly between 50 and 100. The
parameter Q first defined as the ratio of stored energy per cycle to the dissipated power

/
/ 5S /
UV

,QGXFWRU ,QGXFWRU ,GHDO

ZLWKSDUDOOHO ZLWKVHULHV LQGXFWRU
UHVLVWDQFH UHVLVWDQFH 4 ’

Figure 2.27: Equivalent circuit of an inductor.

&
& 5S &
UV

&DSDFLWRU &DSDFLWRU ,GHDO

ZLWKSDUDOOHO ZLWKVHULHV FDSDFLWRU
UHVLVWDQFH UHVLVWDQFH 4 ’

Figure 2.28: Equivalent circuit of a capacitor.

2.8 Nonlinear Behavior in Amplifiers 49

is simply related to the resistive loss in the inductors and the capacitors. As such, a
resonator realized by a pair of elements like an inductor and a capacitor will have
a quality factor which will be less than the quality factor of either of the elements.
Therefore, realizing an LC filter with quality factors in excess of one hundred will not
be possible.
Normally, the skin effect increases the quality factor of the inductors with increas-
ing frequency, but the Q factor is reduced as the frequency passes a certain maximum
value. As a matter of fact, the series resistance of inductors increases by the square root
of frequency due to the skin effect. In practice, in discrete implementations, multiple
inductors are placed in parallel to mitigate the skin effect, and therefore, achieve
a better quality factor. The difficulty of placing a band-pass filter at the receiver’s
front-end is more clear now. Because of the low quality factor of the passive reactive
elements, high Q band-pass circuits are barely realizable in the receiver sections. This
is the reason for which to have very sharp filters with high quality factors, i.e., normally
ceramic filters or crystal filters are used in the receiver chain.

2.8 Nonlinear Behavior in Amplifiers

Consider the transistor amplifier circuit in Figure 2.29.
Also, assume that the collector bias current is 1 mA, The gain of the amplifier can
be obtained as in Equation 2.34:
rin
Av = − × gm RL ≈ −gm RL (2.34)
RS + rin

where gm is the transistor’s transconductance and rin is the base dynamic resistance as
described in Equation 2.35.

KT KT Vt
rin = β = (β + 1) = (β + 1) (2.35)
qIC qIE IE

Now, if the collector load resistance is 1 kΩ, for the collector bias current of 1 mA, the
gain of the amplifier becomes AV = −gm RL = −38.5. The derived equation is merely

VCC=5V

RBB= RL= IC= 1mA

220kΩ 1kΩ
C1 Vo
Q C2
RS
50Ω
+ RE=
Vs CE
2kΩ

Figure 2.29: Common-emitter amplifier circuit.

50 Chapter 2. Oscillators

valid for the linear behavior of an amplifier; however, when a large signal is imposed
at the input, the gain equation should be modified. The transfer characteristics of the
bipolar transistor can be assumed as in Equation 2.36:
qvBE
ie = IES e kT (2.36)

For instance, with this exponential I −V characteristic, with an increase of one thermal
voltage ( kT
q ≈ 26 mV) at the input, the output current will be multiplied by a Neper.
With a supply voltage of 5 V in Figure 2.29, the corresponding output voltage of the
amplifier for different input levels is depicted in Figure 2.30. Here, β is assumed to be
equal to 100.
As it is obvious from Figure 2.29, the output DC of the collector is 4 V. First,
consider the input amplitude is 12.5 mV. Thus, output signal swing will be about 1 V.
If we continue increasing the input voltage to 25 mV, the signal will be limited from
the top to supply voltage and from the bottom to 2.4 V. Further entering large-signal
input regime will result in limiting the signal from the top to 5 V and from the bottom
to about 2.2 V while having a significant distortion with respect to the sinusoidal form.
Consider Figure 2.31.

5
VS=12.5mV
4 VS=25mV
VC(v)

VS=50mV
3
2
1
0 2 4 6 8 10
Time (µs)

Figure 2.30: The collector voltage, for different values of input voltage, as a
function of time.

VCC =5V

RB RL=1kΩ

C1 Vc Vo
Q C2
RS
50Ω
+
Vs IBias CBypass

Figure 2.31: Common-emitter amplifier with a current source.

2.8 Nonlinear Behavior in Amplifiers 51

Similarly, the collector current is assumed to be 1 mA here and we gradually

increase the input voltage as before. The difference between Figures 2.29 and 2.31
is the current source at the emitter of Figure 2.31. The currents’ source fixes the DC
current at the output. Increasing the input voltage results in exponential increase of
the output current. However, the current source maintains the DC current at a fixed
level. As a matter of fact, the DC voltage of the emitter is increased in such a way to
maintain the DC current of the emitter at the specified bias current, Ibias . Therefore, the
growing current of the amplifier is controlled. Simulation results of this phenomenon
are shown in Figure 2.32.
If we replace the load resistance in Figure 2.31 with a parallel RLC circuit with a
high quality factor, indeed we arrive at a tuned amplifier structure as in Figure 2.33.
The ideal gain of this circuit in Figure 2.33 can be obtained as

Vout
= −Gm RL (2.37)
Vs

5
4
3
VC(v)

2
1
0
0 2 4 6 8 10
Time (µs)

Figure 2.32: Output collector voltage with 100 mV input at 1 MHz frequency.

9&&

/ 5/ &

5%
9RXW
4

9V

4 4
&%\SDVV

9((

Figure 2.33: Tuned amplifier with implemented emitter current source.

52 Chapter 2. Oscillators

9&Y

7LPH—V

Figure 2.34: Output voltage waveform of the tuned amplifier for a 50 mV

sinusoidal input (RL = 1 kΩ, C = 3.2 nF, and L = 7.93 µH).

At the large-signal regime, it is possible to choose a desired harmonic of the input

signal by tuning the output tank circuit, as depicted in Figure 2.34.

2.9 A Note on the Modified Bessel Functions of the First Kind

Modified Bessel functions of the first kind are frequently encountered in the nonlinear
analysis of the P-N junction diodes and the bipolar transistors due to their exponential
characteristics. Here, we briefly introduce these functions and their characteristics.
The harmonic expansion of an exponential sinusoidal function can be described as
follows

excos(ω0 (t)) = I0 (x)+2I1 (x)cos (ω0 (t))+2I2 (x)cos (2ω0 (t))+· · ·+2In (x)cos (nω0 (t))
(2.38)
Here the functions In (x) are called the modified Bessel functions of the first kind. These
functions are the solutions of the Bessel’s differential equation at certain conditions.
The evolution of these functions with respect to their argument has generally an
exponentially increasing form. Furthermore, the higher order function is generally
smaller than the lower order function for the same argument. That is
In+1 (x)
<1 for all x (2.39)
In (x)
Additionally

In+1 (x)
lim =1 (2.40)
x→∞ In (x)
and

I1 (x)
lim =1 (2.41)
x→∞ I0 (x)
2.10 Large-Signal Transconductance and Harmonic Tuned Amplifiers 53

,Q[ ,Q[

,[
,[
,[
,[
,[ ,[ ,[

,[ ,[
,[
,[
,[



[ [

Figure 2.35: Typical variations of the modified Bessel functions with respect to
their arguments.

Table 2.3: Numerical values of the first four modified Bessel functions of the
first kind as a function of their argument.

x 0 1 2 3 4 5 6 7 8 9
I0 (x) 1 1.27 2.28 4.88 11.30 27.24 67.23 168.59 427.56 1093.59
I1 (x) 0 0.57 1.59 3.95 9.76 24.34 61.34 156.04 399.87 1030.91
I2 (x) 0 0.14 0.69 2.25 6.42 17.51 46.79 124.01 327.60 864.50
I3 (x) 0 0.02 0.21 0.96 3.34 10.33 30.15 85.18 236.08 646.69

and

I1 (x) x
lim = (2.42)
x→0 I0 (x) 2
Furthermore, I0 (0) = 1 and In (0) = 0 for n > 1. Figure 2.35 shows the variations
of the modified Bessel functions of different orders with respect to their argument.
Table 2.3 shows the numerical values of the modified Bessel functions of different
orders as a function of their arguments.

2.10 Large-Signal Transconductance and Harmonic

Tuned Amplifiers
In this section, we derive relations for the amplitude of the output signal using modified
Bessel functions and the concept of large-signal transconductance. The small-signal
transconductance in Figure 2.33 can be obtained as
∂ iC IC
gm = = (2.43)
∂ vbe Vt
where the direct current can be calculated as in Equation 2.44:
VEE −VBEbias
IEbias = (2.44)
RBB
54 Chapter 2. Oscillators

The above equation is valid for the small-signal behavior of an amplifier. One may
write a general equation for large-signal bipolar transistor current as 2.45:

VBE +Vi cos(ω0 t)

bias
iC = αIES e Vt (2.45)

Equation 2.45 can be rewritten as 2.46

VBE V
bias i cos(ω t)
0
iC = αIES e Vt e V t (2.46)

If we define x = Vi /Vt and expanding in terms of modified Bessel functions of the first
kind, that will result in Equation 2.47:
VBE
bias
iC = αIES e Vt (I0 (x) + 2I1 (x) cos (ω0t) + 2I2 (x) cos (2ω0t) + · · · ) (2.47)

If one factors out the DC component of 2.47, he/she reaches to 2.48.

VBE
bias 2I1 (x) 2I2 (x)
iC = αIES e Vt I0 (x) 1 + cos (ω0t) + cos (2ω0t) + · · · (2.48)
I0 (x) I0 (x)

As it is obvious from 2.48, the DC component can be obtained as

VBE
bias
IDC = αIES e Vt I0 (x) (2.49)

While employing the current source, the DC component of current will be constant
(how?). When x increases, I0 (x) will increase similarly but VBEbias will decrease indeed.
The only mechanism that maintains the DC constant is VBE depreciation as stated. The
output signal for a large-signal input can be written as

2I1 (x)
Vout = VCC − αIEbias ZL (0) + ZL ( jω0 ) cos (ω0t) +
I0 (x)

2I2 (x)
ZL (2 jω0 ) cos (2ω0t) + · · · (2.50)
I0 (x)

where the input signal is VS = Vi cos(ωt) and α ≈ 1. The typical frequency response
of the amplifier is shown in Figure 2.36. Here, it is assumed that the output is tuned to
the first harmonic of the input.
As it is obvious from Figure 2.36, the output current contains all harmonics of
the input signal. However, by tuning the band-pass filter, any output harmonic can
be selected at the output. In tuned amplifier and oscillator applications, it is normally
assumed that the output circuit is tuned to the fundamental harmonic of the input.
While band-pass filters are of interest in narrowband applications, we investigate their
impedance behavior a little bit more. A simple parallel RLC band-pass filter fed by a
current source is shown in Figure 2.37.
2.10 Large-Signal Transconductance and Harmonic Tuned Amplifiers 55

_9RMȦ_ )UHTXHQF\UHVSRQVHRI
EDQGSDVVILOWHU

2XWSXWKDUPRQLF

Ȧ
Ȧ Ȧ Ȧ Ȧ

Figure 2.36: Harmonics of output and selecting behavior of the band-pass filter.

IS C R1 L

Zin
Figure 2.37: Resonant circuit.

One may obtain impedance of the band-pass filter as 2.51:

RT
Zin = (2.51)
1 + jQ( ωω0 − ωω0 )

where
1
ω0 = √ RT = R1 k RPC k RPL (2.52)
LC

where RPC and RPL are the equivalent parallel loss resistances of the capacitor and the
inductor, respectively. Q is the overall quality factor of the circuit and is expressed as
2.53:
R1 k RPC k RPL
Q= = RTCω0 (2.53)
Lω0

The total quality factor of the band-pass filter will be

1 1 1 Lω0
= + + (2.54)
Q QL QC R1
56 Chapter 2. Oscillators

The important point in Equation 2.54 is the dominance of low Q element which is
usually an inductor. Typical frequency response of the band-pass filter is shown in
Figure 2.38.
It can be shown that the input impedance at −3 dB point of the circuit is as 2.55:

RT
Zin = (2.55)
1 + j(1)

By comparing Equations 2.51 and 2.55, we reach to 2.56:

ω0 + ∆ω ω0 ω0
Q − = 1 or ∆ω ≈ (2.56)
ω0 ω0 + ∆ω 2Q

One may derive equation for bandwidth of the circuit as

BW = (ω0 + ∆ω) − (ω0 − ∆ω) = 2∆ω(radian/s) (2.57)

Finally, the relation for the bandwidth is as 2.58:

ω0
BW = (radian/s) (2.58)
Q

Equation 2.58 is of great importance. It suggests that we can calculate the quality
factor of resonant circuits by finding the ratio of center frequency to its 3 dB bandwidth.
Moreover, one may obtain the bandwidth of the circuit by the division of the resonant
frequency by the quality factor.
For the nth harmonic of the input, the load impedance described in Equation 2.57
can be expressed as

RT nRT
ZL ( jnω0 ) = 1
' 2 − 1)
(2.59)
1 + jQ n − n jQ (n

|Z(jω)|

BW

RT
-3dB

ω0-∆ω -3dB ω0 ω0+∆ω -3dB

ω

Figure 2.38: Typical frequency response of a parallel resonant circuit.

2.10 Large-Signal Transconductance and Harmonic Tuned Amplifiers 57

With respect to the aforementioned derivation of Q, one may obtain output voltage
of the circuit depicted in Figure 2.33 as

2RT I1 (x) 4RT I2 (x) π
Vout = VCC − αIEbias cos (ω0t) + cos 2ω0t −
I0 (x) 3QI0 (x) 2

3RT I3 (x) π
+ cos 3ω0t − +··· (2.60)
4QI0 (x) 2
Neglecting the smaller valued harmonic terms, we can simplify the above equation to
the following
2RT I1 (x)
Vout ≈ VCC − αIEbias cos (ω0t) (2.61)
I0 (x)
Or
2RT I1 (x)
Vout ≈ VCC − xαIEbias cos (ω0t) (2.62)
xI0 (x)
Or
2I1 (x)
Vout ≈ VCC − gm Vi RT cos (ω0t) (2.63)
xI0 (x)
Here we can define the large signal transconductance as the following
IC1 2I1 (x)
Gm = = gm (2.64)
Vi xI0 (x)
In the above-mentioned equation, it is assumed that the load impedance is tuned to the
first harmonic of the input. As such, it is observed that the higher order harmonics
amplitudes are decreasing monotonically as a function of amplitude and frequency.
If the load quality factor Q is sufficiently large, the higher order harmonics could be
neglected compared to the fundamental harmonic.
Furthermore, regarding Equation 2.57, once the load is tuned to the mth harmonic
of the input, the output voltage will become

mRT 2I1 (x) π 2mRT 2I2 (x) π
Vout =VCC −αIEbias × cos ω0 t+ + × cos 2ω 0 t+ +· · ·
Q (m2 − 1) I0 (x) 2 Q (m2 − 4) I0 (x) 2

2RT Im (x) nmRT 2In (x) π
+ cos (mω0 t) + · · · + × cos nω0 t − +··· (2.65)
I0 (x) Q (n2 − m2 ) I0 (x) 2

Note that, in Equation 2.65, in the developed series n 6= m and here it is assumed that
m > 2. Neglecting the smaller-valued terms, we can approximate the above equation
by the following
2RT Im (x)
Vout ≈ VCC − αIEbias cos (mω0t) (2.66)
I0 (x)
To clarify more what is described in Equation 2.65, two special cases are considered in
the following sections.
58 Chapter 2. Oscillators

2.10.1 Case I: Resonant circuit is tuned to the first harmonic of the input
frequency (tuned amplifier case)
For this special case, as it was already derived in Equation 2.60 for the first three
harmonics, in other words for n = 1, 2, 3. We define nth harmonic at the output as
Hn (x), we will have

2I1 (x)
H1 (x) = RT IEbias (2.67a)
I0 (x)

2I2 (x) RT 2I2 (x) 2RT
H2 (x) = IEbias ≈ IE (2.67b)

I0 (x) 1 + jQ(2 − 2 )

1 I0 (x) 3Q bias

2I3 (x) RT 2I3 (x) 3RT
H3 (x) = IE ≈ IE (2.67c)

I0 (x) 1 + jQ(3 − 13 ) bias I0 (x) 8Q bias

2.10.2 Case II: Resonant circuit is tuned to the second harmonic of the input
frequency (frequency multiplier case)
Here, m = 2. For this case, we derive the equations for first to third output harmonics,
in other words for n = 1, 2, 3. The equation for the first three harmonics can be written
as

2I1 (x) RT 2I1 (x) 2RT
H1 (x) = IEbias ≈ IE (2.68a)

1
I0 (x) 1 + jQ( 2 − 2)

I0 (x) 3Q bias
2I2 (x)
H2 (x) = RT IEbias (2.68b)
I0 (x)

2I3 (x) RT 2I3 (x) 6RT
H3 (x) = IE ≈ IE (2.68c)

3 2
I0 (x) 1 + jQ( 2 − 3 ) bias

I0 (x) 5Q bias

Typical output harmonic currents and the load impedance variations are shown in
Figure 2.39 for both cases (I and II).
As it is obvious from Figure 2.39, in the first case, the output band-pass filter is
tuned to the first harmonic of the input which means it attenuates higher harmonics. In
the second case, the output band-pass filter passes the second harmonic and attenuates
other frequency components, i.e., the first harmonic, the third harmonic and the higher
ones at the output. For the ease of calculation, we define a large-signal transconduc-
tance (Gm ) based on the harmonic number of the output. Our goal is to obtain an
equation for the output signal in terms of Gm . For instance, one may write the output
voltage for the first harmonic as

Vo1 = −Gm1 RTVi (2.69)

We may write the amplitude of input signal as Vi = xVt ; so, we derive Gm1 as
I1 I1
Gm1 = = (2.70)
Vi xVt
2.10 Large-Signal Transconductance and Harmonic Tuned Amplifiers 59

|VO(jω)|
Case Case
1 2

ω
ω1 2ω1 3ω1 4ω1

Figure 2.39: Typical output harmonics as well as load impedance variations for
cases I and II.

With respect to the above definition, we can write the expression for Gm1 as

IEbias 2I1 (x) IEbias 2I1 (x) 2I1 (x)

Gm1 = · = · = gm (2.71)
Vi I0 (x) Vt xI0 (x) xI0 (x)

Equation 2.71 gives an explicit equation for the large-signal transconductance of

the bipolar transistor. Thus, by using modified Bessel function table, we can easily
calculate the Gm ’s. For computing any harmonic, we can define a conversion transcon-
ductance from the first harmonic to the nth harmonic as Gmn where at the output we
would have

In In 2In (x) Von

Gmn = = = gm or = −Gmn ZL ( jnω0 ) (2.72)
Vi xVt xI0 (x) Vi

It is possible to generalize Equation 2.72 for the nth harmonic of the input frequency
when the output band-pass filter is tuned at the mth harmonic of the input. In this case,
the ratio of the output nth harmonic to the input phasor can be described as follows

Von R 2In (x) R

= −Gmn = −gm (2.73)
Vi 1 + jQ( mn − mn ) xI0 (x) 1 + jQ( mn − mn )

Equation 2.73 describes a comprehensive equation to calculate the output voltage of a

nonlinear transistor circuit for each of its harmonics with respect to the center frequency
of the resonant circuit. Figure 2.40 illustrates the ratio of large-signal transconductance
to its small-signal value as well as the conversion transconductances for the second
and the third harmonics.
Table 2.4 shows the value of solid line in Figure 2.40.
60 Chapter 2. Oscillators

Gmn(x)
gm

1
0.8 2I1(x)/xI0(x)
2I2(x)/xI0(x)
0.6
2I3(x)/xI0(x)
0.4
0.2
0
0 1 2 3 4 5 6 7 8 9 10
x
Figure 2.40: Ratio of large-signal transconductance normalized to small-signal
transconductance as well as the conversion transconductances for the second
and the third harmonics.

Table 2.4: Values of large-signal Gm normalized to small-signal gm as well as

the conversion transconductances for the second and the third harmonics.

x 0 1 2 3 4 5 6 7 8 9
2I1 (x)
1 0.893 0.698 0.540 0.432 0.357 0.304 0.264 0.234 0.209
xI0 (x)
2I2 (x)
0 0.214 0.302 0.307 0.284 0.257 0.232 0.210 0.192 0.176
xI0 (x)
2I3 (x)
0 0.035 0.093 0.131 0.148 0.152 0.149 0.144 0.138 0.131
xI0 (x)

Example 2.4 Consider Figure 2.33 where the input is VS = Vi cos ω0t with
ω0 = 2π (50 MHz). First, assume the band-pass filter is tuned to 50 MHz and
then assume it is tuned to 150 MHz. Derive the relations for the output voltage at
the first and the third harmonics.

Solution:
Using Equation 2.73, one may reach to Table 2.5.
2.10 Large-Signal Transconductance and Harmonic Tuned Amplifiers 61

Table 2.5: Normalized values of the first and the third harmonic voltages for
the output tuned to either of the first or the third harmonics.

H1 (x) , n = 1 H3 (x) , n = 3

Vo1 2I (x) Vo3 2I (x) RL
Vi = gmQ xI01 (x) RL cos 108 πt 8

Vi = gmQ xI03 (x) 1+ jQ 8 cos 3 × 10 πt
3

Vo1 2I1 (x) RL 8 Vo3 2I3 (x)
Vi = gmQ xI0 (x) RL cos 3 × 108 πt

Vi = gmQ xI0 (x) 1− jQ 8 cos 10 πt
3

Apparently, in the first case, we have first harmonic at the output with a high
gain and third harmonic at the output with a lower gain. In the second case, we
have the first harmonic at the output with a low gain and the third harmonic at the
output with a relatively higher gain.

In RF communication circuits, mostly narrowband applications are of interest.

However, investigation of harmonics and nonlinear behavior of circuits has a great
influence on the performance of RF circuits. The aforementioned equations are for
bipolar transistor; however, one may derive equations for MOS transistors as well. It is
also possible to reject the undesired harmonics more efficiently with a typical matching
band-pass network which is shown in Figure 2.41.

VCC
R
C R L 50Ω
R
RB 50Ω
Vout
Q1
+
Vs

Q3 Q2
CBypass

-VEE

Figure 2.41: Typical matching network for filtering undesired harmonics.

In the next section, we focus on oscillators based on tapped capacitor and tapped
inductor transformers. The inductive transformers are tunable with their number of
turns and have a good isolation.

Example 2.5 An oscillator can be constructed using a tightly coupled RF trans-

former in the feedback circuit as well. Determine the complex Barkhausen oscilla-
tion condition in the common-base tuned circuit oscillator depicted in Figure 2.42.
Note that CB and CE are considered as RF short circuit.
62 Chapter 2. Oscillators

VCC

R1

+ Q CE M12
CB V
R2 1 -
RE L2 L1 RL C1

VCC
Figure 2.42: A common-base tuned circuit oscillator.

Solution:
The equivalent circuit for the above oscillator is depicted in Figure 2.43.

M12
1:
L1
- -
GmV1 RL C1 L1 Vo Gin GE V1
+ +
Figure 2.43: The equivalent circuit for the common-base tuned circuit
oscillator.

Considering V1 as the feedback voltage phasor, the output collector voltage of

the oscillator is computed as

GmV1
Vo = 2 (2.74)
1
RL + jC1 ω − L1jω + ML12
1
(Gin + GE )

where Gin is the emitter’s input conductance.

Since
M12
V1 = Vo (2.75)
L1
Gm
Given the fact that the transistor’s emitter input conductance is Gin = α , then the
complex oscillation condition becomes
2.11 Differential Bipolar Stage Large-Signal Transconductance 63

M12
L1 G m
2 =1 (2.76)
1
RL + jC1 ω − L1jω + M12
L1
Gm
α + GE

Separating the real and the imaginary parts of Equation 2.76, one obtains two
distinct equations

1
C1 ω − =0 (2.77)
L1 ω
2
1 M12 1
RL + L RE
Gm (x) = 1 (2.78)
M12 1 M12
L1 1 − α L1

From the two above equations, the first one gives the oscillation frequency and the
second one through Gm (x) would determine the oscillation amplitude.

2.11 Differential Bipolar Stage Large-Signal Transconductance

Figure 2.44 depicts a bipolar differential stage tuned amplifier.
Assuming exponential characteristic for either of the transistors, one can write
v
ic1 = αIES eq(VBE0 +v1 )/kT = αIES eq(VBE0 + 2 )/kT (2.79)

v
ic2 = αIES eq(VBE0 +v2 )/kT = αIES eq(VBE0 − 2 )/kT (2.80)

VCC

LL RL CL CL RL LL

IC1 IC2
Vout
+
Q1 Q2
+
v

IE

VEE

Figure 2.44: A differential pair tuned amplifier.

64 Chapter 2. Oscillators

where VBE0 is the DC bias voltage of either of the transistors. Then

ic1
= eqv/kT (2.81)
ic2
Given
ic1 + ic2 = αIE = IC (2.82)
One can compute either of the collector currents using the above two equations:
IC IC h z i
ic1 = = 1 + tanh (2.83)
1 + e−z 2 2

IC IC h z i
ic2 = = 1 − tanh (2.84)
1 + e+z 2 2
where
qv v
z= = (2.85)
kT Vt
Assuming a large sinusoidal input voltage as
v = V1 cos (ωt) (2.86)
Either of the collector AC currents becomes
IC x
ic1,2 = ± tanh cos (ωt) (2.87)
2 2
where
qV1 V1
x= = (2.88)
kT Vt
Now using the above equations, one can compute the harmonic components of the
collector currents as
1 π 1 x
Z
an (x) = tanh cos (θ ) cos (nθ ) dθ (2.89)
π −π 2 2
Note that given the fact that the differential pair transfer characteristic has an odd
symmetry, an (x) functions would be zero for even values of n. Using the fundamen-
tal harmonic current of either of the collectors, one can calculate the large-signal
transconductance of the differential bipolar stage:
IC1 IC2 qIC a1 (x) 4a1 (x)
Gm (x) = =− = = gm (2.90)
V1 V1 kT x x
where
∂ ic1 ∂ ic2 qIC IC
gm = =− = = (2.91)
∂v ∂v 4kT 4Vt
Note that the DC and the fundamental harmonic output voltages at either of the
collectors become
2.12 Inductive and Capacitive Dividers (Impedance Transformers) 65

1
0.9
0.8

Gm(x)/gm
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0

10

12

14

16

18

20
0

8
Vin/VT

Figure 2.45: The evolution of the large-signal transconductance of a differential

pair tuned amplifier as a function of the normalized input voltage amplitude.

−
Vout = VCC − Gm (x) RLV1 cos (ωt) (2.92)

+
Vout = VCC + Gm (x) RLV1 cos (ωt) (2.93)

The differential fundamental harmonic voltage can be expressed as

+ −
Vout = Vout −Vout = 2Gm (x) RLV1 cos (ωt) (2.94)

Using this large-signal transconductance, one can compute the amplitude of oscillations
in a differential pair oscillator.

2.12 Inductive and Capacitive Dividers (Impedance

Transformers)
An ideal inductive transformer is depicted in Figure 2.46.
For the input impedance, we have

L V
Vs 1 VL 1
Rin = = m = 2 = 2 RL (2.95)
is miL m iL m

For example, if the load resistance is 1 kΩ, for m = 5, the input impedance will be 40 Ω.
Transformers play a crucial role in communication circuits for matching purposes.
As stated earlier by tuning the resonant band-pass filter, one may attain a desired
harmonic of the input signal at the output of a nonlinear circuit. The main role of
transformers is to extract the desired signal from the resonant circuit without degrading
its quality factor. However, it is instructive to know more about inductors before
introducing their use in transformers. Discrete inductors have a good quality factor just
for low-frequency applications. These inductors will fail at high frequencies due to
their parasitic capacitances and resistances. Nowadays, RF engineers desire to integrate
every thing on a single chip, thus on-chip inductors are of interest. However, because
66 Chapter 2. Oscillators

of their planar implementation, they will not have a good quality factor. Moreover,
these elements are relatively huge and bulky in size and their fabrication occupies a
huge area on the RF chip. It is possible to implement inductors at high frequencies
(say at a few GHz) using microstrip or printed circuit transmission lines as well.
Furthermore, realization of printed inductors is possible for monolithic microwave
integrated circuits at frequencies well above 5 GHz. In the next section, we introduce
circuits for impendence transformation and step-up and step-down voltage concepts.

2.12.1 Tapped Capacitive/Inductive Impedance Transformers

Figure 2.47 shows a tuned inductive transformer with a tap in the middle.
At it is depicted in Figure 2.47, a tap may separate the inductor in to two parts.
Here, the winding ratio is 1 : m which divides the voltage by an m ratio. The inductive
impedance transformer in Figure 2.47 can be modeled as Figure 2.48.
As depicted in Figure 2.48, by employing the impedance transformer, a resonant
circuit is made which can have a high quality factor. Now consider an input source
with 50 Ω impedance is applied at the input of Figure 2.48. This circuit is shown in
Figure 2.49.
If we assume that RP is a resistor modeling the loss of the resonant circuit, we can
define an unloaded quality factor as

RP
Qunloaded = (2.96)
Lω

is 1:m is/m
+

+
Vs RL VL=mVs

Rin

Figure 2.46: An ideal inductive transformer.

C RP

Figure 2.47: Inductive transformer with its loss and a capacitive load.
2.12 Inductive and Capacitive Dividers (Impedance Transformers) 67

(TXLYDOHQW
LQGXFWRU
P

/ & 53

,GHDO
WUDQVIRUPHU

Figure 2.48: A model of the inductive transformer with its loss.

RS=50Ω
1:m

+
Vs L C RP

Figure 2.49: Applying signal source to the inductive transformer.

Then, the loaded quality factor becomes

RP || RS × m2

QLoaded = (2.97)
Lω
Thus, as per Equation 2.96, the loading of the resonant circuit by the low impedance
source degrades the quality factor of the resonant circuit. However, if the value of
m2 RS is much larger than RP , the loaded quality factor would not be degraded as much.

Example 2.6 Is it possible to extract the signal of a resonant circuit by employing

a buffer instead of impedance transformer?
Answer:
Buffer stages are not of interest in the RF receiver chains due to the very low
available power of the sources; as such, we need the impedance matching at every
stage (for the maximum power transfer purpose). Furthermore, bipolar buffer
transistors are not of interest because of their finite base resistance. Similarly for
MOS transistors, the gate–source capacitor introduces finite capacitance which
may degrade the performance of the resonant circuit. Moreover, buffer design at
high-frequency applications may introduce instability and unwanted oscillation in
them.

Capacitive impedance transformers act like the inductive ones except that they have ca-
pacitive reactances instead of inductive ones at their input. Note that the modeling and
the behavior of capacitive/inductive coupling circuit are a straightforward procedure
and we focus here on their basic behavior.
Figure 2.50 shows a capacitive impedance transformer.
68 Chapter 2. Oscillators

At the resonance, one may obtain the input impedance of Figure 2.50 as

R
Rin = (2.98)
m2
where
C1 +C2
m= (2.99)
C1
Here, m > 1 means a step-up impedance transformation. Moreover, it is also possible
to define an equivalent capacitance as

C1C2
Ctotal = (2.100)
C1 +C2

Provided that for Rin (C1 +C2 ) ω ≥ 10, the above circuit can be modeled by a parallel
RLC circuit along with a step-up transformer as depicted in Figure 2.51. Furthermore,
the resonance condition becomes
C1 +C2
Lω − =0 (2.101)
C1C2 ω
The quality factor of this circuit will be

C1C2
Q= ωRT (2.102)
C1 +C2

where RT is the total equivalent parallel resistance of the tuned circuit. For large m, the
relative values of the capacitors usually follow CC21 1. For C2 C1 , Equation 2.102
can be approximately written as

Q ≈ C1 ωRT (2.103)

For instance, if C1 = 10 pF and C2 = 70 pF, then m = 8 and Ctotal = 8.75 pF, and a load
resistance of 1000 Ω will be transformed to 15.625 Ω. The equivalent circuit of this
step-up resonant impedance transformer is depicted in Figure 2.51 along with its dual
counter part which consists of an inductive step-up impedance transformer.

C1
L R
C2

Rin

Figure 2.50: Capacitive impedance transformer with a parallel inductance.

2.12 Inductive and Capacitive Dividers (Impedance Transformers) 69

1:m
L1 L1+L2
C GL C
GL L2
Gin=GL/m2

1:m
C1C2
C1
C1+C2
L GL L
GL C2
Gin=GL/m2

Figure 2.51: Circuit models for inductive and capacitive impedance

transformers.

Before using the models of Figure 2.51 for the step-up transformers, let’s verify
Equation 2.98 through 2.103 using the admittance or the impedance matrices of the
corresponding circuits. Now, let’s consider Figure 2.52.
One may obtain the admittance matrix of Figure 2.52 as

I1 C1 +C2 −C1 V1
= jω (2.104)
I2 −C1 C1 V2

Or in expanded form

I1 = jω (C1 +C2 )V1 − jωC1V2 (2.105a)

I2 = − jωC1V1 + jωC1V2 (2.105b)

Now we derive the relation for the output admittance when the input is loaded with the
conductance, GL . The circuit is shown in Figure 2.53.
We can write at the input

I1 = −GLV1 (2.106)

I2

I1 C1 +

+ V2
V1 C2

Figure 2.52: Step-up capacitive voltage transformer.

70 Chapter 2. Oscillators

I2
+
I1 C1

+ V2
V1 GL C2

Yout

Figure 2.53: Step-up capacitive voltage transformer with loaded input.

Employing Equation 2.105a, we may obtain

I1
I1 = jω (C1 +C2 ) − jωC1V2 (2.107)
−GL
Thus, the ratio of I1 to V2 can easily be derived from Equation 2.107 as
I1 −GLV1 − jωC1
= = (2.108)
V2 V2 1 + jω(CG1L+C2 )

Finally, we have
V1 jωC1
= =A (2.109)
V2 GL + jω (C1 +C2 )
Using Equation 2.105b, one obtains

I2 = − jωC1 AV2 + jωC1V2 (2.110)

Thus, the output admittance will be

I2 jωC1
Yout = = − jωC1 A + jωC1 = − jωC1 + jωC1 (2.111)
V2 GL + jω (C1 +C2 )
We may rearrange Equation 2.111 as

jωC1 GL + jωC2
Yout = jωC1 1 − = jωC1 (2.112)
GL + jω (C1 +C2 ) GL + jω (C1 +C2 )
Multiplying the numerator and the denominator of Equation 2.112 by the denominator’s
conjugate, one obtains
!
GL 2 + ω 2C2 (C1 +C2 ) − jωC1 GL
Yout = jωC1 (2.113)
GL 2 + ω 2 (C1 +C2 )2

Now, considering a high quality factor for this circuit, it is imposed that the short-circuit
quality factor should be larger than unity

(C1 +C2 ) ω GL (2.114)

2.12 Inductive and Capacitive Dividers (Impedance Transformers) 71

Regarding Equation 2.109, then the voltage ratio would be approximated by

V1 C1
A= ≈ (2.115)
V2 C1 +C2

Therefore, considering the fact that (C1 +C2 )2 ω 2 G2L , Equation 2.113 is reduced to
Equation 2.116:
2
C1 C1C2 GL
Yout ≈ GL + jω = 2 + jωCtotal (2.116)
C1 +C2 C1 +C2 m
C1 +C2
where m = C1 . Finally, the overall quality factor will be

1 C1C2 (C1 +C2 ) ω C2

Q = ReqCtotal ω = 2 · ω= · (2.117)
C1 C1 +C2 GL C1
C1 +C2 GL

If (C1 +C2 ) ω > GL and C2 > C1 , and the quality factor is greater than 10, the
equivalent circuit shown in Figure 2.51 will be valid. However, if the quality factor is
less than 10, the precise relation for the calculation of the admittance (Equation 2.113)
should be used.
The same method applies for inductive transformers. Consider Figure 2.54.
Impedance parameters of Figure 2.54 can be derived as

V1 L L2 I1
= jω 2 (2.118)
V2 L2 L1 + L2 I2

Or in expanded form

V1 = jωL2 I1 + jωL2 I2 (2.119a)

V2 = jωL2 I1 + jω (L1 + L2 ) I2 (2.119b)

The loaded circuit for inductive transformer is shown in Figure 2.55.

At the input, we have

I1 = −GLV1 (2.120)

I2

I1 L1 +

+ V2
V1 L2

Figure 2.54: Step-up inductive voltage transformer.

72 Chapter 2. Oscillators

I2
+
I1 L1

+ V2
V1 GL L2

Yout

Figure 2.55: Step-up inductive voltage transformer with loaded input.

Using Equation 2.118, we can write

V1 = jωL2 (−GLV1 + I2 ) (2.121)

Thus, we will have

V1 jωL2
= =B (2.122)
I2 1 + jωL2 GL

Again, using Equation 2.119b gives

V2 = jωL1 I2 + BI2 (2.123)

Finally, the output admittance will be

I2 1 1 + jωL2 GL
Yout = = jωL2
= (2.124)
V2 jωL1 + 1+ jωL jωL 2 + jωL1 − ω 2 L1 L2 GL
2 GL

Given the fact that, in the tapped inductor transformer, the short-circuit quality factor
should be greater than unity, it is deduced that

L1 + L2
> GL (2.125)
L1 L2 ω

After some manipulations, Equation 2.124 will be reduced to Equation 2.126

2
1 L2
Yout ≈ + GL (2.126)
j (L1 + L2 ) ω L1 + L2

As stated earlier in capacitive step-up transformer, with the condition stated in rela-
tion 2.125, if the quality factor of the inductive transformer is greater than 10 and
L1 > L2 , the above approximation will be valid, and the equivalent circuit shown
in Figure 2.51 can be used. Otherwise, the precise relation for the admittance
(Equation 2.124) should be employed.
2.12 Inductive and Capacitive Dividers (Impedance Transformers) 73

Example 2.7 Calculate the output impedance of the circuit depicted in

Figure 2.56 at 1 GHz for two cases
(a) R = 50 Ω and C1 = C2 /9 = 3.18 pF.
(b) R = 50 Ω and C1 = C2 /9 = 0.318 pF.

C1

R C2 Rin

Figure 2.56: Calculation of the output impedance of the loaded capacitive

transformer.

Solution:
(a) Here the short-circuit quality factor becomes

(C1 +C2 ) ω
= 10 (2.127)
GL

Equation 2.113 gives an exact value of the output admittance as

!
GL 2 + ω 2C2 (C1 +C2 ) − jωC1 GL
Yout = jωC1 = 0.0002+j0.0180 (2.128)
GL 2 + ω 2 (C1 +C2 )2
1
or Zout = = 0.6172 − j55.55
Yout

If we use the approximation stated in Equation 2.116, we reach to

2
C1 C1C2
Yout = GL + jω = 0.0002 + j0.01797 (2.129)
C1 +C2 C1 +C2
1
or Zout = = 0.6193 − j55.64
Yout

As it is obvious from Equations 2.128 and 2.129, the results are quite close to each
other.
(b) Here the short circuit quality factor becomes

(C1 +C2 ) ω
=1 (2.130)
GL
74 Chapter 2. Oscillators

Equation 2.113 gives the exact value of the output admittance as

!
GL 2 + ω 2C2 (C1 +C2 ) − jωC1 GL
Yout = jωC1 =0.0001+ j0.0018 (2.131)
GL 2 + ω 2 (C1 +C2 )2
1
or Zout = = 30.77 − j553.8
Yout

If we use the approximation stated in Equation 2.116, we reach to

2
C1 C1C2
Yout = GL + jω = 0.0002 + j0.0018 (2.132)
C1 +C2 C1 +C2
1
or Zout = = 60.975 − j548.78
Yout

As it is obvious from Equations 2.131 and 2.132, the results don’t match completely,
that is, the approximation is not valid for a low quality factor circuit.

2.13 Analysis of Large-signal Loop Gain of an Oscillator

Now that we have got acquainted to the large-signal transconductance of a nonlin-
ear device, we are able to analyze the oscillator behavior more precisely. Consider
Figure 2.57 where parasitic capacitances are ignored for the sake of simplicity.
The AC model of Figure 2.57 is shown in Figure 2.58.
Here the resistance RP represents the RF losses of the inductor and the capacitors.
Using the equivalent circuit of the capacitive impedance transformer of Figure 2.51,
we can reduce Figure 2.58 to the equivalent circuit of Figure 2.59.
The output collector voltage of the oscillator can be calculated as
GmVi
Vout = 1 1
(2.133)
jωCeq + jωLP + RP + n2 Gin

VCC
L

Q C1
RP
C2
RB

-VCC

Figure 2.57: A Colpitts oscillator core circuit.

2.13 Analysis of Large-signal Loop Gain of an Oscillator 75

+
Q C1
LP RP
Vout
+
C2 V
Is i
- -

Figure 2.58: An AC model of the oscillator core of Figure 2.57.

Q

*P9L &HT /3 53
9RXW *LQ 9L

Figure 2.59: Equivalent circuit of the Colpitts oscillator.

Here, we have
C1 C1C2
n= , Ceq = (2.134)
C1 +C2 C1 +C2
The input emitter voltage Vi is (note that here m < 1)
Vi = nVout (2.135)
Now, replacing Vout in Equation 2.133, we arrive at an expression for the closed-loop
gain of the oscillator:
nGm
ACL ( jω) = 1
=1 (2.136)
jωCeq + + R1P + n2 Gin
jωLP

Equation 2.136 describes the oscillation condition of the oscillator (Barkhausen’s

oscillation condition). Indeed, the large-signal input at the emitter is amplified by the
large-signal gain of the oscillator and the output voltage at the collector is divided
by the capacitive division ratio of the transformer m, and is fed back to the emitter.
The whole loop gain in the large-signal regime and at the oscillation frequency should
become equal to unity (1∠0). Note that in the small-signal regime, the oscillation
begins with the small-signal noise voltage at the emitter, which is amplified by the
small-signal gain of the transistor (note that normally in every oscillator the small-
signal gain is much larger than the large-signal gain). As the feedback signal grows, the
small signal-gain is gradually compressed to its large-signal value. Furthermore, the
large-signal input conductance of the emitter can be approximated by the large-signal
transconductance divided by α. That is
Gin
Gm = (2.137)
α
76 Chapter 2. Oscillators

As it is seen in Equation 2.136, the right-hand side of the equation is purely real, so
we can separate the real and the imaginary parts of Equation 2.136 and obtain the
following pair of equations:
1
ωCeq − =0 (2.138)
ωLP
1
RP
Gm = (2.139)
n 1 − αn

Equation 2.138 gives the oscillation frequency and by Equation 2.139, we can obtain
the oscillation amplitude through the large-signal transconductance. Here our focus
was on the first harmonic, because other harmonics are attenuated by the high-Q tuned
resonant circuit to some extent.
Example 2.8 Consider Figure 2.60, where the transistor has a current gain
α = 0.99 and a parasitic collector–base capacitance of 0.2 pF and a parasitic base–
emitter capacitance of 5 pF. Given the 1.5 mA emitter current source, compute the
oscillation amplitude and the oscillation frequency in this circuit.

S)

4 S)
Q+ Nȍ

S) P$ S)

9&& 9 9&& 9

Figure 2.60: A Colpitts oscillator with parasitic capacitances.

Solution:
An important point in this example is the absorption of parasitic capacitances in
the resonant circuit. First, we calculate the capacitive transformer ratio n as

10
n= = 0.087 (2.140)
10 + 100 + 5
From Equation 2.139, we obtain
1
1000
Gm 1 = = 12.6 mf (2.141)
0.087 1 − 0.087
0.99

We can easily calculate the small-signal gm as

2.13 Analysis of Large-signal Loop Gain of an Oscillator 77

1.5 mA
gmQ = 0.99 × = 57.1 mf (2.142)
26 mV
Thus, using Equations 2.141 and 2.142, we will have

Gm 1
= 0.220 (2.143)
gmQ

Using Equation 2.143 and Table. 2.4, x can be obtained as

x = 8.5Vt = 8.5 (26 mV) = 221 mV (2.144)

The voltage obtained from Equation 2.144 is that of the base–emitter junction. The
collector voltage is higher by the ratio of 1/m, thus

x 0.221
VC = = = 2.54 V (2.145)
n 0.087
By assuming the supply voltage equal to 5 V, the output voltage will be

VCtotal = 5 + 2.54 cos (2π f0t + ϕ) (2.146)

Note that the parasitic collector–base capacitance will be added to the equivalent
capacitance of the capacitive divider. So, the total capacitance would become

C1 (C2 +CBE )
Ctotal = +CBC = 9.33 pF (2.147)
C1 +C2 +CBE

The oscillation frequency for Equation 2.146 will be

1 1
f0 = √ = 164.77 MHz (2.148)
2π 100 nH × 9.33 pF

Here we verify the required condition for the capacitor tapped transformer model
that is
(C1 +C2 ) ω
= 114 (2.149)
GL

which is much larger than unity and therefore, the tapped transformer equivalent
circuit is valid here.

2.13.1 Increasing the Quality Factor and the Frequency Stability with a Crystal
Consider Figure 2.61.
As it is depicted in Figure 2.61, for increasing the quality factor, a crystal is placed
in series within the feedback loop. Normally, the parallel RLC circuit’s resonance
frequency is chosen the same as that of the crystal. However, if the frequency of
78 Chapter 2. Oscillators

Cµ

Q C1
L RL

Cπ IE C2

-VCC +VCC

Figure 2.61: A Colpitts oscillator with series crystal.

resonant circuit is slightly different from the crystal series resonance, the oscillation
frequency will change to satisfy the Barkhausen’s oscillation condition. Any phase
change in the loop should be compensated by the crystal. However, due to sharp phase
characteristic of the crystal, this will result in a very small frequency change. It is
possible to show the series crystal equivalent model as presented in Figure 2.62.
Now, we are going to investigate the resonant circuit detuning more precisely. This
will result in Q degradation. Figure 2.63 shows the crystal impedance behavior about
its series resonance.
Similarly, the impedance of the parallel resonant circuit is shown in
Figure 2.64.
In this case, assume that the resonant frequency of parallel RLC is higher than the
crystal resonant frequency. The circuit will oscillate near the crystal resonant frequency
( fS ) due to its higher quality factor. The tank circuit introduces a finite phase change
as ∆Φ in the loop gain. Thus, the crystal phase characteristics should compensate this
phase by introducing −∆Φ in the loop gain to maintain the Barkhausen’s oscillation
condition. While the phase characteristics of the crystal is sharp, this phase change
does not alter the oscillation frequency significantly. It is noteworthy that the amplitude
of oscillation might be altered a little bit as well. The interested reader is referred to
section 2.20 for further details.
In another topology, the crystal might be used as an inductive reactance within the
resonant circuit of a Colpitts oscillator as depicted in Figure 2.65.
Here, with a slight shift of the oscillation frequency with respect to the crystals’
resonant frequency, the Barkhausen oscillation condition can be satisfied. Assuming
the oscillation frequency near to fs , and further neglecting the effect of CP , the crystal
impedance can be represented by

ZX = R + jX (2.150)

LS CS RS

ZX

Figure 2.62: An equivalent model for series crystal.

2.13 Analysis of Large-signal Loop Gain of an Oscillator 79

|ZX|

rs

ZX fS f

90

fS f

-90

Figure 2.63: Impedance behavior of the crystal about its series resonance.
|Ztank|
RP

Ztank fS ftank f

90

∆Φ
fS ftank f

-90

Figure 2.64: Variations of the impedance of the parallel resonant circuit about
the resonance frequency.

where
R = rs (2.151a)
∆f
X = 2Q0 rs (2.151b)
fs
Here rs is the crystal’s series resistance and Q0 = Lsrωs s is the crystal’s unloaded quality
factor. For a series resonant circuit, one can write
1
ZX = rs + jLs ω − j (2.152)
Cω
80 Chapter 2. Oscillators

-VCC

RFC

Q C1

IE C2

-VCC

Figure 2.65: Colpitts-like crystal oscillator; the crystal operates in an inductive

mode.

Or

ω ωs ∆ω
ZX = rs 1 + jQ0 − = rs 1 + j2Q0 (2.153)
ωs ω ωs
Here, ω = ωs + ∆ω. For the resonance condition, we should have

C1 +C2
X= (2.154)
2π fsC1C2
or
C1 +C2 ∆f
= 2Q0 rs (2.155)
2π fsC1C2 fs
The point is that we have put fs instead of fo in the left-hand side of Equation 2.155.
The reason being the fact that ∆ f is extremely small compared to fs . By resolving
Equation 2.155, one simply obtains ∆ f and the oscillation frequency is determined as
fo = fs + ∆ f (2.156)
The oscillation amplitude could be obtained from the following
mGx
Gm (x) = 1
(2.157)
1 − mα
where
C1 +C2
m= (2.158)
C1
and the crystal conductance is
R
Gx = 2 (2.159)
R + X2
With the above-mentioned procedure, given the crystal parameters (rs , Q0 , and fs ), one
can easily determine the oscillation frequency and the oscillation amplitude. The same
procedure can be used for a Hartley-like crystal oscillator.
2.13 Analysis of Large-signal Loop Gain of an Oscillator 81

2.13.2 Oscillator Harmonics Calculation

It is also instructive to calculate other harmonics in a bipolar transistor oscillator circuit.
The oscillator voltage harmonics are proportional to the harmonic currents as well
as the load impedance at the harmonic frequencies. As such, the ratio of the second
harmonic to the first harmonic can be written as Equation 2.160:

V2 I2 (x) ZL (2ω0 ) I2 (x) 2

= · ≈ (2.160)
V1 I1 (x) ZL (ω0 ) I1 (x) 3 jQ

Equation 2.160 describes the amplitude ratio as well as the phase difference. A more
general form of Equation 2.160 for the kth harmonic will be

Vk Ik (x) ZL ( jkω0 ) Ik (x) k

= · ≈ (2.161)
V1 I1 (x) ZL ( jω0 ) I1 (x) jQ (k2 − 1)

It is possible to calculate the ratio of each harmonic to the main harmonic by Equa-
tion 2.161. In Equation 2.161, the load is impedance and is the one which is seen at
the collector of the transistor. Given the fact that harmonic currents are smaller than
the fundamental current and Q is large, it is obvious from Equation 2.161 that the
harmonic voltages are quite smaller than the fundamental voltage.
In order to extract the oscillator signal, we should not load the tank circuit di-
rectly because its quality factor will be degraded. It is possible to use either an
impedance transformer or extract the output from the emitter (where there is a low
output impedance). This point is illustrated in Figure 2.66.
As it is stated earlier, the output impedance of Figure 2.66 will decrease by p2 and
could reach to 50 Ω. An appropriate value of p (p < 1) will not degrade the quality
factor of tank circuit as much.

VCC VCC
1:P

RL rLoad RL LL

Q C1 Q C1
C∞

rLoad
Is C2 Is C2

(a) (b)

Figure 2.66: Extracting the output signal of an oscillator without degrading its
quality factor.
82 Chapter 2. Oscillators

2.14 Colpitts Oscillator with Emitter Degeneration

Consider Figure 2.67 where the equivalent bias circuit of the transistor is shown at the
input.
In this configuration, the operating point of the transistor will be modified by
the input large-signal by a certain coefficient. That is the input DC current and
consequently the emitter DC current will increase due to the large-signal imposition.
It can be shown that the overall DC current in the presence of the large-signal input
voltage will take the following form
!
ln (I0 (x))
IE0 = IEQ 1 + V
(2.162)
λ
Vt

where I0 (x) is the zeroth-order modified Bessel function of the first kind, IEQ is the
operating point DC current of the emitter (in the absence of the large-signal), and Vλ is
defined as

Vλ = Vdroppedbase +Vdroppedemitter = RB IBQ + RE IEQ ≈ RE IEQ (2.163)

Actually, Vλ is the DC voltage drop across RE . Consequently, the large-signal transcon-

ductance of the transistor will be modified by the same coefficient as in Equation 2.164:

! !
αIEQ ln(I0 (x)) 2I1 (x) ln(I0 (x)) 2I1 (x)
Gm = 1+ Vλ
= gmQ 1 + Vλ
(2.164)
Vt xI0 (x) xI0 (x)
Vt Vt

As we increase RE , the voltage drop across it for a constant current will increase (Vλ
increases and the coefficient approaches unity), and as a result, it acts approximately
as a current source. The evolution of the transconductance of a bipolar transistor stage
biased with an emitter resistor instead of a current source is depicted in Figure 2.68.

VCC

CL RL LL

RB Vout
Q
Vss

RE
Vs

Figure 2.67: Common-emitter amplifier with emitter degeneration.

2.15 MOS Stage Large-Signal Transconductance 83

1
Vλ/Vt=20
0.8
Gm(x)/gmQ Vλ/Vt=40
Vλ/Vt=60
0.6 Vλ/Vt=80
Vλ/Vt=100
0.4

0.2

0 x
0 2 4 6 8 10 12 14 16 18 20

Figure 2.68: The evolution of the large-signal transconductance of a bipolar

transistor biased with an emitter resistor instead of a current source (normalized
DC voltage drop across the emitter resistor as the parameter).

2.15 MOS Stage Large-Signal Transconductance

In a similar derivation, it is possible to compute the large-signal transconductance of a
MOS transistor having its I −V characteristics. This point is shown in Figure 2.69.
A MOS tuned amplifier stage is depicted in Figure 2.70. We assume a large signal
is applied to the gate input. The large capacitors CG and CS are considered as AC
short-circuit at the RF carrier frequency. The output RLC circuit is considered to have
a high quality factor and is tuned to the carrier frequency.
Assuming above the threshold bias voltage and a square law characteristics in
the saturation region, one can compute the drain source current from the square law
characteristics:

IDS = k(VGS −VTH )2 (2.165)

ID

VGS
VTH
I
Gm1= ~D1
VGS

Figure 2.69: Typical I−V characteristic of MOS transistor (ṼGS is the gate–
source’s AC voltage phasor).
84 Chapter 2. Oscillators

VDD

VGG CL RL LL

RFC
Vout
M
+
CG VGS0 -
V1cos(ωt)
I0 CS

Figure 2.70: Constant current MOS stage tuned amplifier for computation of
the large-signal transconductance.

The drain–source DC current at the bias voltage is

IDS0 = k(VGS0 −VTH )2 (2.166)
The small-signal transconductance can be computed as
gm = 2 k (VGS0 −VTH ) (2.167)
The total drain–source current under the large-signal excitation can be computed as
iDS = k(VGS0 −VTH +V1 cos (ω0t))2 (2.168)
The DC, the fundamental, and the second harmonic currents are obtained as
V12 V2

2
iDS = k (VGS0 −VTH ) + + 2 k (VGS0 −VTH )V1 cos (ω0t) + k 1 cos (2ω0t)
2 2
(2.169)
Now, neglecting the second harmonic, one can express the output drain–source
current as
 
2 (VGS0 −VTH )V1 cos (ω0t) 
iDS ≈ I0 1 + h (2.170)

V2
i 
(VGS0 −VTH )2 + 21

where I0 is the current source’s bias current. Now, the large-signal transconductance is
defined as
 
I1 2 (VGS0 −VTH )
Gm = = I0  h (2.171)
 
V12
i
V1 (V −V ) + 2
GS0 TH 2
2.15 MOS Stage Large-Signal Transconductance 85

1
0.9
0.8

Gm(x)/gm
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0

0.5

1.5

2.5

3.5

4.5

5
x=V1/(VGS0-VTH)

Figure 2.71: Normalized transconductance variations of a MOS tuned amplifier

stage as a function of the normalized input voltage.

The normalized large-signal transconductance becomes

Gm I0
= h (2.172)
V2
i
gm k (VGS0 −VTH )2 + 21

Or in another form

Gm I0
= (2.173)
V12
h i
gm 2
k(VGS0 −VTH ) 1 +
2(VGS0 −VTH )2

Given the fact that at the operating point, one can write

I0 ≈ k(VGS0 −VTH )2 (2.174)

The normalized large-signal transconductance is simplified to the following

Gm 1
=h (2.175)
V12
i
gm 1+
2(VGS0 −VTH )2

V1
Let x = VGS0 −VTH ,

Gm (x) 1
= 2 (2.176)
gm 1 + x2

The normalized MOS stage transconductance is depicted in Figure 2.71.

This large-signal transconductance can be employed in the MOS oscillator circuit
design/analysis for computation of the amplitude of oscillation.
86 Chapter 2. Oscillators

2.16 Differential MOS Stage Large-Signal Transconductance

A differential MOS tuned amplifier is depicted in Figure 2.72.
Considering a square law transfer characteristic of the MOS transistors and assum-
ing that the differential voltage is equally divided between the pair of transistors (at
least for a limited range of differential voltage), one can write
v 2 v
I1 = k VGS0 −VTH + for < |VGS0 −VTH | (2.177)

2 2

v 2 v
I2 = k VGS0 −VTH − for < |VGS0 −VTH | (2.178)

2 2
Then
2
I1 VGS0 −VTH + 2v
= 2 (2.179)
I2 VGS0 −VTH − 2v

Given

I1 + I2 = I0 (2.180)

The difference in current becomes

I1 − I2 = 2 k (VGS0 −VTH ) v (2.181)

The normalized difference current can be calculated as

∆I (VGS0 −VTH ) v
= 2 (2.182)
I0 (VGS0 −VTH )2 + v4

VDD

LL RL CL CL RL LL

I1 I2
Vout
+
M1 M2
+
v

I0

Figure 2.72: A differential MOS pair tuned amplifier.

2.16 Differential MOS Stage Large-Signal Transconductance 87

iD2/I0 1
iD1/I0
0.9
0.8
0.7
0.6
I/I0
0.5
0.4
0.3
0.2
0.1
-2.5

-2

-1.5

-1

-0.5

0.5

1.5

2.5
V/(VGS0-VTH)
Figure 2.73: Variations of the differential pair drain currents as a function of
the normalized differential voltage in a MOS differential pair.

Either of the drain currents can be expressed as

 
v
I0  VGS0 −VTH
I1 = 1+  (2.183)
2 v2
1+ 2
4(VGS0 −VTH )

 
v
I0  VGS0 −VTH
I2 = 1−  (2.184)
2 v2
1+ 2
4(VGS0 −VTH )

The normalized difference current can be expressed as

v
(VGS0 −VTH )
∆iDD = I0 (2.185)
v2
1+
4(VGS0 −VTH )2

This model describes approximately the nonlinear behavior of a differential MOS

transistor pair. The variations of a real differential pair drain currents as a function of
the differential input voltage are depicted in Figure 2.74. Although the mathematical
expressions are quite different, it is noticeable that these currents’ variations are quite
similar to those of the bipolar differential pair.
Note that Equations 2.183 through 2.185 are valid for VGS0 v−VTH ≤ 2. If VGS0 v−VTH >

2, then I1 = I0 and I2 = 0, and if VGS0 v−VTH < −2, then I1 = 0 and I2 = I0 . As such, a
nonlinear transfer characteristic has been specified for a MOS differential pair for the
whole span of possible input voltages.
The differential pair small-signal transconductance becomes

I0
gmd = (2.186)
VGS0 −VTH
88 Chapter 2. Oscillators

For large-signal AC drive, we can extract the large-signal transconductance of the

differential MOS stage:
V1 cos(ωt)
(VGS0 −VTH )
∆iDD = I0 (2.187)
V1 2 cos2 (ωt)
1+
4(VGS0 −VTH )2

Defining the normalized AC input voltage as

V1
x= (2.188)
VGS0 −VTH

The harmonic components of the large-signal output current can be computed as

1 x cos θ
Z π
bn (x) = 2 cos nθ dθ (2.189)
π −π 1 + x4 cos2 θ

Care should be taken that these computations are valid for x ≤ 2. Note that given
the fact that the differential MOS pair transfer characteristic has an odd symmetry,
bn (x) functions would be zero for even values of n. The fundamental harmonic current
becomes

I1 = I0 b1 (x) (2.190)

Now the large-signal differential transconductance can be calculated as

I1 I0 b1 (x) b1 (x)
Gmd (x) = = = gmd (2.191)
V1 (VGS0 −VTH ) x x

1
0.9
Gmd(x)/gmd

0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0

0.5

1.5

2.5

3.5

4.5

x=V1/(VGS0-VTH)
Figure 2.74: Normalized transconductance variations of a MOS differential
tuned amplifier stage as a function of the normalized input voltage.
2.17 An Oscillator With a Hypothetical Model 89

or

Gmd (x) b1 (x)

= (2.192)
gmd x

For the case where the large input signal does not satisfy the condition x ≤ 2, the
transistor pair drains would switch between zero and I0 . As such, the first harmonic
currents would have a value as
4
I1 = I0 (2.193)
π
The large-signal transconductance becomes
I0
I1 4 I0 4 VGS0 −VTH 4
Gmd (x) = ≈ = V1
= gmd (2.194)
V1 π V1 π VGS0 −VTH
πx

or

Gmd (x) 4
≈ (2.195)
gmd πx
√
This is valid for x ≥ 2 2.
As such, the overall normalized differential MOS stage transconductance is de-
picted in Figure 2.74.
This large-signal transconductance can be employed in the differential MOS
oscillator circuit design/analysis for computation of the amplitude of oscillation.

2.17 An Oscillator With a Hypothetical Model

Consider Figure 2.75 where a hypothetical active element is shown within a Colpitts
oscillator circuit. The I −V characteristics of the hypothetical element, about the bias
point, are given in Equation 2.196

+\SRWKHWLFDO 9RXW P
. HOHPHQW 9L

,=
.
& / 5/
9=
9RXW

5LQN 9L
,V &

9ELDV

Figure 2.75: Oscillator with a hypothetical amplifier.

90 Chapter 2. Oscillators

IZ = B0 + B1VZ + B2VZ2 + B3VZ3 (2.196)

In Equation 2.196, VZ is considered as a sinusoidal signal as VZ = Vi cos ωt, so we have

B2 2
IZ = B0 + B1Vi cos(ω0t) + V (1 + cos(2ω0t)) + B3Vi3 cos3 (ω0t) (2.197)
2 i

We are looking for a gain at the fundamental frequency in Equation 2.197. Thus,
one may obtain the first harmonic large-signal transconductance as

B1Vi + 34 B3Vi 3 3
Gm1 = = B1 + B3Vi 2 (2.198)
Vi 4

Therefore, the large-signal loop gain will be

1 3 1
ALs = Gm1 RL ||m2 Rin,k = B1 + B3Vi 2 RL ||m2 Rin,k (2.199)
m 4 m

C1 +C2
Here, m = C1 . Or the oscillation condition becomes explicitly as

mRL Rin 3
B1 + B3Vi 2 = 1 (2.200)
RL + m2 Rin 4

and
1 C1C2 ω0
− =0 (2.201)
Lω0 C1 +C2

2.18 A MOS Oscillator with Differential Gain Stage

Consider Figure 2.76 where a differential MOS oscillator is depicted with a transformer-
type feedback.
The I −V characteristics of the circuit are also shown in Figure 2.76. As it was
described in section 2.17, the large-signal transconductance Gm of this stage can be
obtained from the I −V characteristics of the differential pair. The oscillation condition
for this oscillator becomes as described in Equation 2.202:

mGm
ALs ( jω) = j
= 1∠0 (2.202)
jCω − Lω + R1 + m2Yin

where Yin is the input admittance of the differential pair. The above equation describes
the closed-loop gain of the oscillator. Considering the fact that the input admittance of
2.19 Voltage-Controlled Oscillators 91

VDD ID
1:m
C R
VBias
id Vid

+ M2 M1
vid - Gm

Yin Is

Vid

Figure 2.76: Differential amplifier for the oscillator.

the MOS differential pair is mainly capacitive, at the resonant frequency, regarding the
closed loop gain, one can write
1
Cω0 − + m2Yin ( jω0 ) = 0 (2.203)
Lω0
ALs ( jω0 ) ≈ mGm R = 1 (2.204)

Having the large-signal transconductance of the differential MOS pair as a function of

the input fundamental harmonic voltage amplitude, the oscillation amplitude can be
computed from Equation 2.204.

2.19 Voltage-Controlled Oscillators

Voltage-controlled oscillators are widely used in RF communication circuits. VCO
is a block where we can change the oscillation frequency by a certain input voltage.
Historically, this was done with mechanically variable capacitances where a sample of
it is shown in Figure 2.77.
However, nowadays instead of VCOs frequency synthesizers are widely used. In
integrated circuits, we employ variable capacitances which are tunable with voltage.
Figure 2.78 shows a typical VCO where the transistors M3 and M4 are used as voltage-
controlled capacitors (the control voltage being VC ). These varactors would be in
parallel with L1 and L2 , respectively, AC wise (C1 is relatively large), and as such they
would directly affect the oscillation frequency along with C3 and C2 . The transistors
M1 and M2 provide the required loop gain in this oscillator.

2.19.1 Different Types of Varactors and their Bias

Voltage variable capacitors can be implemented via reverse-biased diodes as well. The
area of the diode is sufficient to achieve a certain reverse capacitance. Figure 2.79
shows a typical C −V characteristic of a diode.
92 Chapter 2. Oscillators

5RWRU
SODQHV

6KDIW

6WDWRU
SODQHV

Figure 2.77: Mechanically variable capacitor.

The capacitor is biased by a negative voltage where the reverse DC current of the
diode is negligible. The negative voltage should be less than the breakdown voltage of
the diode junction. Moreover, it is possible to switch between capacitors to change the
frequency coarsely. Figure 2.80 shows the implementation of a variable capacitance in
an oscillator.
At low frequency, the bias current of the variable capacitors passes thorough the
inductor (note that the inductor is short-circuit at low frequencies). The oscillation
frequency of the circuit is determined by the resonance of the total capacitance of

VDD
L1 L2

M3 M4
M2 M1
C2 C3

IDC
R
VC
C1

Figure 2.78: Cross-coupled VCO with voltage variable MOS capacitors.

2.19 Voltage-Controlled Oscillators 93

C1 and C2 plus the capacitances of the varactor with the inductor, L. Furthermore, it
is possible to modulate the frequency of oscillation by a time-varying voltage at the
cathode of the varactors. The bias resistance of the varactors (Rbias ) is assumed to
be sufficiently large in order to avoid the loading of the tuned circuit or else an RFC
should be added in the bias circuit. At high frequencies, the varactor capacitances are
in series.
As Figure 2.79 suggests, the variable capacitor is nonlinear which may result in
signal distortion (generation of RF harmonics). In Figure 2.80, the oscillation voltage
is divided between the two varactors, resulting in better linearity. Indeed, a varactor
pair allows for double AC voltage swing, and thus, a lower distortion can be achieved
by a varactor pair at the output (with respect to a single varactor oscillator). In fact, the
bias voltage across these varactors changes their values and these changes will result
in resonant frequency variations. Three different kinds of VCOs with their varactor
implementation are shown in Figure 2.81.
In Figure 2.81(a), the tuning voltage can select any value greater than zero and vari-
able capacitance will experience the substrate noise. Tuning voltage in Figure 2.81(b)
can have only values smaller than supply voltage for staying in reverse bias. It also
experiences the supply voltage noise and its ripples. Finally, Figure 2.81(c) will have
the same tuning voltage as Figure 2.81(b). In this case, from the supply point of view,
the two varactors are in parallel; however, from the RF point of view, those are in series,
therefore, the supply noise voltage is canceled out in the RF circuit. Furthermore, the
nonlinear behavior of the VCO is ameliorated in this case.

&

2SHUDWLRQ
9'
UHJLRQ

Figure 2.79: Capacitance variations of a diode as a function of its voltage.

4 &
/ 5 5ELDV
9&&9&RQWURO
5HYHUVH
& ELDV
,V
9&& 9&&

Figure 2.80: A Colpitts voltage-controlled oscillator using a pair of varactors.

94

VCC VCC VCC

VC1 VC1
L R L R VBias L R VBias
C∞ VC2

Q C1 C∞ Q C1 Q C1

VBias
Vbias Vbias Vbias
Is C2 VC1 Is C2 Is C2

(a) (b) ( c)

Figure 2.81: Voltage-controlled oscillators with different kinds of varactor implementations.

Chapter 2. Oscillators
2.19 Voltage-Controlled Oscillators 95

Example 2.9 Consider the given differential MOS pair in the circuit of
Figure 2.82.

I1 I2

V1 M1 M2 V2

ISS

Figure 2.82: Differential MOS pair circuit.

(a) Considering the quadratic I −V characteristic of MOS device in the follow-

ing equation
2 1 w
I = k Vgs −Vth , Vd = V1 −V2 , k = µnCox (2.205)
2 L
prove that
s s !
ISS 2k k
I2 = 1 −Vd 1− Vd 2 (2.206)
2 ISS 2ISS

(b) Now, suppose that the input is a differential signal with Vi = Vm cos (ωt). Find
the expansion of Equation 2.206, and then find the large-signal transconductance.
(Large-signal transconductance is the ratio of the fundamental harmonic current to
the input voltage amplitude.)
(c) Now, suppose that with the circuit of part (a), we have implemented the oscillator
of Figure 2.83.
With the assumption of ideal transformer and with the derived equation for the
large-signal transconductance, find the loop gain and then the oscillation criteria.
Finally, with R = 3 kΩ, k = 1 m VA2 , and ISS = 1 mA, find the coupling coefficient n
for the oscillation amplitude of 600 mV.
96 Chapter 2. Oscillators

VDD
1:2n

Vb
R L C

M1 M2

ISS

Figure 2.83: A differential pair MOS oscillator.

(d) Suppose that this oscillator is designed to oscillate at 1 GHz with the values
of L = 5 nH, and C = 5 pF. To change the oscillator, to the VCO of Figure 2.84,
we need to add the varactors in parallel to the capacitors. The characteristic of the
varactor is shown in Figure 2.85.
VDD
1:2n
Cv
Vcont Vb
R L C
Cv

M1 M2

ISS

Figure 2.84: A VCO based on a differential pair.

CV
2pF

0.5pF
Vvar
-VDD

Figure 2.85: Varactor characteristics.

2.19 Voltage-Controlled Oscillators 97

Find the frequency range of oscillation.

(e) Using the derived equation of part (a) for the amplitude of third harmonic and
considering the frequency response of the resonant circuit, find the ratio of third
harmonic to the fundamental harmonic.
Solution
(a) By writing KCL at the source of the transistor of Figure 2.82, we have
ISS = I1 + I2 (2.207a)

2
I1,2 = k VGS1,2 −VTH (2.207b)

and using KVL, we reach to

−V1 +VGS1 −VGS2 +V2 = 0 (2.208)

Equation 2.208 can be modified as

r r
I1 I2
V1 −V2 = Vd = (VGS1 −VTH )−(VGS2 −VTH ) = VGS1 −VGS2 = − (2.209)
k k
Substituting the value for I2 from Equation 2.207a into Equation 2.209, we obtain
the following equation
2
ISS − kVd2
I22 − I2 ISS + =0 (2.210)
4
The roots of this equation will have the following forms
s s !
ISS 2k k
I2 = 1 −Vd 1− Vd 2 (2.211)
2 ISS 2ISS
s s !
ISS 2k k 2
I1 = 1 +Vd 1− Vd (2.212)
2 ISS 2ISS
q
Note that the above two equations are valid for Vd < 2IkSS .
(b) We can use the approximation of Equation
q 2.213 for a relatively large
1 2ISS
differential signal (however, satisfying Vd < 2 k ) as
s
k k
1− Vd 2 ' 1 − Vd 2 (2.213)
2ISS 4ISS
98 Chapter 2. Oscillators

Therefore, the drain current of M2 for relatively large signals will be

s s !
ISS 2k k3 3
I2 ≈ 1 −Vd + 3 d
V (2.214)
2 ISS 8ISS

For sinusoidal input (i.e., Vd = Vm cos (ωt)), I2 becomes

s
ISS ISS 2k 3k 2
I2 = − Vm 1 − Vm cos (ωt) (2.215)
2 2 ISS 16ISS
s
ISS 2k k
+ Vm 3 cos (3ωt)
32 ISS ISS

Thus, the large-signal transconductance will be

q
ISS 2k 3k 2
2 V
ISS m 1 − V
16ISS m
Gm = −
Vm
s
ISS 2k 3k 2
=− 1− Vm (2.216)
2 ISS 16ISS

As Equation 2.216 suggests, when the oscillation amplitude increases, the large-
signal transconductance decreases which results in stable oscillation.
(c) As we stated earlier, for the oscillation condition, the resonant circuit impedance
will become real at the oscillation frequency. Now, bearing this in mind, we write
the loop gain. The operation of the oscillator is as follows, the differential pair
converts the input voltage to the output current at the opposite drain, and then this
current flows through the resonant circuit and generates the output voltage. Finally,
the transformer returns a part of the output voltage to the input with the same phase
(positive feedback). Therefore, one may write the loop gain (assuming that the
input of the MOS stage does’nt load the output transformer), HL , as

HL = 2nGm R = 1∠0◦ (2.217)

By substituting the 600 mV amplitude in Equation 2.216, we compute Gm =

0.66 mA/V. By substituting the large-signal transconductance in Equation 2.217,
we obtain n = 0.25. For instance, if the number of turns at the drain of the transistor
is 8, then the number of turns at the gate must be about 2.
(d) Half the value of the varactor adds up with the constant capacitor (why?), and
therefore we are able to obtain the frequency range as

1 1
fmax = r = 982.3 MHz (2.218)
2π CV,min
L C+ 2
2.19 Voltage-Controlled Oscillators 99

1 1
fmin = r = 918.8 MHz (2.219)
2π CV,max
L C+ 2

(e) Using Equation 2.215, we can compute the third harmonic from Equation 2.215.
Then, the ratio of the third harmonic to the first one becomes
|H3 | kVm 2 3
= 2
≈ 9.5 × 10−5 or − 80.4 dBc (2.220)
|H1 | 16ISS − 3 kVm 8Q

Example 2.10 Consider the oscillator circuit depicted in Figure 2.86 which is a
VCO.

$PSPRGHO
9RXW

Y 5LQ L2 52 & &Y
5)& 5%
9LQ 9E
/
&Y &’
&

Figure 2.86: A voltage-controlled oscillator with a power series nonlinear

amplifier characteristics.

Moreover, the varactor’s characteristics are depicted in Figure 2.87.

CV

145pF
120pF
105pF
Vvar
-3 -2 -1
Figure 2.87: Varactor characteristics.
100 Chapter 2. Oscillators

The circuit parameters are as follows:

L = 10 nH,C1 = 150 pF,C2 = 1350 pF, RB = 20 kΩ,

Rin = 10 kΩ, Ro = 5 kΩ (2.221)
A A A
QL = 50, LRFC = 10 µ, a = 0.2 , c = −5.8 3 , e = 1 5 (2.222)
V V V
and the nonlinear characteristics are

io = av + cv3 + ev5 (2.223)

Note that
3 cos θ + cos 3θ 10 cos θ + 5 cos 3θ + cos 5θ
cos3 θ = , cos5 θ = (2.224)
4 16
(a) Investigate the effect of finite resistance of RFC if its equivalent parallel resistor
is 2.5 kΩ.
(b) Find the amplitude and the frequency of oscillations for Vb = 1 V.
(c) Find the range of oscillation frequency for 1 < Vb < 3.
(d) Find the amplitude of the fifth harmonic in case (a).

Solution:
(a) The RFC resistance is added in parallel to the output. To calculate its effect, we
should first determine the total output resistance at the operating frequency. The
effective loading resistance of the RFC which would appear at the output of the
oscillator would be
0
RPRFC = n2 RPRFC = 10 kΩ (2.225)

where n = 2 because of the existence of the double varactors. The effect of the
RFC parallel resistance would be to reduce the output resistance and the overall
gain as described in part (b).
(b) The total capacitance at the output (at Vb = 1 V) is computed as

C1C2 CV
CT = + = 207.5 pF (2.226)
C1 +C2 2

By calculating the resonant frequency at Vb = 1 V

1
f= √ = 110.487 MHz (2.227)
2π LCT

The equivalent parallel resistance of the inductor L becomes

RPL = QL Lω0 = 347 Ω (2.228)

2.19 Voltage-Controlled Oscillators 101

The closed loop-gain at the oscillation frequency will be

0
1
GainLoop = Gm1 Ro k RPL k RPRFC =1 (2.229)
m
Then
m mA
Gm 1 = = 31.8 (2.230)
RT V

where
0
RT = Ro k RPL k RPRFC = 314.3 (2.231)

To calculate the large-signal transconductance out of the nonlinear characteristics,

one can write

Vin = V1 cos (ω0t) (2.232)

3 3 5 5
io = aV1 cos (ω0t) + cV1 cos (ω0t) + eV1 cos (ω0t) (2.233)

By expanding Equation 2.232 and considering only the main harmonic component
of the current, we obtain

3c 2 5e 4
io1 = V1 cos (ω0t) a + V1 + V1 (2.234)
4 8

Finally, the large-signal transconductance will be

3c 2 5e 4
Gm 1 = a + V1 + V1 = 0.0318 (2.235)
4 8
Resolving Equation 2.235, one obtains two possible solutions:

V1 = 0.197 V (2.236a)

or

V1 = 2.63 V (2.236b)
∂ Gm
Only one of these solutions is acceptable and that is the one for which ∂V 1 < 0.
1
Actually, the loop gain should decrease with the amplitude at a stable point (why?),
and here only the first solution has such a characteristic.
(c) For the frequency range of the VCO, we can compute the upper bound
and the lower bound frequency of the oscillation from Equation 2.227 for CVmin =
105 pF and CVmax = 145 pF, respectively. Therefore, the frequency range will be
from 116.230 MHz to 110.487 MHz .
102 Chapter 2. Oscillators

(d) To calculate the amplitude of the fifth harmonic, we have

V5 Gm5 ZL (5 ω0 )
= ·
V1 Gm ZL (ω0 )
(2.237)
1

The total output quality factor is

QT = RTCT ω0 = 45.27 (2.238)

The ratio of the fifth harmonic to the first harmonic becomes

V1 4

V5 16 e 1 1
V1 a + 3 cV 2 + 5 eV 4 1 + jQ 5 − 1 ≈ 73110
=


(2.239)
4 1 8 1 T 5

Finally, the amplitude of the fifth harmonic will be

1
V5 = 0.197 × = 2.7 µV (2.240)
73110

2.20 Special Topic: Nonlinear Device Fed by Sinusoidal

Large-Signal Current
Till now in most of the oscillators which we have studied, the nonlinear element
has been considered as a nonlinear transconductance fed by a large-signal sinusoidal
voltage and the loop gain has been computed in terms of the fundamental voltage. In
some cases, one can consider a nonlinear element as a resistance or a transresistance
fed by a large-signal sinusoidal current. In this case, a large-signal resistance or
transresistance can be defined as the ratio of the output fundamental voltage to the
amplitude of the input sinusoidal current. Furthermore, it is possible to compute the
loop gain in terms of the fundamental current instead of the fundamental voltage. The
oscillator depicted in Figure 2.88 illustrates this concept.
If we consider the crystal model as a high-Q series resonant circuit, it is obvious
that it has a low impedance at the resonant frequency and has a high impedance at other
frequencies (harmonic frequencies). As such, one could say that only the fundamental
current passes through the crystal (it is approximately considered as open circuit for
the harmonics). Therefore, the expression for the emitter current would be

iE = IEQ + IE1 cos (ωt) (2.241)

As the transistor’s input nonlinear characteristics are

iE = IES eqvBE /kT (2.242)

Equating Equations 2.241 and 2.242, one obtains a relation between the base–emitter
voltage and the emitter current.
2.20 Special Topic: Nonlinear Device Fed by Sinusoidal Large-Signal 103

kT IEQ kT IE1
vBE = ln + ln 1 + cos (ωt) (2.243)
q IES q IEQ

Or in another form
kT
vBE = VBEQ + ln [1 + y cos (ωt)] (2.244)
q

where
IE1
y= (2.245)
IEQ

The fundamental voltage component at the base–emitter can be expressed as [1]

kT 2 p
VBE1 = 1 − 1 − y2 (2.246)
q y

As such, the large-signal input resistance seen from the emitter can be obtained
p
VBE1 VBE1 IEQ kT 2 1 − 1 − y2
Rin (y) = = = × (2.247)
IE1 IEQ IE1 qIEQ y2

Contrary to the large-signal transconductance which is compressed with the input

voltage amplitude, the large-signal resistance expands with input current amplitude.
For this reason, we draw the inverse normalized large-signal resistance. The inverse
normalized emitter input resistance can be expressed as

rin y2
= (2.248)
Rin (y) 2 1 − 1 − y2
p

Vout
Q
C1
IE1
L RL
RE IEQ C2

-VEE VCC
Figure 2.88: A crystal Colpitts oscillator (Butler oscillator) where the input
current at the emitter is approximately sinusoidal.
104 Chapter 2. Oscillators

where rin is the small signal input resistance seen through the emitter:
kT Vt
rin = = (2.249)
qIEQ IEQ
The variations of the inverse normalized emitter resistance as a function of the normal-
ized input current are depicted in Figure 2.89. Note that 0 < y < 1 in essence.

1
0.95
0.9
0.85
rin/Rin

0.8
0.75
0.7
0.65
0.6
0.55
0.5 y
0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Figure 2.89: Variations of the normalized inverse large-signal input resistance 1

as a function of the input current amplitude.

The application of the above concept is illustrated in Example 2.11.

Example 2.11 Consider the crystal Colpitts oscillator of Figure 2.90.

Vout
Si C1=300pF
α=0.98
L RL=5kΩ

RE=8.4kΩ C2=15nF
10MHz

-VEE VCC

Figure 2.90: Crystal Colpitts oscillator.

In this circuit, if the resonant frequency of the tank circuit and the crystal
resonant frequency are not exactly the same, a slight change in frequency and the
amplitude will occur. Find the amplitude and the frequency of the oscillations for
two cases: (i) determine the value of inductance L for the oscillations at 10 MHz,
(ii) if the resonance frequency of the tank circuit is reduced by an amount of 10 kHz,
for example, due to temperature or process variations, determine the new frequency
2.20 Special Topic: Nonlinear Device Fed by Sinusoidal Large-Signal 105

and amplitude of oscillations. The crystal parameters are fs = 10 MHz, rs = 35 Ω,

and Q0 = 49000 and the supply voltage is VCC = VEE = 5 V. Assume VBEQ = 0.7 V.

Solution:
First, we assume that both resonant frequencies are the same, and therefore we
attain
C1 1
n= = (2.250)
C1 +C2 51

and the equivalent capacitor will be

C1C2
Ceq = = 294 pF (2.251)
C1 +C2

Thus, the overall quality factor at 10 MHz will be

Q = RLCeq ω0 ≈ 92.4 (2.252)

and for the value of inductor, one may write

1
L= = 861 nH (2.253)
Ceq ωs 2

and
VEE −VBEQ
IEQ = = 0.512 mA (2.254)
REE

and
kT
rin = = 50.7 Ω (2.255)
qIEQ

In Figure 2.91, the current loop gain at the resonant frequency can be written as

αIE1 RL n
= IE1 (2.256)
rs + Rin

Note that for n 1, the secondary of the transformer in Figure 2.91 doesn’t load
the primary. The oscillation condition is

αRL n
=1 (2.257)
rs + Rin

Therefore

Rin = nαRL − rs = 61.1 Ω (2.258)

106 Chapter 2. Oscillators

So the normalized inverse large-signal resistance becomes

rin
= 0.829 (2.259)
Rin (y)

Using Figure 2.89, one obtains y = 0.75. Therefore, for the oscillation amplitude,
we attain

Vosc = αIE1 RL = αyIEQ RL = 1.89 V (2.260)

Finally, without considering the phase change, output voltage will be

Vout = VCC + 1.89 cos (ωst) (2.261)

Now, suppose that due to process variation, the resonant frequency of the tank is
10 kHz lower than the series resonance frequency of the crystal, i.e., fo = fcrystal −10
kHz. The tank circuit introduces a phase-change which must be compensated by
the crystal. Since the rate of change of the reactance of the crystal is extremely
high near the resonant frequency, a slight change in the frequency will compensate
the aforementioned phase shift. To calculate the oscillation frequency alongside
the oscillation amplitude, consider Figure 2.91.

rs Ls Cs IE1
1:n

αIE1 L RL C Rin

Figure 2.91: Crystal Colpitts oscillator equivalent circuit seen through the
emitter.

The oscillation criteria mandate that the overall current loop gain to be unity
with zero phase, therefore we obtain (neglecting the loading of the secondary
impedance on the primary of the transformer, given the fact that n 1)

αIE1 RL n 1
× = IE1 (2.262)
ω
1 + jQt ω0 − ω ω0 rs + R in + jX

Or
αRL n 1
× = 1∠0 (2.263)
ω
1 + jQt ωω0 − ω0 rs + Rin + jX
2.20 Special Topic: Nonlinear Device Fed by Sinusoidal Large-Signal 107

where in Equation 2.262, X is the crystal reactance and Rin is the emitter input
resistance. Therefore, from Equation 2.263, we have
ω − ωs ω − ωs
X ≈ 2QL (rs + Rin ) = 2Q0 rs (2.264)
ωs ωs

where QL is the loaded quality factor and Q0 is the unloaded quality factor of the
crystal. The magnitude of Equation 2.263 can be written as

(αRL n)2 1
2 × =1 (2.265)
(rs + Rin )2 + X 2

1 + Qt ωω0 − ωω0

For the phase criteria, one may write

ω ω0 X
tan−1 Qt − = −tan−1 (2.266)
ω0 ω rs + Rin

Equation 2.265 gives us

ω ω0 X
Qt − =− (2.267)
ω0 ω rs + Rin

Substituting Equation 2.267 into Equation 2.265, we then obtain

αRL n
rs + Rin = 2 (2.268)
1 + Qt ωω0 − ωω0

It is possible to replace ω in Equation 2.268 with the series resonant frequency of

the crystal, i.e., ω ≈ ωs (why?). Thus, for input resistance, we have

αRL n
Rin = 2 − rs ≈ 57.9 Ω (2.269)
ωs ω0
1 + Qt ω0 − ωs

and correspondingly, for the reactance X, one may write

ω ω0
X = − (rs + Rin ) Qt − = −17.17 Ω (2.270)
ω0 ω
108 Chapter 2. Oscillators

With respect to Equation 2.264, we obtain

fs
∆f = X ≈ −63 Hz (2.271)
2Q0 rs

and finally, the oscillation frequency will be

fosc = 10 MHz − 63 Hz = 9.999937 MHz (2.272)

Now for computing the new oscillation amplitude, we should consider the new
value for Rin . The inverse normalized large-signal resistance becomes
rin
= 0.875 (2.273)
Rin (y)

Using Figure 2.89, one obtains y = 0.66. The output tuned circuit voltage can be
calculated as
RL
|vt | = αIE1 |ZL | = αyIEQ r 2 = 1.69 V (2.274)
1 + Q2t ω
ω0 − ω0
ω

2.21 Datasheet of a Voltage-Controlled Oscillator

Model name: ZX95-2536C+
• Maximum Ratings

Operating Temperature −55◦ C to 85◦ C

Storage Temperature −55◦ C to 100◦ C
Absolute Max. Supply Voltage (VCC) 5.6 V
Absolute Max. Tuning Voltage (Vtune) 7.0 V
All specifications 50 Ω system

• Electrical Specifications

Min. 2315
Frequency (MHz) Max. 2536
Power output (dBm) Typ. +6
1 −75
Typical phase noise (dBc/Hz) 10 −105
SSB at offset frequencies, kHz 100 −128
1000 −148
Min. 0.5
Tuning voltage range (V) Max. 5
2.21 Datasheet of a Voltage-Controlled Oscillator 109

Sensitivity (MHz/V) Typ. 57–77

Port cap (pF) Typ. 36
Modulation bandwidth, 3 dB (MHz) Typ. 70
Nonharmonic spurious (dBc) Typ. −90
Typ. −18
Harmonics (dBc) Max. −10
VCC (V) 5
DC operating power Max. current (mA) 45

• Performance Data

V tune Tune Sens Frequency Output Power Harmonics

(MHz/V) (MHz) (dBm) (dBc)
−55◦ C +25◦ C +85◦ C +25◦ C F2 F3 F4
0.0 81.90 2267.6 2257.4 2249.2 5.14 −21.7 −19.0 −36.6
0.5 74.61 2306.7 2297.3 2289.5 5.23 −30.5 −20.4 −35.5
1.0 73.76 2344.0 2334.4 2326.4 5.32 −32.0 −22.3 −36.4
1.5 74.01 2381.6 2371.3 2362.6 5.43 −25.6 −22.5 −39.9
2.0 74.15 2419.7 2408.5 2398.9 5.58 −22.2 −23.5 −44.0
2.5 71.91 2456.9 2445.3 2435.4 5.69 −20.0 −23.9 −43.5
3.0 68.45 2492.6 2481.0 2471.1 5.80 −18.5 −25.3 −44.9
3.5 61.36 2525.2 2514.5 2504.9 5.91 −17.3 −27.7 −46.3
4.0 53.56 2554.4 2544.2 2535.4 6.01 −16.3 −30.1 −48.7
4.5 45.62 2579.9 2570.1 2561.7 6.10 −15.6 −33.0 −49.1
5.0 36.26 2601.0 2591.8 2583.8 6.17 −15.2 −35.9 −51.1

• Curves
2XWSXW3RZHUG%P
)UHTXHQF\0+]

+DUPRQLFVG%F

ƒ&
ƒ&
ƒ&


)
)
)


7XQLQJYROWDJH9 7XQLQJYROWDJH9 7XQLQJYROWDJH9

Figure 2.92: Oscillation frequency, output power, and harmonic levels of the
ZX95 VCO as a function of the tuning voltage.
110 Chapter 2. Oscillators

Model name: POS-100+

• Maximum Ratings
Operating Temperature −55◦ C to 85◦ C
Storage Temperature −55◦ C to 100◦ C
Absolute Max. Supply Voltage (VCC) 16 V
Absolute Max. Tuning Voltage (Vtune) 18 V
All specifications 50 Ω system
• Electrical Specifications
Min. 50
Frequency (MHz) Max. 100
Power output (dBm) Typ. +8.3
1 −83
Typical phase noise (dBc/Hz) 10 −107
SSB at offset frequencies, kHz 100 −130
1000 −150
Min. 1
Tuning voltage range (V) Max. 16
Sensitivity (MHz/V) Typ. 4.2-4.8
Modulation bandwidth, 3 dB (MHz) Typ. 0.1
Typ. −23
Harmonics (dBc) Max. −18
VCC (V) 12
DC operating power Max. current (mA) 20
• Performance Data

V tune Tune Sens Frequency Output Power Harmonics

(MHz/V) (MHz) (dBm) (dBc)
−55◦ C +25◦ C +85◦ C +25◦ C F2 F3 F4
1.00 3.80 45.55 44.40 43.93 9.42 −40.40 −38.20 −48.70
2.00 4.20 49.41 48.60 48.31 9.40 −46.40 −40.80 −46.60
3.00 4.50 53.98 53.15 52.83 9.32 −58.40 −40.90 −44.50
4.00 4.10 58.08 57.27 56.90 9.22 −50.30 −39.80 −43.40
5.00 4.00 62.10 61.31 60.88 9.12 −45.60 −38.60 −42.50
6.00 4.10 66.20 65.43 64.96 8.99 −43.40 −37.40 −41.50
7.00 4.20 70.43 69.62 69.13 8.86 −42.60 −36.20 −40.50
8.00 4.30 74.80 73.93 73.43 8.67 −43.10 −35.00 −39.60
9.00 4.40 79.26 78.33 77.81 8.46 −44.70 −34.10 −38.70
10.00 4.40 83.78 82.77 82.25 8.22 −48.50 −33.10 −38.30
11.00 4.50 88.26 87.23 86.68 8.00 −53.80 −32.50 −38.10
12.00 4.50 92.73 91.69 91.10 7.77 −54.90 −31.80 −37.70
13.00 4.40 97.13 96.06 95.46 7.52 −51.10 −31.50 −37.40
14.00 4.40 101.53 100.45 99.81 7.31 −48.00 −30.90 −37.30
15.00 4.40 105.98 104.84 104.18 7.13 −46.20 −30.60 −37.30
16.00 4.40 110.43 109.22 108.55 6.93 −44.60 −30.20 −37.30
2.22 Conclusion 111

• Curves

2XWSXW3RZHUG%P
)UHTXHQF\0+]

+DUPRQLFVG%F

)
)
)
ƒ&
ƒ&
ƒ&

7XQLQJYROWDJH9 7XQLQJYROWDJH9 7XQLQJYROWDJH9

Figure 2.93: Oscillation frequency, output power, and harmonic levels of the
POS-100 VCO as a function of the tuning voltage.

2.22 Conclusion
In this chapter, we have studied the basic operation of sinusoidal oscillators. Oscillators
generally operate by means of amplification of circuit noise in a relatively high-gain
frequency selective closed-loop circuit. Here, the noise as an initial signal contributes
to the build up of the oscillator sinusoidal signal and the loop gain of the oscillator
is consequently compressed (reduced) by the generated large signal. For a stable
oscillation, it is necessary to satisfy Barkhausen’s criteria. That is to say, to achieve a
unity closed-loop gain with 2π or zero phase. In general, an active element in addition
to a frequency selective (resonating) circuit is needed in an oscillator. It is noteworthy
that the oscillators generally operate in large-signal regime. So it is important to have
a nonlinear model for the device in order to compute adequately the amplitude and the
frequency of the oscillation.
In this chapter, different oscillator topologies including CE, CB, CC, (or CS, CG,
and CD for MOS transistors) as well as Colpitts-like or Hartely-like oscillators were
studied. The study of oscillator circuit is essentially divided into two parts: In the
first part, the resonant dividing circuits were studied where RLC resonant circuits are
used with either capacitive or inductive dividers. In the second part, the nonlinear
behavior of the active elements used in the oscillator circuits should be studied. Here
we presented large-signal models for the bipolar transistors, differential bipolar pairs,
MOS transistors, and the MOS differential pairs where large-signal transconductances
were computed for either of the active elements. Using variable capacitors or varactors
in the oscillator circuits permits the frequency tuning of them. As such, voltage-
controlled oscillators (VCO) were presented. VCOs are one of the main building
blocks of the phase-locked loops which will be discussed in the next chapter. The
main figures of merits of an oscillator are its frequency stability, its spectral purity, low
harmonic level, and its low phase noise.

2.23 References and Further Reading

1. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
112 Chapter 2. Oscillators

2. F. Farzaneh, RF Communication Circuits (in Persian), Tehran: Sharif University

Press, 2005.
3. H.L. Krauss, C.W.Bostian, F.H. Raab, Solid State Radio Engineering, New
York, NY: J. Wiley & Sons, Inc., 1980.
4. B. Razavi, Design of Analog CMOS Integrated Circuits, Boston, MA: McGraw-
Hill, 2001.
5. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
6. J.R. Smith, Modern Communication Circuits, second edition, New York, NY:
McGraw Hill, 1997.
7. J. Everard, Fundamentals of RF Circuit Design with Low Noise Oscillators,
United Kingdom: J. Wiley & Sons, Inc., 2000.
8. R. Chi-Hsi Li, RF Circuit Design, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
9. R. Dehghani, Design of CMOS Operational Amplifiers, Norwood, MA: Artech
House, 2013.
10. A. Hajimiri, T.H. Lee, The Design of Low Noise Oscillators, Boston, MA:
Kluwer Academic, 1999.
11. D.H. Wolaver, Phase-Locked Loop Circuit Design, United Kingdom: Prentice
Hall, 1991.
12. M. Tohidian, A. Fotowat-Ahmady, Mahmoud Kamarei, “A simplified method
for phase noise calculation,” IEEE Custom Integrated Circuits Conference
(CICC 2009), San Jose, CA, September 2009.
13. H. Teymoori, A. Fotowat-Ahmady, A. Nabavi, “A new low phase noise LC-tank
CMOS cascode Cross-coupled oscillator,” IEEE Iranian Conference Electrical
Engineering (ICEE 2010), Isfahan University of Technology, Isfahan, May
2010.
14. Mini-circuits, RF designers handbook, VCO datasheets (http://www.mini cir-
cuits.com/).
2.24 Problems 113

2.24 Problems
Problem 2.1 Consider the resonant circuit depicted in Figure 2.94 which is normally
used in Clapp oscillators.
1. We know that the oscillation will occur where the impedance of resonant circuit
is pure real which corresponds to zero phase shift. In the given resonant circuit,
find at which frequency the impedance will be pure real?

L
Zin CP R
CS

Figure 2.94: Clapp-type resonant circuit.

2. With the results of part 1, find the oscillation frequency of Figure 2.95 for
L1 = 50 nH and C0 = C1 = C2 = 3 nF.

VDD

RFC
VGG
L1 C1

C0 I
C2

Figure 2.95: Common-drain Clapp oscillator.

3. In the Colpitts-like oscillator, we can change the oscillation frequency by

varying capacitors C1 or C2 ; however, this will change the loop gain. Explain
what is the advantage of Clapp oscillator with respect to its counterpart.
114 Chapter 2. Oscillators

Problem 2.2 Consider the Colpitts oscillator depicted in Figure 2.96 with the given
values of parasitic capacitances, namely, base–collector Cµ = 15 pF, collector–substrate
CCS = 15 pF, base–emitter Cπ = 30 pF, IC = 3 mA, and CB is RF short.

VCC= 10V
R1 L1 RL
7.8kΩ 20nH 500Ω
Vout
C1
230pF
R2
CB
2.2kΩ I C2
3mA 200pF

Figure 2.96: Bipolar Colpitts oscillator.

1. Find the oscillation frequency and the fundamental harmonic amplitude.

2. Find the second and third harmonics’ amplitudes.
3. If we substitute the current source with the resistor, find the value of the resistor
in such a way that the emitter current is 3 mA. Moreover, recalculate parts 1 and
2. In all parts, assume that the transistor is silicon-type with VBE,Q = 0.7.
Problem 2.3 In the given Colpitts oscillator of Figure 2.97, assume that the MOS
transistor is ideal with Vth = 0.7v and µnCox = 0.134 mA , W = 100. The circuit param-
v2 L
eters are L1 = 2µH,C1 = C2 = 10nF,Cg = 200nF and the transistor is biased in the
square law region. Note that in the MOS transistor, K = 12 µnCox WL . Find the oscillation
frequency and amplitude in this oscillator.

VDD
RL
R1 L1
830Ω
Vout
C1

Cg R2 I=
C2=C1
2mA

Figure 2.97: MOS common-gate Colpitts oscillator.

2.24 Problems 115

Problem 2.4 For the given Colpitts oscillator depicted in Figure 2.98 which is
supposed to oscillate at 100 MHz ? Consider the transistor’s Early voltage is 40 V and
β = 100.

3v
Q=? Cµ
L=? 0.2pF 5mA

Q=100 Cπ
C2=20pF 2pF

Q=100
RE=?
C1=20pF

Figure 2.98: Bipolar common-collector Colpitts oscillator with corresponding

Cµ and Cπ parasitic capacitances.

1. Find the required emitter resistance, RE .

2. Find the proper value of the inductor, L.
3. Determine the oscillation condition, and then find the minimum quality factor
for the inductor to sustain the oscillations.
Problem 2.5 Find the equivalent capacitor in such a way that the circuit depicted
in Figure 2.99 oscillates at 50 MHz. Find the ratio of the capacitors in order to have
an oscillation amplitude of 200 mV and as such determine the values of either of the
capacitors.

5v
VA=40v
L1=300nH
6kΩ 0.1pF β=100
Q=20
Vout
C1=?
1pF Q=100

2nF 4kΩ C2=?

650Ω Q=100

Figure 2.99: Bipolar common-base Colpitts oscillator.

116 Chapter 2. Oscillators

Problem 2.6 Figure 2.100 depicts the block diagram of a hypothetical oscillator.

5HVRQDQW
/LQHDU
$03 FLUFXLW

/LPLWHU

Figure 2.100: A hypothetical oscillator block diagram.

Each block in Figure 2.100 can be modeled by an ideal element (for the amplifier,
you may put a voltage-dependent current source with gm transconductance and finite
output resistance R, and for the resonant circuit, an LC resonator with infinite quality
factor). Suppose that the limiter characteristics follow Vo = tanh (bVin ) where Vin and
Vout are the input and the output voltages of the limiter, respectively. Moreover, assume
we have a gm = 4 mf, R = 500 Ω,C = 5 pF, L = 5 nH, and |b| = 10 V−1 .
1. Draw an equivalent circuit diagram for the oscillator, and determine the oscilla-
tion frequency.
2. Determine the effective gain of the limiter.
3. Determine the sign of the parameter b in the characteristic of the limiter for
positive feedback.
Problem 2.7 Common topologies of the MOS oscillators are shown in Figure 2.101.

VDD VDD VDD

Is L
L
R1 L
VG M
M M C1 C1
C∞
C1 C2 C∞ R2
Is C2 C2 Is

Figure 2.101: Different types of the MOS Colpitts oscillators, common-source,

common-gate, and common-drain.

All transistors have the transconductance and their parasitic capacitances are
Cgs = 231 fF,Cgd = 94 fF,Csb = 24 fF, and Cdb = 19 fF. Moreover, for other parameters,
we have L = 1.5 nH,C1 = 20 pF, and C2 = 5 pF. With the given values, find the
oscillation frequency and compare them in the three topologies.
2.24 Problems 117

Problem 2.8 In the circuit depicted in Figure 2.102, assume that the input large
signal of the stage is Vi = Vm cos (ω0t), and the I − V characteristics of the active
2
device follow I = 12 K Vgs −Vth for Vgs ≥ Vth , and I = 0 for Vgs ≤ Vth . Assume
QL = 50, the output circuit is tuned to ω0 and Vb = Vth . Find the conduction angle in
the output current and then find the first to the fifth output current harmonics and the
first to the fifth output voltage harmonics.

VDD

L C

Q=100
M1

Vb
+
Vi CB

Figure 2.102: MOS tuned amplifier driven by a large signal.

Problem 2.9 The crystal oscillator depicted in Figure 2.103 is named after its de-
signer as Driscoll oscillator. In this oscillator contrary to other types of oscillators, at
the oscillation condition, transistor Q1 will not be driven to the nonlinear regime and
the diodes D1 and D2 will be driven to the nonlinear region and as such will limit the
signal level. Using the exponential I −V characteristics of diodes and using the Bessel
function expansion, find the loop gain, and find the amplitude of the oscillation (an
important feature of the circuit in Figure 2.103 is the separation of the resonant circuit
from the limiter which results in better phase noise of the oscillator). Assume that Vb1
and Vb2 are adequate positive voltages to maintain Q1 and Q2 in their active region.
Furthermore, the phase shifter block has a voltage gain of unity and it doesn’t load the
output tuned circuit.

VCC
180º phase shift at L2 C2 RL D1 D2
oscillation frequency
L1 C∞
Vout
C1 C1
Q2
Vb2
Rb
Q1
C∞
Vb1
Tuner of the crystal RE
capacitance

Figure 2.103: Driscoll oscillator.

118 Chapter 2. Oscillators

Problem 2.10 Assuming a square law characteristics for the MOS transistors as
in Equation 2.275, one can derive the drain current of the MOS differential stage as
Equation 2.276. Using the polynomial expansion of Equation 2.276, find the large-
signal transconductance of the stage and the large-signal loop gain to deduce the
amplitude of oscillation.

1 W 2
ID = µnCox Vgs −Vth (2.275)
2 L

s
ISS µnCox W 4ISS
ID1 = −Vg2 −Vg2 2 (2.276)
2 4 L µnCox WL

VDD
C1
R L
C2

RFC
M2 M1
+
Vg2 - ISS
-VSS

Figure 2.104: MOS differential oscillator.

Problem 2.11 Consider the Colpitts oscillator depicted in Figure 2.105 and assume
that Vcontrol = 6 V, bipolar transistor’s β = 100, L = 2 µH,C1 = 55 pF, and C2 = 550 pF.
Moreover, Figure 2.106 depicts the variable capacitance characteristics. Assume that
the MOS transistor is off.

VCC=3V
RL C2 CV1 Rb
Vs M1 L Vcontrol
C1 CV2
R1 C∞
Vout
356fF

1pF
C∞ R2
IE=2.5mA RE=500Ω

Figure 2.105: A BiCMOS VCO.

2.24 Problems 119

CV1,2

3.25pF
2pF
0.85pF

-7 -3 -1 Vvar

Figure 2.106: Variable capacitance characteristics.

1. Find the oscillation frequency.

2. If the control voltage varies between 4 V and 10 V, find the range of the oscilla-
tion frequency.
3. Find the load resistance RL to have an oscillation amplitude of 500 mV at the
collector.
4. If the transistor M1 is actuated by a feedback network depicted in Figure 2.107,
and goes into the triode region, find the ratio of the third harmonic to the first
2
harmonic in this case. Note that if Isd = 12 K Vgs −Vth , then in the triode region,
we would have gds = K Vgs −Vth . Assume K = 500 VµA2 and Vth = −1 V.

9&& Y

5/

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(QYHORSH
GHWHFWLRQ
P9'&

Figure 2.107: Feedback amplitude control loop.

Problem 2.12 In a nonlinear amplifier depicted in Figure 2.108, the input–output

relation follows Vout = 5Vin −0.65Vin 2 −0.3Vin 3 . This amplifier is placed in a feedback
loop and the combination results in a stable oscillation.

1. Find the oscillation frequency.

2. Find the −3 dB bandwidth of the resonant circuit.
3. Find the small-signal and the large-signal loop gain.
4. Find the oscillation amplitude alongside the second harmonic amplitude in dBc.
120 Chapter 2. Oscillators

442pF

1μH
442pF

Vin

Rin= Rout=
250Ω +
Vo 1000Ω

Figure 2.108: An oscillator with a nonlinear amplifier in feedback.

Problem 2.13 In an oscillator depicted in Figure 2.109 where the nonlinear transfer
characteristics of the device are given by Equation 2.278, find the oscillation frequency
as well as the amplitude of the fundamental and the second harmonic.

L&
UR *P9EH S)
ȍ

Q+
9EH UH
UH§*P ȍ 9RXW

S)
9ELDV ,ELDV

9ELDV

Figure 2.109: Colpitts oscillator.

v1 = vbe (2.277)

1 v1 v1 2 v1 3
iC = + + − A (2.278)
100 50 300 400
Problem 2.14 Design problem. In the reference Driscoll oscillator depicted in
Figure 2.110,
1. How the values of C1 , C2 , L4 , and L5 are determined, in such a way that the
circuit oscillates at the third series resonance of the crystal ( fS ). Describe the
corresponding relations (write the oscillation condition).
2.24 Problems 121

2. The oscillation amplitude at the emitter of Q1 is much smaller than the thermal
voltage VT , and at the collector of Q2 , it is larger than a few VT ’s, and the third
overtone of the crystal is the dominant impedance. The amplitude of oscillations
at the collector of Q2 is determined by the Schottky diodes impedances. The
VD
I −V characteristic of diodes follows ID = IS e Vt . Find the harmonic content of
the current by the Bessel function expansion of the output characteristics and
determine an expression for the loading impedance of the diodes.

VCC
Vo 50Ω

L4
1 C∞
Rb3 20
L5
C2
Q2
C∞
Rb2 C∞
C∞ R R C∞
Q1
-VC +VC
RFC
Rb1 C1
REb

Figure 2.110: Reference Driscoll oscillator.

Problem 2.15 For the oscillator depicted in Figure 2.111, using the large-signal
model of the transistor, draw the equivalent circuit and write the complex relation
describing Barkhausen’s oscillation criteria. Assume that the crystal’s admittance is
represented by a complex value Yx . Note: do not use the equivalent transformer model
for the capacitive divider in this case.

VCC

R1
Si
α=0.99
C1
Yx R2

RE
C2

Figure 2.111: Common-collector crystal oscillator.

122 Chapter 2. Oscillators

Problem 2.16 Writing the oscillation condition, find the frequency and the amplitude
of oscillations in the circuit of Figure 2.112 at the collector of the transistor Q1 .
Furthermore, find the third harmonic amplitude at the same node.

5V M12

4kΩ 20pF 5µH 5kΩ 40pF

L1 L2
Vout

Si
Q1 Q2
α=0.99

IE= 1mA L1=2.5µH

L2=6.25nH
M12=125nH
-5V

Figure 2.112: Differential pair tuned circuit oscillator.

Problem 2.17 The amplifier model in Figure 2.113 is representative of an operational

amplifier where Ri is quite large and µ is adequately large and ro is quite small. Find
the complex oscillation condition in Figure 2.113 as a function of the circuit parameters.
Assume that the crystal impedance is represented by R + jX. Furthermore, explain
how does the signal amplitude is limited in this topology.

R+jX

+VCC

+ ro
Ri µVi
Vi +
C1 C2

-VCC

Figure 2.113: Pierce-like oscillator using an ideal amplifier.

Problem 2.18 In the Pierce crystal oscillator depicted in Figure 2.114, the crystal
is inductive and will resonate with the input and the output capacitors resulting in a
sinusoidal oscillation. Assume the nonlinear element has the given I −V characteristics.
First find the large-signal effective Gm as a function of AC voltage amplitude and draw
it to the scale. Then, write the complex oscillation condition in Figure 2.114 as a
function of the circuit parameters. What is the required Gm for an oscillation amplitude
of 1 V?
2.24 Problems 123

5M;

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5 & &L L I9 & 5
9



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Į P$9
99 ܵ
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Figure 2.114: Pierce crystal oscillator with a nonlinear transconductance.

II
Part 2
3 PLL, FM Modulation, and FM Demodulation . 127
3.1 Frequency Modulation
3.2 Frequency Demodulation
3.3 Basics of PLLs and their Application as an
FM Demodulator
3.4 Further PLL Applications
3.5 Advanced Topic: PLL Type II
3.6 Conclusion
3.7 References and Further Reading
3.8 Problems

4 Mixers . . . . . . . . . . . . . . . . . . . . . . . . 169
4.1 Mixer Concept
4.2 Third Order Intermodulation Concept in a Nonlinear
Amplifier
4.3 Basic Concept of Third-Order IM in a Basic Mixer
4.4 Bipolar Transistor Active Mixer
4.5 Mixer types Based on Switching Circuits
4.6 Matching in Mixers
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer
4.8 Linearization Methods in Mixers
4.9 Calculating Third-Order Input Intercept Point in
Cascaded Stages
4.10 Important Point in RF Circuit Simulation
4.11 Conclusion
4.12 References and Further Reading
4.13 Problems

5 Modulation/Demodulation of Amplitude/Phase
223
5.1 AM Modulation
5.2 AM Demodulation
5.3 Generating AM Signals
5.4 Double-Sideband and Single-Sideband Suppressed
Carrier Generation
5.5 Synchronous AM Detection
5.6 Gilbert Cell Applications
5.7 Modern Practical Modulations
5.8 Effect of Phase and Amplitude Mismatch on the Signal
Constellation
5.9 Conclusion
5.10 References and Further Reading
5.11 Problems

6 Limiters and Automatic Gain Control . . . . . 257

6.1 Limiting Versus Automatic Gain Control
6.2 Total Bandwidth with Multistage
6.3 Offset Compensation Circuits
6.4 Automatic Gain Control
6.5 Amplitude Detectors
6.6 Amplifier Circuit with Gain Control Based on Analog
Multipliers
6.7 Increasing Bandwidth Methods
6.8 Oscillation in Limiting Stages
6.9 Conclusion
6.10 References and Further Reading
3. PLL, FM Modulation, and FM Demodulation

As discussed in Chapter 2, voltage-controlled oscillators are widely used in many

applications such as phase-locked loops (PLLs), frequency modulation (FM), and
demodulation. Baseband signal transmission cannot be realized without modulation.
For instance, voice signals need a carrier to be transmitted through the transmission
medium. Moreover, each standard specifies a carrier frequency and a bandwidth for
the specified service.

3.1 Frequency Modulation

It is possible to change the frequency of an oscillator by varying its tuned circuit
varactor voltage. As an example, in a Colpitts-like oscillator circuit, as depicted in
Figure 3.1, the total capacitance of the tuned circuit is varied by the varactor control
voltage.
As it is obvious from Figure 3.1, we can easily change the oscillation frequency
by the control voltage of the varactor which changes the resonant frequency of the
circuit. Tuning voltage passes through a low-pass circuit and by a specific time constant
changes the output frequency. Voice signal adds through a high-pass filter (C1 and R2 )
to its common-mode level and as a result, the baseband signal modulates the oscillator
frequency. Modulation index is based on the amplitude of the baseband signal which
also modulates the oscillator nonlinearly. The modulation index is determined by the
derivative of Cv (v) and the amplitude of the voice signal, as shown in Figure 3.1. It is
possible to obtain the instantaneous frequency of the oscillator in Figure 3.1 as
1
f= r (3.1)
2π L CC11+C C2
2
+C V

The instantaneous value of the varactor capacitance can be described as

∂Cv
Cv (VB +Vm g (t)) = Cv (VB ) + Vm g (t) = Cv (VB ) +C (t) (3.2)
∂v
128 Chapter 3. PLL, FM Modulation, and FM Demodulation

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Q) S) &9W
&
S)
0LFURSKRQH 5 5 9'
S) ,6
9 9
&
9'W
9'
FRQWUROYROWDJH

Figure 3.1: A typical voltage-controlled oscillator (VCO) with voice input for
frequency modulation.

where Vm is the maximum value of the baseband voltage, VB is the varactor’s bias
voltage, and g (t) is a random normalized function (varying between +1 and −1)
proportional to the input information. The function g (t) may be a continuously valued
analog signal for FM or a two discrete level valued digital signal for FSK modulation.
The instantaneous frequency can be computed as
!
1 C(t)
1− 2 C1C2 +C (V )
1 C +C
1 2
v B
f= r ≈ r = f0 + ∆ f (t)
C1C2 C1C2
2π L C1 +C2 +Cv (VB ) +C (t) 2π L C1 +C2 +Cv (VB )
(3.3)

Here, the carrier frequency is

1
f0 = r (3.4)
2π L CC11+C
C2
2
+Cv (VB )

and the frequency deviation becomes

!
C(t)
− 12 C1 C2
C1 +C2 +Cv (VB )
∆ f (t) = r (3.5)
2π L CC11+C
C2
2
+Cv (VB )

Here the carrier frequency and the frequency deviation are clearly described as a
function of circuit parameter values. Now with the definition of frequency modulation,
3.1 Frequency Modulation 129

we can write the FM signal as

 Θ

z Z }| {
 
vFM (t) = A sin 
 ω 0 t + ∆ωm (t)dt 
 (3.6)

We can obtain the instantaneous frequency of Equation 3.6 by the derivation of the
argument of the sinusoidal signal:

dΘ
ω (t) = (3.7)
dt
where in Equation 3.7, Θ is called the total phase. Moreover, we know that

ω (t) = 2π f = ω0 + ∆ωm (t) (3.8)

where in Equation 3.8 ω0 is the carrier radian frequency and ∆ωm (t) is a function of
the baseband or the radian frequency deviation. Comparing Equations 3.7 and 3.8, we
reach to
Z Z
Θ= (ω0 + ∆ωm (t))dt = ω0t + ∆ωm (t)dt (3.9)

Thus far, we have calculated the signal phase for Equation 3.6 and also introduced
the frequency modulation. As Equation 3.6 suggests, we have defined the frequency-
modulated signal by a constant amplitude sinusoid. The information is embedded in
∆ωm (t) which changes the VCO frequency proportionally. It should be noted that
the bigger the amplitude of the input baseband signal the more will be the frequency
deviation. Thus, in many applications, we employ a limiter in the baseband circuit
to limit the bandwidth occupancy. Therefore, the information is merely in a specific
bandwidth. As an example, we can inspect the specifications of the commercial FM
radio. The standard obligates the bandwidth of this radio to be limited to 200 kHz. The
Carson bandwidth equation predicts that

BW FM ∼
= 2 ( fdev + fBB ) (3.10)

where in Equation 3.10, fdev is the frequency deviation and fBB is the maximum
baseband signal frequency. As an example, for a frequency deviation of 75 kHz, and a
maximum baseband frequency of 20 kHz, the Carson bandwidth becomes

BW FM ∼
= 2 (75 + 20) = 190 kHz (3.11)

which is within the specified bandwidth of 200 kHz. As another example, the time
variation of an FM signal is illustrated in Figure 3.2. Here for the sake of illustration,
the carrier frequency is chosen as 500 kHz and the frequency deviation is chosen as
75 kHz.
As depicted in Figure 3.2, when the amplitude of the baseband signal is high, the
frequency increases and when this amplitude is low, the frequency decreases.
130 Chapter 3. PLL, FM Modulation, and FM Demodulation

%DVHEDQG
VLJQDO
N+]

N+] N+]

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PRGXODWHG
VLJQDO

Figure 3.2: Typical baseband and the corresponding FM signal variations with
time.

3.2 Frequency Demodulation

We can easily detect frequency-modulated signals by employing a time derivative and
then amplitude detection:

Z t
dvFM
= A (ω0 + ∆ωm (t)) cos ω0t + ∆ωm (t) dt (3.12)
dt 0

The above signal can be detected using an envelope detector. As such, it is possible
to detect an FM signal through a differentiator followed by an AM detector. We now
continue with the other concepts for frequency demodulation.

3.2.1 Phase Detector

One of the methods to detect FM signals is through the use of a phase detector circuit.
Thus, if we find a circuit which gives the phase difference between two inputs, we can
demodulate the FM signal. This procedure can be done by an XOR (Exclusive-OR).
Consider Figure 3.3.
If two signals in Figure 3.3 completely overlap, the output will be zero. If the
two signals have a slight phase shift, the output will be nonzero (proportional to
the DC component of the output pulse train). Furthermore, the maximum value of
the phase detector output occurs when the signals have 180◦ phase difference. The
main drawback in Figure 3.3 is the logic level which is not appropriate for phase
detection (the DC component of the output is proportional to the absolute value of the
phase difference). Thus, we introduce another circuit for this purpose which is the
Gilbert cell.
3.2 Frequency Demodulation 131

1
V4
V1 0
1 1
V2 0
∆ɸ -π π ∆ɸ
1
2π V1 V3
V3 0 LPF V4
V2
Figure 3.3: XOR (phase detection) characteristics driven by two signals with a
common frequency and a fixed phase shift.

3.2.2 Gilbert Cell as a Phase Detector

Figure 3.4 shows the Gilbert cell circuit. We can assert that the Gilbert cell is composed
of three differential pairs. The lower differential transistors are called the lower tree
and the upper pairs are called the upper tree. The Gilbert cell is capable of being a
phase detector. The advantage of this circuit is that it doesn’t need a certain logic level
to function as a phase detector. In bipolar transistors, the required voltage for correct
behavior of phase detector is at least 4Vt where Vt is the thermal voltage. In the lower
tree of the Gilbert cell shown in Figure 3.4(a), one can write

I0 qv
1
IC1,C2 = 1 ± tanh (3.13)
2 2 kT

VCC VDD
RL - vout + RL RL - vout + RL
IC3,5 IC4,6 ID3,5 ID4,6
CL CL

Q3 Q4 Q5 Q6 M3 M4 M5 M6
v2 v2

IC1 IC2 ID1 ID2

Q1 Q2 M1 M2
v1 v1

I0 I0

(a) (b)

Figure 3.4: Gilbert cell (analog multiplier), (a) by bipolar transistor pairs and
(b) by MOS transistor pairs, used as a phase detector.
132 Chapter 3. PLL, FM Modulation, and FM Demodulation

The differential current in the upper tree becomes

qv qv
1 2 v1 v2
∆I = IC3,5 −IC4,6 = I0 tanh tanh = I0 tanh tanh (3.14)
2 kT 2 kT 2Vt 2Vt
Given the large load capacitance, CL , the output voltage will be proportional to the
low-pass component of RL ∆I. Note that the Gilbert cell produces a differential current
proportional to the analog multiplication of the input voltages. The point here is that
the hyperbolic tangent function saturates to ±1 once its argument (or the input voltage)
is large, either positive or negative. As such, the output current will exhibit a bipolar
XOR (Exclusive-OR) function of the two large inputs (an Exclusive-OR with ±1 logic
levels). This way the low-pass component of the output will be proportional to the
phase difference of the inputs, provided that the inputs are large signal, that is larger
than 4Vt (Figure 3.5).
In an analytical manner, one can describe the all-pass components of the output (if
the capacitance, CL did not exist) as

V1 cos (ω0t) V2 cos (ω0t + φ )
Vout = I0 RL tanh tanh (3.15)
2Vt 2Vt

For large signal inputs, that is, VV1t 1 and VV2t 1, the hyperbolic tangent of sinusoidal
signals turn into square-wave signals of the same frequency and phase. That is
Vout = I0 RL S (ω0t) S (ω0t + φ ) (3.16)

1
∆ɸ =0 0
-1

Vout,LP 1
∆ɸ =π/4 0
RLI0 -1

1
-π π ∆ɸ =π/2
∆ɸ 0
-1

1
-RLI0 ∆ɸ =3π/4 0
-1

1
∆ɸ =π 0
-1

(a) (b)
Figure 3.5: Gilbert cell function as a phase detector. (a) The phase detector
output characteristics. (b) Signal waveforms for phase detector operation.
3.2 Frequency Demodulation 133

where S (ω0t) is a bipolar square wave of a unity amplitude. The Fourier expansion of
the square waves gives

4 1 1
Vout = I0 RL cos (ω0t) − cos (3ω0t) + cos (5ω0t) − · · ·
π 3 5

4 1 1
× cos (ω0t + φ ) − cos (3ω0t + 3φ ) + cos (5ω0t + 5φ ) − · · · (3.17)
π 3 5

The low-pass component of the output becomes

8 1 1
Vout,LP = 2 I0 RL cos (φ ) + cos (3φ ) + cos (5φ ) + · · · (3.18)
π 9 25

With a coefficient of I0 RL , this is evidently a Fourier expansion of a triangular func-

tion of φ whose value is unity at 0 radians and its value is 0 at ±π/2 radians (see
Figure 3.5(a) and compare it with Figure 3.3).
With MOS transistors (with a typical 700 mV threshold voltage), this can be
roughly done by about 200 mV–300 mV bias above the threshold voltage. The capacitor
in Figure 3.4(b) realizes a low-pass response to suppress undesired higher frequency
components.
Considering a square law characteristics for the MOS transistors

ID = K(vGS −VTH )2 for vGS > VTH (3.19)

Here we assume that vGS1 = VGS01 + v1 /2 and vGS2 = VGS01 − v1 /2. The ratio of
the currents in the lower tree transistors, with the above assumption, becomes (with
v1
2 < VGS01 −VTH to remain in the square law region)
2 2
I1 VGS01 + v21 −VTH Veff + v21
= 2 = 2 (3.20)
I2 VGS01 − v21 −VTH Veff − v21

where Veff = VGS01 −VTH , and

I1 + I2 = I0 (3.21)

and the current in the either drains of the lower tree transistors can be described as
   
v1 v1
I0  VGS01 −VTH  I0  Veff
I1 = 1 + 2  = 1 + (3.22)

2 
2 2

1 v1 1 v1
1+ 4 VGS01 −VTH 1+ 4 Veff

   
v1 v1
I0  VGS01 −VTH  I0  Veff
I2 = 1 − 2  = 1 − (3.23)

2 
2 2

v1 v1
1 + 41 VGS01 −VTH 1 + 41 Veff
134 Chapter 3. PLL, FM Modulation, and FM Demodulation

These equations are valid for v1 ≤ 2 (VGS01 −VTH ).

In a similar manner, the differential current of the upper tree can be described
as a function of two differential voltages, v1 and v2 (provided v21 < VGS01 −VTH and
v2
2 < VGS02 −VTH )
 
v1 v2
 VGS01 −VTH VGS02 −VTH 
∆I = ID3,5 − ID4,6 = I0 
 2  (3.24)
2 
1 + 14 VGS0 v1−VTH 1 + 14 VGS0 v2−VTH
1 2

where, VGS01 is the DC bias voltage of the lower tree transistors and VGS02 is the
DC bias voltage of the upper tree transistors. Here again, the output voltage will be
proportional to the low-pass component of RL ∆I. Note that the MOS Gilbert cell
produces a differential current proportional to the analog multiplication of the input
voltages approximately. This function is again a saturating function of the input
voltages and tends approximately to ±1 once its argument (input voltage) is large. As
such, again the output current will exhibit a bipolar XOR (Exclusive-OR) function of
the two large inputs (an Exclusive-OR with ±1 logic levels). This way the low-pass
component of the output will be proportional to the phase difference of the inputs,
provided that the inputs are large signal, that is, larger than 2Veff . The same analytical
procedure as described in Equations 3.16 through 3.18 holds for MOS phase detector as
well and consequently, a triangular output characteristics is produced here again. The
phase detector characteristics, that is, the output voltage versus the phase difference of
the two input signals, are shown in Figure 3.5(b).
In general, the Gilbert cell will be a phase detector when both inputs are driven to
the large signal regime. If the lower tree is driven by a small signal and the upper tree
experiences hard switching, the circuit changes to a mixer operation (which we will
study in Chapter 4). However, if both trees are driven by small-signal inputs, we will
have an analog multiplier. Now we desire to design a phase detector with a Gilbert
cell. We know that the data lie in the phase or the frequency of the carrier.

3.2.3 Quadrature Phase (FM) Detector

Figure 3.6 shows a receiver with quadrature FM detection. The main objective in this
circuit is to detect a frequency-modulated signal through a phase shift of 90◦ degrees
of the signal.
In Figure 3.6, the 104 MHz input signal is first amplified and then downconverted
to the IF frequency of 10.7 MHz. Then the IF signal again is amplified and using an
external filter is fed to a limiter. The limiter keeps the phase information and removes
any variations on the amplitude of the signal. Finally, the limited signal goes through
a quadrature detector for frequency demodulation. The point is that the capacitive
impedance of the series capacitor CS is much larger than the impedance of the resonator
at its center frequency. As such, we would observe a phase shift of approximately
90◦ between V2 and V1 at the center frequency. Note that, for this purpose, we should
have RPCS ω1 1. For instance, consider a signal with the limited amplitude of 1V
at 10.7 MHz with a frequency deviation of ±75 KHz which has experienced a phase
shift of 90◦ (V2 is in quadrature with V1 ) and the two signals are fed to the phase
3.2 Frequency Demodulation 135

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0+] 0+]
*LOEHUW
0+] /3) FHOO
9RLFH 9
VLJQDO
&6
9
)UHTXHQF\
GHPRGXODWRU /3 &3 53

Figure 3.6: Signal receiver for FM.

detector. Here, a Gilbert cell can be used as the phase detector. Assuming a high input
impedance for both inputs of the phase detector, we can easily show that
V2 CS LP s2
= (3.25)
V1 s2 S
ω12
+ Qω 1
+1

where
1
ω1 = p (3.26a)
LP (CP +CS )
Q = RP (CP +CS ) ω1 (3.26b)
Here Q is the detector’s quality factor and ω1 is the center frequency of the detector.
In the frequency domain, one can write

V2 jQ CSC+C
S ω
jQ CSC+C
S

= P ω1 ≈ P
(3.27)
V1 1 + jQ ωω1 ω ω2
− 1 1 + j2Q ∆ω
ω
2 1
1

where ∆ω = ω − ω1 , and it is considered that ω ≈ ω1 in Equation 3.27. Figure 3.7

shows the frequency response of the a quadrature detector.
As such, the phase difference between the voltages in the quadrature phase detector
becomes

π −1 ∆ω
∆φ = ∠V2 − ∠V1 = − tan 2Q (3.28)
2 ω1
Assume the input FM signal has the following form
Z t
V1 = A cos ω1t + ∆ω f (τ)dτ (3.29)
0
136 Chapter 3. PLL, FM Modulation, and FM Demodulation

V2
V1

QCS/(CP+CS) High Q

Low Q

f
f1
V2
V1

180º
90º f1
0º f

Figure 3.7: Frequency response of the phase detector.

Then, the instantaneous frequency of this signal would be

ω = ω1 + ∆ω f (t) (3.30)

where f (t) is the normalized baseband signal, that is, −1 ≤ f (t) ≤ +1. The approxi-
mate formula for Equation 3.28 can be written as
 
ω1
− (ω1 +∆ω f (t))Q  π 2Q
∆φ = tan−1  2  ≈ − (∆ω) f (t) (3.31)

2 ω1

ω1
1 − ω +∆ω f (t)
1

As it is seen in Equation 3.31, the phase difference between the two voltages V1 and
V2 is proportional to the instantaneous frequency deviation ∆ω f (t) (while the two
voltages are at quadrature at the resonant frequency). Or in other words, as Figure 3.7
suggests, the phase difference between two inputs of phase detector at f1 is 90◦ . Due
to the frequency deviation of the frequency-modulated signal, the output voltage varies
with frequency deviation and consequently with the slope of the phase characteristics
of the quadrature tank. Figure 3.8 depicts the phase characteristics of the quadrature
tank for different quality factors.
As it is obvious from Figure 3.8, for a higher quality factor, we will attain a higher
sensitivity for a specific frequency deviation and the characteristic of Figure 3.8 will
be sharper. We can approximate the phase variations in Figure 3.8 near the center
frequency linearly as depicted in Figure 3.9.
3.2 Frequency Demodulation 137

V2
V1
High Q
180º
Low Q
90º f1

0º f

Figure 3.8: Phase characteristics of the quadrature tank by different quality

factors.

9
9 +LJK4
/RZ4
ž

I
I
)UHTXHQF\
GHYLDWLRQ

Figure 3.9: A linear approximation for phase characteristic of the quadrature

tank.

This linear approximation is valid for a small frequency range. In our example, the
IF frequency is 10.7 MHz which is normally used in FM receivers. Moreover, as stated
earlier, the frequency deviation is ±75 KHz. The mentioned frequency deviation is
the maximum value; however, its instantaneous value depends on the input baseband
signal. We can write the phase difference in Figure 3.9 with Equation 3.31 as
π 2Q
∆φ = − (∆ω) f (t) (3.32)
2 ω1
where in Equation 3.32, ∆ω is the frequency deviation, f (t) is the voice signal, Q is
the quality factor, and ω1 is the center frequency. The quality factor is the following
Q = (CS +CP ) ω1 RP (3.33)
In this circuit, the frequency deviation is translated to ∆φ and the phase detector
translates the phase difference to a voltage proportional to the baseband. Now, let’s
analyze quantitatively the output from the multiplication occurring in the phase detector.
Consider the FM input applied to port1 of the phase detector as
Z t
V1 = A cos ω1t + ∆ω f (τ)dτ (3.34)
0
138 Chapter 3. PLL, FM Modulation, and FM Demodulation

One may obtain V2 at ω1 as

Z t
CS π 2Q
V2 = QA cos ω1t + ∆ω f (τ)dτ + − (∆ω) f (t) (3.35)
CS +CP 0 2 ω1

It should be noted that higher quality factor results in more nonlinearity and distortion
in the detection process. For a moment if we assume the phase detector as a multiplier
and with the inputs of Equations 3.34 and 3.35, then the output would have a form like

QA2 CS

π 2Q
V1V2 = cos − (∆ω) f (t)
2 CS +CP 2 ω1
Z t
π 2Q
− cos 2ω1t + 2∆ω f (τ)dτ + − (∆ω) f (t) (3.36)
0 2 ω1

But considering the amplitude A is large enough to make a hard switching for the upper
tree of the Gilbert cell, and the amplitude of V2 that is QA CSC+C
S
P
is still large enough to
make a hard switching of the lower tree, then the output of the phase detector would
be proportional to RL I0 . As such, the low-pass component of the output of the phase
detector will have the following form

2Q 2Q
vout LPF = RL I0 sin (∆ω) f (t) ≈ RL I0 (∆ω) f (t) (3.37)
ω1 ω1

The linear approximation is valid for 2Q∆ω/ω1 < π/4. As Equation 3.36 suggests,
higher quality factor of the resonant circuit results in larger amplitude of V2 . However,
linear approximation of the frequency response will be violated for large values of
the quality factor and distortion in the baseband data will emerge at the output due
to response nonlinearity. To mitigate this issue, one may decrease the quality factor.
There is another frequency demodulation scheme which is discussed in the PLL section.

Example 3.1 In the given FM detector circuit

(a) Find the transfer function of the frequency demodulator. The carrier signal
frequency is 455 kHz and the Sallen–Key filter has two poles at 455 kHz. Moreover,
the Gilbert cell is a multiplier circuit which experiences complete switching for its
transistors.
(b) Suppose the modulation frequency of 1 kHz and the frequency deviation of
8 kHz, find the amplitude of the second and the third harmonics of 1 kHz at the
output. R1 = R2 = 1 kΩ, C1 = C2 = 350 pF and you may use the given Taylor’s
expansion.

−1 π 1 1 2 1 3
tan (1 + x) ≈ + x− x + x for x < 1 (3.38)
4 2 4 12
3.2 Frequency Demodulation 139

Limiter
10kHz
V1
455±8kHz Vout
2nd order
V2

C1
R1 R2

C2

Figure 3.10: Frequency demodulator by quadrature phase detector using a

Sallen–key filter.

Solution:
(a) Given R1 = R2 = R, and C1 = C2 = C, the transfer function of the Sallen–Key
filter can be written as
v2 1
= (3.39)
v1 (1 + jRCω)2

Then

v2 ω f
∠ = −2tan−1 (RCω) = −2tan−1 = −2tan −1
(3.40)
v1 ω0 f0

We also know that f = f0 + ∆ f , therefore Equation 3.39 shrinks to

v2 ∆f
∠ = −2tan−1 1 + (3.41)
v1 f0

Note that

V2 1 ∆f
≈ for 1 (3.42)
V1 2 f0

If we expand Equation 3.41, we then reach to

v2 π ∆f π ∆f
∠ = −2 + −··· = − − (3.43)
v1 4 2 f0 2 f0
140 Chapter 3. PLL, FM Modulation, and FM Demodulation

Now two signals with large amplitudes and the above phase shift are applied
to a phase detector with a gain of KPD , thus the output voltage of this block for a
sinusoidal modulation will be

π ∆f
vOUT = −KPD + cos (ωmt) (3.44)
2 f0

For the AC output component proportional to the frequency deviation, we have

∆f 8
vout = −KPD cos (ωmt) = −KPD cos (ωmt) (3.45)
f0 455

(b) The 1 kHz component is the main baseband transmitted signal, i.e., ωm =
2π(1000) Hz. If we expand Equation 3.38 for the higher order terms (nonlinear
terms) as well for vOUT , then we reach to

1 ∆f 2 2

π ∆f
vOUT = −KPD + cos (ωmt) − cos (ωmt)
2 f0 2 f0
!
1 ∆f 3 3

+ cos (ωmt) (3.46)
6 f0

The all-pass filter translates this frequency deviation to a specific phase shift,
and consequently to the corresponding voltage at the output of the phase detector.
Moreover, we know that the nonlinear characteristic of phase transfer function
results in harmonic generation of the baseband signal. As such, the output voltage
will be

" ! !
π 1 ∆f 2 1 ∆f 2 ∆f
vOUT = −kPD − + 1+ (3.47)
2 4 f0 8 f0 f0
#
1 ∆f 2 1 ∆f 3

cos (ωmt) − cos (2ωmt) + cos (3ωmt) + · · ·
4 f0 24 f0

Therefore, the amplitudes of the second and the third harmonics are
2
KPD 8
H2 = (3.48a)
4 455
3
KPD 8
H3 = (3.48b)
24 455

3.3 Basics of PLLs and their Application 141

Example 3.2 Consider the FM detector depicted in Figure 3.6. The FM signal
carrier is at 455 kHz with 2 V amplitude. If the frequency deviation is 8 kHz, and
with the assumption of an ideal multiplier with a load resistance of RL = 1 kΩ and
the total bias current of I0 = 1 mA, and assuming CP = 1 nF, CS = 10 pF, and Q = 5,
obtain the detected output signal amplitude.
Solution:
With the given parameters, we can write
Z t
V1 = 2 sin ω0t + ∆ω f (τ)dτ Volts (3.49)
0

For V2 , we have
Z t
CS π 2Q
V2 = Q × 2 sin ω0t + ∆ω f (τ)dτ + − (∆ω) f (t) Volts
CS +CP 0 2 ω0
(3.50)

Z t
π 2Q
V2 = 0.099 sin ω0t + ∆ω f (τ)dτ + − (∆ω) f (t) Volts (3.51)
0 2 ω0

Considering that the Gilbert cell multiplier is driven to its saturation level by both
input signals, the low-pass component of the output becomes

2Q
vout LPF = RL I0 sin (∆ω) f (t) (3.52)
ω1

Now noting that the sinusoidal argument is less than 1 rad, we then reach to

2Q
vout LPF ≈ RL I0 (∆ω) f (t) = 0.176 f (t) Volts (3.53)
ω0

where by substituting the parameters, the output voltage amplitude is 176 mV.

3.3 Basics of PLLs and their Application as an FM Demodulator

In this section, we introduce the PLL as a frequency demodulator. First of all, let’s
survey some important characteristics of PLLs. Consider Figure 3.11.
The input in Figure 3.11 consists of an FM sinusoidal signal whose frequency
alternates in a time interval ∆T . For the sake of simplicity, assume that the VCO is
operating at its free-running frequency, say, 10.7 MHz. The VCO signal is multiplied
by the input frequency-modulated signal by an analog multiplier. If we assume an ideal
multiplication, we will reach to the second harmonic (21.4 MHz ± 70 kHz) and the
low-pass component whose frequency of variations is proportional to 1/∆T . This low-
pass component appears at the output of the low-pass filter. The feedback loop tends to
142

10.7MHz 10.7MHz
+70kHz -70kHz
VIN VOUT
LPF

t VCO t
∆T ∆T ∆T ∆T

Figure 3.11: Frequency demodulation with PLL.

Chapter 3. PLL, FM Modulation, and FM Demodulation
3.3 Basics of PLLs and their Application 143

change the VCO frequency toward the instantaneous frequency of 10.7 MHz ± 70 kHz.
In other words, the VCO in this loop tries to follow the input frequency. This behavior
is called phase locking and we call this loop as PLL. While the input frequency varies
in the PLL, the loop tries to generate an error voltage to correct the VCO frequency.
This error voltage is proportional to the baseband modulating signal and by this virtue,
the PLL output will be the FM detected signal. Note that if the variations are fast (that
is, faster than the loop bandwidth), the loop would not be capable of following the
input frequency and the loop will not operate properly. Indeed, the PLL is a low-pass
system.

Example 3.3 A student asks whether the PLL is the same as frequency-locked
loop (FLL), i.e., at the steady state, the frequencies will be the same as the phases
are the same. Is he/she right?
Answer:
Yes, in a sense that once the loop is locked the reference and the VCO output
frequencies would be the same but with a constant phase shift existing between
them. But if the loop is not locked the VCO will act as a free-running oscillator.

Now, consider Figure 3.12.

Assume in Figure 3.12, the multiplier is a Gilbert cell phase detector, then we may
obtain the phase detector gain as

VOPD
KPD = (3.54)
φin − φout

where in Equation 3.36, KPD is the phase detector gain. We may obtain the transfer
function of the low-pass filter (for a single-pole low-pass filter) easily as

Vout 1
= s (3.55)
VinLPF 1 + ωLPF

We can also write the output signal of the oscillator as

Z
Vosc = A sin Θ (t) = A sin ωfrt + KVCO Vout (t)dt (3.56)

ɸin ɸerror VOUT

LPF
ɸout

VCO

Figure 3.12: PLL schematic diagram.

144 Chapter 3. PLL, FM Modulation, and FM Demodulation

The oscillator in its static mode oscillates at the free-running frequency, ωfr . Here
KVCO is the VCO gain in rad/s per Volts or equivalently Hz V . Depending on the VCO
gain and the input signal, the output frequency changes. We can write the expression
for the instantaneous frequency of the oscillator as

ωosc = ωfr + KVCOVout (t) (3.57)

We can reach to time-dependent frequency by taking the derivative of the total phase
which results in
d
Θ (t) = ωfr + KVCOVout (t) = ωosc (t) (3.58)
dt
Taking the Laplace transform of both sides of Equation 3.58 gives

sφout (s) = KVCOVout (s) = ωosc (s) (3.59)

Finally, the output phase in s-domain

KVCOVout (s)
φout (s) = (3.60)
s
As Equation 3.60 suggests, VCO acts as an integrator in the PLL.

3.3.1 The Transfer Function of the First-Order PLL

Figure 3.12 can be modeled as Figure 3.13.
The phase detector output is the result of multiplication of two square-wave signals
which the low-pass filter extracts its average value. As depicted in Figure 3.13, the
feedback is of unity gain. Note, signals in this loop are both considered as voltage and
phase. However, our transfer function of interest is the output phase as a function of
the input phase. One may obtain the open loop gain as

!
1 KVCO
a (s) = s KPD (3.61)
1 + ωLPF s

Then, the closed-loop gain (as a negative feedback loop) which is the transfer function
of interest can be written as
φo a (s)
= (3.62)
φi 1 + f a (s)

ɸin ɸerror VPD 1 Vin-VCO KVCO ɸout

+ KPD 1+ s
ωLPF s
ɸout

Figure 3.13: PLL model.

3.3 Basics of PLLs and their Application 145

Substituting Equation 3.61 into Equation 3.62 and setting the feedback gain f = 1 give

1 KPD KVCO
φo 1+ ω s s
LPF
= (3.63)
φi 1 KPD KVCO
1+ 1+ ω s s
LPF

We can write Equation 3.63 as

φo 1
= (3.64)
s2
φi
ωLPF KVCO KPD + KVCOs KPD + 1

Equation 3.64 suggests that the transfer function gain at low frequencies is unity
which means that the loop follows the input phase at the output for low-frequency
variation. However, for a high-frequency input, the gain of the loop will be decreased.
Thus, the transfer function has a low-pass behavior. We can rewrite the transfer
function as
φo 1
= 2 (3.65)
φi s
ωn + Qωs n + 1

where parameters in Equation 3.65 can be derived as

p
ωn = ωLPF KVCO KPD (3.66a)
r
KVCO KPD
Q= (3.66b)
ωLPF

The parameter Q in Equation 3.65 has an important effect. If Q is equal to 1/2, the
poles of the loop coincide, if it is greater than 1/2, we will have complex conjugate
poles, and if Q is lower than 1/2, the loop consists of real poles. It is instructive to
know that at ωn , the loop exhibits an overshoot which is illustrated in Figure 3.14.

ORJ݊RXW݊LQ

G% 4G%

G%GHF

ȦQ ORJȦ

Figure 3.14: Overshoot in the frequency response of the PLL near the natural
frequency.
146 Chapter 3. PLL, FM Modulation, and FM Demodulation

Example 3.4 To implement the phase detector, we use the given Gilbert cell.
(a) Find the load resistance and the load capacitance to have a phase-detector gain
of π1 Radian
Volts
.
(b) With the phase detector characteristics depicted in Fig. 3.16, we implement a
PLL as in Figure 3.17. Suppose Rf = 100 Ω, find the value of Cf and the transfer
function of the loop.
(c) If the input frequency suddenly changes from 100 MHz to 100.1 MHz, draw the
control voltage as a function of time.
Assume KVCO = 500 kHz/V, and Q = 1/ (2ζ ) = 0.5.

VDD
Vout
RL CL RL

M3 M4 M5 M6
V2

M1 M2
V1

I0=0.5mA

Figure 3.15: The Gilbert cell used as the phase detector.

Vout
+0.5V

∆ɸ
0 π/2 π
-0.5V

Figure 3.16: The desired transfer function of the phase detector.

%XIIHU
DPSOLILHU
݊LQ 5I .9&2 ݊RXW
*
V
&I

Figure 3.17: Simple PLL (Type I).

3.3 Basics of PLLs and their Application 147

Solution:
(a) When a current completely flows to one side, we have RL I0 = 0.5 V, which
gives the load resistance of 1 kΩ, and consequently (Figure 3.16) the gain of the
phase detector will be 1/π.
As the output of the phase detector should be low pass

1
100 MHz (3.67)
2πRLCL

Let
1
= 5 MHz (3.68)
4πRLCL

Then, CL = 16 pF.
(b) We have the expression for Q as
s
r 1
KPD KVCO (2π × 0.5 MHz)
Q= ⇒ 0.5 = π (3.69)
ωLPF ωLPF

rad
ωLPF = 2π × 6.25 × 105 (3.70)
sec
For the value of the capacitor, we have

Q2
Cf = = 400 pF (3.71)
2πKPD KVCO Rf

The transfer function of the PLL can be expressed as

φo 1
= 2 (3.72)
φi s
ωn + Qωs n + 1

The natural frequency of the loop can be calculated as

√ q
ωn = KPD KVCO ωLPF = π1 × 2π × 0.5 MHz × 2π × 6.25 × 105 sec
rad

rad
= 2M sec (3.73)

and thus the output phase relation will be

2
φo 2 × 106
= 2 (3.74)
φi s + 2 × 106 rad
sec
148 Chapter 3. PLL, FM Modulation, and FM Demodulation

As Equation 3.74 suggests, the system is critically damped here, and therefore,
it will have the fastest response without overshoot.

(c) The relation between the output frequency and the input frequency can be
written as
fo (s) sφo (s)
= (3.75)
fi (s) sφi (s)

Thus, the output frequency varies with double pole as 1/(s + 2 Mrad/sec)2 , and we
will reach to Figure 3.18.

IR
0+]

0+]
IJ 0UDGV
QV
WIJ

Figure 3.18: Time response of the PLL Frequency.

Moreover, one may write the output phase as

KVCO
φo = vin,control ⇒ sφo = KVCO vin,control (3.76)
s
and for the frequency, we have

f (s) = KVCO vin,control (s) ⇒ f1 (t) = KVCO vin,control1 (t) (3.77)

Finally, Figure 3.19 depicts how the control voltage varies with time and
reaches to its final value.
9FRQWURO
P9

WIJ

Figure 3.19: The control voltage of the PLL as a function of time.

3.3 Basics of PLLs and their Application 149

Example 3.5 In the FM detector circuit depicted in Figure 3.20, the output of
the limiter has an amplitude of 200 mV. With a maximum frequency variation rate
(modulation rate) of 5 MHz, the frequency deviation is 7 MHz. The IF carrier
frequency is at 140 MHz.

ȍ
$
9R
$PS /LPLWHU P9SS

9R
%

ȍ = ȍ

5 Ȝ ȍ
ȍ 5 5 ȍ

Figure 3.20: Quadrature FM demodulator.

(a) Determine the input signal amplitude at the point B.

(b) Secondly, given the multiplier circuit, find the amplitude of the detected signal.
(c) If the transmission line had a phase shift of 70◦ instead of 90◦ at 140 MHz, what
would be the DC value across the 7.6 pF capacitor (at the output of circuit depicted
in Fig. 3.21).

5V
RL CL RL
1.5kΩ 7.6pF 1.5kΩ

Q3 Q4 Q5 Q6
400mVp-p
A
RFC 50Ω
Q1 Q2
Vb C∞ C∞
50Ω 1mA

C∞
B

Figure 3.21: Gilbert cell phase detector.

Solution:
(a) In this part, the input signal is attenuated through a π-section resistive attenuator.
As the attenuator is matched at the input and the output, the output voltage will
become
150 Chapter 3. PLL, FM Modulation, and FM Demodulation

R1 k Z0
VB = VA = 0.706VA = 141 mV (3.78)
R2 + R1 k Z0

(b) Here, given the instantaneous FM signal frequency, the quarter-wave transmis-
sion line acts as a 90◦ phase shifter in the following manner.
The instantaneous frequency is

ωi = ω0 + ∆ω f (t) (3.79)

The instantaneous phase shift would be

π ∆ω
∆φ = 1+ f (t) (3.80)
2 ω0

where f (t) is the baseband modulating signal, with unity amplitude. Now, given
the low-pass output circuit of the multiplier and the fact that VA and VB are quite
larger than Vt , the Gilbert Cell acts as an ideal phase detector (recall section 3.2.2),
so its output would be proportional to the phase difference of the in-phase and the
quadrature signals. Considering the cut-off frequency of the output RC circuit as

1
fcut-off = ≈ 7 MHz (3.81)
4πRLCL

Therefore, given the fact that the modulating signal is band limited to 5 MHz, the
output would have the following form

π ∆ω
Vout = I0 RL f (t) = 117 f (t) mV (3.82)
2 ω0

(c) The phase detector works such that it gives a zero DC output for a π/2 phase
shift between the two input signals. Therefore, if the transmission line has a 70◦
phase shift at the center frequency, the DC output would become
!
7π
∆φ 18 2
VDC,out = I0 RL 1 − π = I0 RL 1 − π = I0 RL ≈ 333 mV (3.83)
2 2 9

Some applications mandate high-speed PLLs; however, others may use slow loops. It is
possible to control the loop speed by proper choice of ωn . Moreover, one may change
the bandwidth of the low-pass filter to control the loop bandwidth. Equation 3.66
suggests that lowering the low-pass filter bandwidth results in increase in Q which may
be undesirable and also may make the loop unstable with any additional parasitic pole.
It can be stated that the flat gain is mostly obtained up to ωn frequency. If one increases
the bandwidth of the low-pass filter in order to achieve a fast loop, the bandwidth
will not be extended because of the fact that the poles move farther from each other.
3.3 Basics of PLLs and their Application 151

ωVCO

KVCO
ωfree-running

Vin-DC
Vin, free-running

Figure 3.22: VCO characteristics.

Thus, it seems that we should increase the gain of the phase detector or the VCO gain
to maintain the quality factor constant. This loop is called Type-I loop, because its
open-loop gain has a pole at the origin (note that the order of the transfer function of
the PLL is always equal to the order of the transfer function of low-pass filter plus
one). Now, consider a tone with 10 MHz frequency is applied at the input of a Type-I
PLL. Moreover, the initial phase difference between the input and the output is 90◦ . If
this input is applied to a Gilbert cell, the output voltage will be zero. If the oscillator is
at its free-running frequency, the loop will be stable. Note that, if the input frequency
changes to 11 MHz, an input voltage must be applied to the VCO to shift its frequency
to 11 MHz. Thus, the phase difference between the input and the output will diverge
from 90◦ , it may be, say, 85◦ . Thus, a PLL is not inherently capable of locking to any
frequency. This phenomenon occurs due to the limited locking and capturing range in
PLLs that is due to transfer function of the phase detector. The consequence of this
phenomenon is that a PLL may not be locked.
Figure 3.22 shows the transfer function of the VCO. It is imperative that the
designer must take into account the voltage range of the phase detector output and the
VCO transfer function to allow the loop to lock.

Example 3.6 Given the initial conditions of the PLL transfer function, how is
that the input and the output frequencies will be equal in steady state?
2π
φo s fo fo 1
= 2π
= = 2 (3.84)
φi s fi
fi s
ωn + Qωs n + 1

Solution:
Bearing in mind that the initial condition must be considered in Laplace transform,
since we describe here the equation about the free-running frequency of the VCO
(Vin−VCO = 0), the phase initial condition is not important here. This point is shown
in the time domain as follows
ϕo (t) − ϕi (t) = cte. (3.85)

Taking the derivative of both sides of Equation 3.85, we then reach to

d d
ϕo (t) − ϕi (t) = 0 ⇒ fo (t) = fi (t) (3.86)
dt dt
Thus, the frequencies will be equal.
152 Chapter 3. PLL, FM Modulation, and FM Demodulation

3.4 Further PLL Applications

In Figure 3.23, different inputs are applied to the PLL and the output is shown.
As depicted in Figure 3.23, the input signal bears different conditions. First,
noise is added to the input signal, then the signal continues as usual, then the signal
disappears (goes to zero), and finally a large signal, with a same frequency, is applied
to the input. As the transfer function of the PLL has a low-pass characteristic, it
passes the low-frequency component of the noisy signal; however, the overall noise
is averaged out and the loop continues its normal behavior. Then, once the input
signal has vanished, one of the phase detector inputs goes to zero. As the phase
detector output will be equal to the product of the inputs, and if one of the inputs is
zero, the output of the phase detector will be zero, the oscillator should tend to its
free-running frequency by zero control voltage. However, the loop will maintain its
current frequency if it has a sufficiently slow response (the time duration of the signal
cut-off is much shorter than the loop time constant). Nonetheless, for high-speed loops,
it may result in frequency change and movement to the free-running frequency of the
oscillator. For the large-signal input (Figure 3.23), as the phase detector is principally
insensitive to the input amplitude its output will remain unchanged, and consequently
the PLL output will be unchanged.

1RLV\VLJQDO
1RVLJQDO
,QSXW
VLJQDO
1RUPDO 1RUPDO
VLJQDO VLJQDO
/DUJHVLJQDO

2XWSXW
VLJQDO

Figure 3.23: PLL response for different input signals.

Example 3.7 Does the transfer function relating the output phase to the input
phase of the PLL infer unconditional stability, because of the fact that the output
phase reaches to −180◦ at positive infinite frequency?
Solution:
This is the simplified transfer function of the system with two poles; however, due
to nonidealities, the order of the system might be increased. Furthermore, the phase
margin is defined for an open loop, and we write it for the open loop to predict the
closed-loop behavior. Moreover, since the transient response of the loop is of great
importance, we need to take care of the phase margin.
3.4 Further PLL Applications 153

Example 3.8 Consider the given type I PLL in Figure 3.24 with the Gilbert cell
as the phase detector and with the following parameters.

VCOFree-running frequency = 100 MHz, KVCO = 200 MHz/V (3.87)

ωLPF = 2π × 1 MHz, KPD = 2 V/rad (3.88)

VCO
݊in VPD R Vcont KVCO ݊out
KPD
s
C

Figure 3.24: Type I PLL.

(a) Find the closed-loop transfer function.

(b) Find the loop phase margin.
(c) If the loop locks at 100 MHz, what is the phase difference between φi and φo ?
(d) If the loop locks at 110 MHz, what is the phase difference between φi and φo ?
Solution:
(a) For the transfer function of the PLL, we can write
1 K
ϕout KPD RCs+1 VCO
s KPD KVCO
H (s) = = 1 KVCO
= 2 +s+K K
(3.89)
ϕin 1 + KPD RCs+1 s RCs PD VCO

(b) To calculate the phase margin, we should find the point where the open-loop
gain reaches unity. Then at that point, we compute the phase. Therefore

1 KVCO
|HOL ( jω)| = 1 ⇒ KPD =1 (3.90)
RC jω + 1 jω

Then, the unity gain frequency will be

KPD KVCO
√
ω 1 + R2C2 ω 2 = 1 (3.91)

p
2 −1 + 1 + 4R2C2 KPD 2 KVCO 2
⇒ω = = 1.58 × 1016 (3.92)
2R2C2
rad
ω = 125.69 × 106 ⇒ f = 20 MHz
sec

Finally, the phase at this frequency will be ϕ = − π2 − tan−1 (RCω) = −177.1◦ and
the resulting phase margin is 180 − 177.1 = 2.9◦ .
154 Chapter 3. PLL, FM Modulation, and FM Demodulation

(c) Since the given frequency is equal to the free-running frequency of the oscillator,
the phase difference will be 90◦ and the control voltage will be zero.

ϕi − ϕo = 90◦ (3.93)

(d) For this case, we have

∆f 10 MHz
∆V × KVCO = ∆ f ⇒ ∆V = = = 50 mV (3.94)
KVCO 200 MHz
V

and the phase difference with respect to the previous case will be

VPD 50 × 10−3
∆ϕ = = = 0.025 rad = 1.43◦ (3.95)
KPD 2

ϕi − ϕo = 90 + ∆ϕ (3.96)

Thus, the obtained phase difference will be added to 90◦ (ϕ = 91.43◦ ).

Example 3.9 In the previous example, using the ADS simulation tool, compute
the following. The reference signal at first has a frequency of f1 and then it
experiences a frequency step and goes to a frequency of f2 ,
(a) Draw the control voltage (Vcont ), VPD , Vin , Vout , and fout .
(b) Suppose f1 = 100 MHz, f2 = 110 MHz, and KVCO = 200 MHz/V. Find the final
value of Vcont with respect to its initial value.

V(t)

f1 f2

Figure 3.25: Time variations depicting a frequency step.

(c) If the input signal with the frequency of f1 , where f1 is not the free-running
frequency of the oscillator, vanishes, describe qualitatively what happens in the
PLL.
3.4 Further PLL Applications 155

V(t)

f1 f2 f1

Figure 3.26: The signal vanishes in short step.

Solution:
(a) Figure 3.27 depicts the wanted signals.
(b) We can write

∆f 10 MHz
∆V × KVCO = ∆ f ⇒ ∆V = = = 50 mV (3.97)
KVCO 200 MHz
V

ILQ 0+] ILQ 0+]

9LQ
W

IRXW 0+] 0+]IRXW0+] IRXW 0+]

9RXW
W

93'
W

9FRQW P9

W

0+]
IRXW
0+]
W

Figure 3.27: Desired signals.

156 Chapter 3. PLL, FM Modulation, and FM Demodulation

(c) The frequency response of the loop is dependent of its natural frequency, i.e.,
ωn . If this value is large with respect to the input, then the loop will be fast enough
to sense the disappearing of the signal and pushes the VCO to its free-running
frequency. However, if the mentioned disconnection time is small with respect to
the loop time constant, the loop may stand at its current frequency and phase and
the VCO will continue its oscillation properly.

3.4.1 FM with PLL

Consider the oscillator in Figure 3.28. In Figure 3.28, the MOS transistors M3 and M4
are used as varactors where their drain sources are short circuited. Figure 3.29 depicts
the characteristics of the varactors (here C1 has a large capacitance which is considered
as a short circuit at oscillation frequency). As Figure 3.28 suggests, the varactors are
in parallel with the inductors and make the resonant circuit. The transistors M1 and
M2 realize the positive feedback, or otherwise, make a negative resistance across the

9''
/ /

0 0
0 0
& &

,'&
5
9'&
&

Figure 3.28: Cross-coupled oscillator.

CV(v)

VDC

Figure 3.29: Characteristics of the nonlinear MOSFET varactor.

3.4 Further PLL Applications 157

resonant circuit terminals. The frequency of the oscillation then can be obtained as
s
1 1
f= (3.98)
2π L (CN +CV (v))

where in Equation 3.98, CN is the total capacitance at the output node and Cv (v) is the
nonlinear bias dependent varactor capacitance. The nonlinearity of varactor results
in changing the VCO gain which in fact changes the closed-loop gain and the phase
margin.
In the previous sections, we discussed the frequency demodulation with PLL. Now,
we focus on FM with a PLL. Figure 3.30 illustrates both frequency modulation and
demodulation with PLL.
Figure 3.30 shows the system-level structure of a frequency modulator. We have
seen that by varying the varactor voltage, we are able to make a frequency modulator.
The varactor was the MOS device which was biased in the reverse region. As an
example, consider a 100 mV single-tone input signal in the control voltage of the VCO
with the frequency of 10 Hz as

VMOD = 0.1 sin (2π × 10 Hz) (3.99)

Moreover, suppose that the VCO is locked to 10.7 MHz. Depending on the bandwidth
or speed of the loop, different outputs can be achieved. If the loop is faster than the
input signal of the oscillator, it doesn’t let the VCO to change its frequency (maintains
the frequency of the loop as stable). On the other hand, for slow loops, the FM will

Demodulator Modulator

VIN VOUT
RS
+

LPF
VMOD
CS
Vout
VCO
VCO

Figure 3.30: Frequency modulation and demodulation with PLL.

fVCO

10.7MHz

Vin-DC
1.4 1.5 1.6

Figure 3.31: VCO characteristics for a 10.7 MHz carrier.

158 Chapter 3. PLL, FM Modulation, and FM Demodulation

be materialized. The PLL here plays a main role to hold the intermediate frequency
(the carrier frequency) as constant. From the quantitative analysis point of view, we
remember that loop’s f−3dB is selected near ωn to have complex poles with proper
settling time. Now assume that the natural frequency of the loop is 500 Hz. Thus, the
loop is fast enough not to let the frequency change. Now, if the input signal to the VCO
changes its frequency to 5 kHz, the VCO changes its frequency with a rate of 5 kHz.
The frequency deviation in the oscillator is merely dependent on the variations of its
control voltage. It is clear that the larger-signal input to the VCO will result in more
frequency deviation from the center frequency of the oscillator. Figure 3.31 depicts the
characteristics of the oscillator for this example.
In an ordinary PLL, the output follows the input to find the same frequency.
However, in FM with PLL, the loop resists against the carrier frequency variation. In
fact, the loop has an output with the average frequency of 10.7 MHz and will find
a frequency deviation corresponding to the input signal. It can be stated that in the
frequency modulator, the loop should be designed as a slow loop, and in the frequency
demodulator, the loop should be designed as a fast loop. Thus, the lower limit in
frequency modulator is ωn and the upper limit is specified by the low-pass filter for the
modulating signal.

Example 3.10 Is is possible to feed the baseband signal to the VCO for the sake
of FM generation without a PLL?
Answer:
Although an FM modulator with a simple VCO is conceivable, practically it is
not possible, because of the requirement for the carrier frequency stability. The
frequency stability of the PLL is then necessary for correct operation of the FM
generation which is guaranteed by means of the negative feedback in the PLL loop.
Moreover, PLL shapes the phase noise of the oscillator which is of great importance
as well.

3.4.2 PLL Application in Frequency Synthesizers and Its Transfer function

Consider Figure 3.32.

RS
+

VMOD
Vout
÷N VCO

÷M

Figure 3.32: Frequency synthesizer block diagram for a frequency modulation

scheme.
3.4 Further PLL Applications 159

Figure 3.32 is the usual frequency synthesizer which is used to generate a frequency-
modulated signal. The divider shown in Figure 3.32 is a digital counter which after M
input pulses, generates one pulse. Note in any counter, the value of M can be selected
digitally. In the steady-state condition, both the inputs of the phase detector will have
the same frequency and as a result, we will have

fCrystal fVCO
= (3.100)
N M
Suppose the crystal frequency is equal to 10.7 MHz, then for the VCO frequency, one
may obtain

M M
fVCO = fCrystal = 10.7 MHz (3.101)
N N
Moreover, assume that for the input divider, we have N = 107. Thus, the comparison
frequency will be equal to 100 kHz. Now, assume that M = 9000. As a result, the output
signal will be at 900 MHz and the channel spacing could be 100 kHz. The channel
selection can be achieved by changing M, and thus 10.7NMHz will be the minimum
channel step. Assuming an input sinusoidal signal with 100 mV for the modulation
signal, for the frequency of the VCO, we will have

M
fVCO = fCrystal + 100 mV × KVCO sin (ωBBt) (3.102)
N
M is changed by the digital circuitry, and therefore one may hop from one channel to
another. With respect to different standards, we can change the comparison frequency
to change the channel spacing. In the high-frequency applications (e.g., higher than
5 GHz), we should break the divider into several stages and design a special counter
for the first stage which operates at high frequency.
Till now, we have learned how to demodulate a frequency-modulated signal by
a quadrature resonator or a PLL. Suppose the input signal frequency to the PLL is
10.7 MHz ± 70 kHz (in other words, the frequency deviation is 70 kHz), therefore the
VCO follows the input frequency variations and the output of the phase detector through
the low-pass filter gives in the detected FM baseband. However, in the quadrature FM
detector, if the transmitted signal carrier frequency is changed, the detector could not
detect thoroughly the input FM because the phase shift in quadrature component will
be no longer about 90◦ and the detector would not perform correctly.
We have also shown that, using a PLL, we are able to generate a frequency-
modulated signal which is shown in Figure 3.33. As stated earlier, the bandwidth of
the FM signal at the PLL output in Figure 3.33 is

BW = 2 ( fdev + fm ) (3.103)

where fdev is the maximum frequency deviation and fm is the maximum frequency of
the baseband signal. However, the bandwidth of the PLLs is far less than the above
bandwidth. The frequency deviation is proportional to the amplitude of the modulating
signal. As discussed earlier, the correct operation of the frequency modulator has two
160 Chapter 3. PLL, FM Modulation, and FM Demodulation

56

902'
5
$FWLYH
FLUFXLW
& / & 5

/3) 9&2

Figure 3.33: System- and circuit-level implementation of frequency modulation

using a PLL.

margins which are specified by the natural frequency of the loop and the maximum
frequency component of the modulating signal. In fact, the time constant of the loop
characterizes the upper margin of the PLL. For increasing the time constant, making
the loop slow, we can increase the capacitance in the loop filter.
Now, we derive equations for the dynamic behavior of the synthesizer in Figure 3.32.
We stated that in the steady-state condition, both inputs of the phase detector will have
the same frequency. It can be asserted that the phase detector is somehow a frequency
detector as well and we can employ frequency modulator system as a phase modulator
block too. Now, if we write the relation between the output phase and the input phase
in Figure 3.32, we reach to
−1
φo fo
s
1 + ωLPF KPD KVCO
s
= = −1 (3.104)
fi

φi
1 + 1 + ωLPF s
KPD KVCO 1
s M

Thus, Equation 3.104 gives the transfer function of the frequency synthesizer. One of
the important parameters in this loop is the transition time to shift from one channel
frequency to another channel frequency which can be calculated through the inverse
Laplace transform of Equation 3.104 which yields the settling time as
4
TS = (3.105)
ζ ωn
Note that the settling time is defined as the lapse of time required for the output
frequency to reach 98% of its final value. Here ζ is the damping factor and it is
expressed by
1
ζ= (3.106)
2Q
Now, suppose the oscillator in Figure 3.32 has a frequency equal to 900 MHz and the
channel spacing is 30 kHz. We can obtain channel spacing as follows
fCrystal
Channel Spacing = (3.107)
N
3.5 Advanced Topic: PLL Type II 161

Here, N determines the channel spacing. Thus, we now have implemented a frequency
synthesizer which is used for frequency generation for both the receiver and the
transmitter. Moreover, by putting a baseband signal in the control voltage of the latter,
we will have a frequency modulator. As an example, for a crystal oscillator of 15 MHz
frequency, one may obtain the value of N as

15000
N= = 500 (3.108)
30
To change the channel frequency, we are able to change the value of M. Another usual
method for frequency synthesis is the direct digital synthesis (DDS) which is very
precise with the precision of hundredth of hertz (at IF frequency). The DDS-based
design is out of the scope of this text.
Nowadays, the FM is not used in high-speed and high-performance transceivers.
It is mainly used in commercial broadcast systems which depend on great number
of conventional FM receivers. However, digital modulations such as M − QAM and
QPSK are common in data communication which we discuss in the following chapters.

3.5 Advanced Topic: PLL Type II

The problems that the type I PLLs introduce have driven the designers to find a second
type of PLL structure which does not have those imperfections. The very first problem
of the type I PLL is its tradeoff between the stability and the output distortion. To
mitigate the spur level at the output of the VCO, we can bring the pole of the LPF
near the origin; however, this scheme will decrease the phase margin and as a result,
there will be a greater possibility of instability. Another drawback of the type I PLL is
its limited locking range due to the phase detector characteristics. These drawbacks
were the incentive for the designers to propose a structure named phase-frequency-
detector (PFD) which is also able to detect the difference of the input frequencies and
consequently increase the locking range. We now introduce the basic behaviors of the
PFD and the charge pump which are crucial in type II PLL. Using two D flip-flops and
an AND gate, the system-level implementation of the PFD is shown in Figure 3.34.
As Figure 3.34 suggests, applying two signals with the same frequency and slight
phase difference results in periodic output which is proportional to the phase difference
of the inputs. This behavior is the same as that of the phase detector. The operation of
the PFD is as follows: while signal A goes high, the output QA goes high till the input
B goes high as well and both outputs QA and QB are applied to the AND gate and
the output of it goes high. Then, the output of the flip-flops will be reset. Now, suppose
the inputs have different frequencies then PFD will generate a signal proportional to the
frequency difference which finally makes the oscillator to lock to the input frequency.
In type II PLL, the charge-pump circuit alleviates the tradeoff between the stability
and the spur level by introducing a new parameter. Figure 3.35 shows the charge-pump
circuit.
The output signals of the PFD drive the up and the down inputs of the charge pump
and as a result, the current sources may charge or discharge the capacitance charge
level. Figure 3.36 depicts the operation of the charge pump alongside the PFD.
162 Chapter 3. PLL, FM Modulation, and FM Demodulation

VDD
D
Q QA A
A CLK
B
Reset AND
QA
B CLK
Q QB QB
D
VDD

Figure 3.34: System-level implementation of PFD using two D flip-flops and

an AND gate.

Charge pump
VDD
I1

Up S1 Vo
Down S2
C
I2

Figure 3.35: A typical charge-pump circuit using two current sources and two
switches.

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Figure 3.36: Operation of the charge-pump circuit under the excitation of the
PFD.
3.5 Advanced Topic: PLL Type II 163

Figure 3.36 suggests that when the switch is on, the capacitor is charged linearly
and the circuit can be assumed as an integrator and when the switch is off the capacitor
holds its value. The output voltage increment in Figure 3.36 can be approximated as

∆ϕ I
∆Vcont = T (3.109)
2π C
Equation 3.109 can be rewritten for the control voltage of the oscillator as

∆ϕ I
Vcont (t) = tu (t) (3.110)
2π C
By taking the Laplace transform of Equation 3.110, we reach to

Vcont (s) I 1
= (3.111)
∆ϕ 2πC s
Equation 3.111 shows the integration behavior of the circuit explicitly. Finally, by
placing the charge-pump circuit subsequent to the PFD, and applying a unity feedback,
the type II PLL can be achieved as in Figure 3.37.
The reason that we call this architecture type-II is that it has two poles at the
origin in the open-loop transfer function (one for the charge pump and another for
the VCO). The two poles at the origin make the instability of great concern. Thus,
for the stability issues, we place a series resistor with the capacitor and rewrite the
charge-pump equation as (this brings a zero in the open-loop as well as the closed-loop
transfer function)

Vcont I 1
(s) = +R (3.112)
∆ϕ 2π Cs

VDD
I1

ɸi S1 Vcont
PFD VCO ɸo
S2
C
I2 R

Figure 3.37: Type-II PLL block diagram including a PFD, a charge pump, and
a VCO.
164 Chapter 3. PLL, FM Modulation, and FM Demodulation

Thus, we can write the overall transfer function for type-II PLL as

IKVCO ω 2 1 + 2ξ s
ϕo 2πC (RCs + 1) n ωn
H (s) = = 2 I I
= 2 (3.113)
ϕi s + 2π KVCO Rs + 2πC KVCO s + 2ξ ωn s + ωn2

where the parameters of the loop are

r
R ICKVCO
ξ= (3.114a)
2 2π
r
IKVCO
ωn = (3.114b)
2πC
1
Q= (3.114c)
2ξ

Furthermore, the poles and the zero for the transfer function, H(s), are
p
sp1,2 = −ξ ± ξ 2 − 1 ωn (3.115a)
−ωn 1
sZ = =− (3.115b)
2ξ RC

As Equation 3.114 suggests, to mitigate the spur level, we can increase the value of
C, and therefore ζ will be increased which now does not pose any problem for the
instability. Thus, the drawbacks of the type-I PLL are now resolved at the cost of lower
phase margin and consideration for stability due to increased order of the transfer
function. To increase the locking speed, one should increase ωn , and therefore, IKVCO
should be increased, or C could be decreased. Regarding the stability check of the
type-II PLL, further reading in the given references is recommended.

3.6 Conclusion
In this chapter, the general configuration of the PLLs was studied. Care should be
taken that in a PLL, the parameter of the study whose stability and response should be
considered is the phase (and consequently, the frequency), so here we are considering
the frequency response of the phase (or the frequency) in the loop. The phase detector
was one of the main components of the PLL whose implementation using a Gilbert
cell or an XOR was introduced. FM using a varactor-tuned oscillator was introduced
alongside an FM demodulator using a quadrature resonator. The FM demodulation
is possible using a sufficiently high-speed PLL. This concept was introduced as well.
FM is possible using a low-speed PLL whose concept was described in this chapter.
Frequency synthesizers are one of the basic building blocks of the modern transceivers.
The basic structure of a frequency synthesizer using a crystal oscillator, a frequency
divider, and a PLL including a second frequency divider was introduced as well. Type I
PLLs are based on a phase detector, a low-pass filter, and a VCO. This type of PLL
suffers from the problem of instability, and limited locking range. Type II PLLs were
3.7 References and Further Reading 165

introduced to mitigate the problem of instability and the locking range. The type II
PLL is based on a phase-frequency-detector, a charge pump, and a VCO. In sum,
the building blocks described in this chapter can be used as frequency modulators,
frequency demodulators, synthesizers, and eventually phase modulators.

3.7 References and Further Reading

1. F.M. Gardner, Phaselock Techniques, second edition, New York, NY: J. Wiley
& Sons, 1979.
2. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog
Integrated Circuits, fifth edition, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
3. D.H. Wolaver, Phase-Locked Loop Circuit Design, United Kingdom: Prentice
Hall, 1991.
4. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
5. T.C. Carusone, D.A. Johns, K.W. Martin, Analog Integrated Circuit Design,
Singapore: J. Wiley & Sons, 2013.
6. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
7. D.O. Pederson, K. Marayam, Analog Integrated Circuits for Communications,
Boston, MA: Kluwer Academic Publishers, 1990.
8. L.W. Couch, Digital and Analog Communication systems, eighth edition, New
Jersey: Prentice-Hall, 2013.
166 Chapter 3. PLL, FM Modulation, and FM Demodulation

3.8 Problems
Problem 3.1 Figure 3.38 depicts a simplified frequency synthesizer.

fref R KV fout(900MHz)
KP
s
C

÷M

30KHz

900MHz

Figure 3.38: Type I frequency synthesizer.

In the transfer function of the loop, the value of ζ is taken as 0.707 and ωn =
500 rad/sec, and KP = 10 V/rad. q q
ωLPF KV KP 1 MωLPF
1. First show that in this loop ωn = M , ζ = 2 KV KP .
2. For 30 kHz reference frequency, design the synthesizer for the channel spacing
of 30 kHz and a center frequency of 900 MHz. (Find the divider’s modulus M,
the low-pass filter’s RC time constant, and the VCO gain, KV ).
3. Find the settling time of the loop when it hops from the current channel to the
adjacent channel.
4. If we replace the phase detector with a bipolar Gilbert cell, find the value of RL
for a bias current of 5 mA to obtain KP = 10 V/rad.

Problem 3.2 It is possible to make an FM modulator out of a PLL as in Figure 3.39.

ĭref R KV ĭout
KP + s
fref= C
15MHz
Xin

÷60

Figure 3.39: Frequency modulator using a PLL.

Suppose that we have f3dBLPF = 100 Hz and ωn = 2π × 50 Hz.

1. Determine φout /φin in the Laplace domain.
3.8 Problems 167

2. If the signal xin is injected to the input of the VCO through RS , determine
the minimum and maximum frequency of the baseband input. Suppose that
R = 10 kΩ, C = 159.2 nF, RS = 100 kΩ, and the average capacitance seen
through the VCO is Cin,0 = 160 pF. You may use the equivalent circuit shown
in Figure 3.40 for this purpose.
3. If R1 = 400 Ω, and KV = 2π × 100 kHz/V determine the required KP and conse-
quently the tail current of the Gilbert cell phase detector.

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Figure 3.40: The equivalent circuit of the part of the PLL used as the FM
modulator.

Problem 3.3 In the synthesizer depicted in Figure 3.41, we have ωn = 2π × 45 kHz,

and Q = 0.5,
1. Find the loop filter’s cut-off frequency and the phase-detector gain if the VCO
gain is KVCO = 2π × 1 MHz/V.
2. If the value of M changes from 1000 and 1001, draw the control voltage
waveform.

ωLPF
Vout
÷N VCO
15MHz
N=15

÷M
M=1000

Figure 3.41: Frequency synthesizer using type I PLL.

Problem 3.4 FM Modulator; In the MOS oscillator stage depicted in Figure 3.42,
the right-hand section acts as a variable reactance which loads the left-hand oscillator
1
stage. Here, assume that r Cω 0
. Determine an expression for the variable reactance
seen through the right-hand section and from there obtain an expression for the fre-
quency of oscillations (the carrier frequency and the frequency deviation) in terms of
168 Chapter 3. PLL, FM Modulation, and FM Demodulation

the circuit parameters. Assume that both MOS transistors operate in the square-law
active region. Secondly, write an expression for the oscillation condition which deter-
mines the amplitude of oscillations. Here, f (t) is the low frequency baseband signal
varying between +1 and −1.

M12 VDD
Variable
reactance
L2 L1 R1 C1

M1 M2
+
Vinf(t)
r -
ID C∞
VGS0
-VDD
IDS=K(VGS-VTH)2

Figure 3.42: MOS-based FM modulator/VCO.

4. Mixers

4.1 Mixer Concept

Mixers are of integral parts of radio systems. Due to large-signal input, this block is
usually quite nonlinear. This three-port block is used in receivers to downconvert the
RF signal and in transmitters to upconvert the modulated signal. Due to their intrinsic
nonlinear behavior and port-to-port leakage, these blocks mandate specific analysis
for their operation. Moreover, taking into account their ever-existing harmonics in
transceivers, it is necessary to achieve a high-performance system. In normal mixer
operation, there is a large signal which is the local oscillator and two other small
signals which are the IF and the RF signals. Upon driving a mixer’s input toward
large-signal regime (either of IF or RF signals) depending on the fact that the mixer is
an upconverter or a downconverter), the output can pass through saturation.

4.1.1 The Conceptual Behavior of Single-Diode Mixers

Consider a simple mixer schematic as depicted in Figure 4.1.
Regarding the thermal voltage (VT = 26 mV at 300◦ K), one can roughly consider
the signals with an amplitude of less than 15 mV as small signal, and the signals in
excess of 100 mV as large signal. A silicon diode will turn on by the threshold voltage

D Vout

+
V1cosω0t
C R L
+
vScosωSt

Figure 4.1: Basic mixer schematic with a single diode.

170 Chapter 4. Mixers

of, say, 700 mV and shows a finite turn on resistance. We know the on-resistance of
the diode is equal to
VT
ron = (4.1)
ID
Normally, the turn-on resistance of the diode is in order of the few ohms which could
be considered as a short circuit compared to the load resistance (R). As such, once
the diode is on, a whole RF voltage would appear at the output. Once the diode is
turned off (has a large series impedance) in the negative half cycle of the LO signal, the
output voltage goes to zero. As such, the input RF signal is sampled at the rate of the
LO signal. The output voltage can be expressed as

vout = vs cos (ωst) .S (ω0t) (4.2)

where S(ω0t) is a square-wave signal that toggles between one and zero with the period
of the LO. Its Fourier expansion is expressed in Equation 4.40. The small-signal output
waveform is shown in Figure 4.2. It is obvious that within the right-hand product of
Equation 4.2, there exists the sum and difference frequency components of the RF and
the LO terms. As such, if the RF is at the input, the difference component gives in the
IF signal and if the IF was at the input, the sum component would give in the RF signal.
For now, we have shown that the large-signal input makes diode to be on and off
and when the diode is on, the input small signal appears at the output and when the
diode is off, there would be no signal at the output. Moreover, by virtue of the tuned
circuit, the desired frequency component of the signal would appear at the output. In
the next section, we delve into the nonlinear transconductance which is approximated
by a polynomial expansion.

4.1.2 A Nonlinear Circuit as a Mixer

Consider Figure 4.3. As Figure 4.3 suggests two input signal sources with finite
resistance generate a voltage v at the input of our nonlinear device. Then, the output
current passes through a resonant circuit. This voltage-dependent current source can
be assumed as a nonlinear transconductance. Here, we have assumed the characteristic
polynomial of the third order; however, in reality, this polynomial might be a more

vScosωSt

1.5V
0.7V
V1cosω0t t

Vout t

Figure 4.2: Input and output signals for Figure 4.1.

4.1 Mixer Concept 171

RS i=av+bv2+cv3
+ +
VLcosωLt L C R
Rin v i
+
VRcosωRt

Figure 4.3: Polynomial model for a nonlinear current source.

complex function such as an exponential one. In radio communication, the weak signal
is received by the antenna which is noted in Figure 4.3 as (VR cos ωRt) and then this
signal is mixed with the local oscillator signal noted as (VL cos ωLt). Therefore, one
may express the output current as

i = a (VR cos(ωRt) +VL cos(ωLt)) + b(VR cos(ωRt) +VL cos(ωLt))2 + (4.3)

3
c(VR cos(ωRt) +VL cos(ωLt))

Our objective is to find the product term of RF and LO frequencies in Equation 4.3.
We can expand Equation 4.3 to arrive at Equation 4.4:

i = aVR cos(ωRt) + aVL cos(ωLt) + bVR 2 cos2 (ωRt) + bVL 2 cos(ωLt) (4.4)
3 3 3 3
+ 2bVRVL cos(ωLt) cos(ωRt) + cVR cos (ωRt) + cVL cos (ωLt)
+ 3cVR 2 cos2 (ωRt)VL cos(ωLt) + 3cVR cos(ωRt)VL 2 cos2 (ωLt)

Each nonlinear circuit is capable of receiving both large and small signals, and by
virtue of its nonlinearity generates the harmonics of the inputs and their products. We
can define each component of Equation 4.4 as “RF,” “LO” themselves, and “RF 2nd
harmonic and a DC component,” “LO 2nd harmonic and a DC component,” “desired
component of IF,” “3rd harmonic of RF,” and finally “3rd harmonic of LO.” With the
following trigonometric equations

1 + cos (2ωt)
cos2 (ωt) = (4.5)
2
3 1
cos3 (ωt) = cos (ωt) + cos (3ωt) (4.6)
4 4
In real design, however, the large signal is the signal of local oscillator which can
degrade the performance of the circuit due to nonlinear characteristic of diodes. More-
over, this signal can leak to other points of the circuit through the supply voltage line
and the ground line, and cause undesirable effects. This leaked signal upon a nonlinear
element can generate unwanted harmonics and mixing products. Finally, the main
drawback of a nonlinear system is the handling of strong interferes and intermodulation
products. This unfavorable mixing occurs in any nonlinear circuit with large-signal
input. Tuning circuit may be useful to mitigate the effect of harmonic generation. For
instance, if the LO frequency resides at 945 MHz and the RF frequency is at 900 MHz
(as in the GSM case), by tuning the resonant circuit at 45 MHz, we can suppress the
unwanted mixing products.
172 Chapter 4. Mixers

4.2 Third Order Intermodulation Concept in a

Nonlinear Amplifier
Consider Figure 4.3 where the amplifier had a third order polynomial characteristics,
here the input signals consist of two adjacent channels which we call father and
mother signals. If we write the I −V equation for the nonlinear amplifier, we arrive at
Equation 4.7:

VO =a (Vf cos(ωft) +Vm cos(ωmt)) (4.7)

2
+ b(Vf cos(ωft) +Vm cos(ωmt))
+ c(Vf cos(ωft) +Vm cos(ωmt))3

If rewrite Equation 4.7, we can reach to

VO =a (Vf cos(ωft) +Vm cos(ωmt)) (4.8)

+ b (Vf cos(ωft))2 + (Vm cos(ωmt))2
+ 2b (Vf cos(ωft)) (Vm cos(ωmt))

+ c (Vf cos(ωft))3 + (Vm cos(ωmt))3

+ 3c (Vf cos(ωft))2 (Vm cos(ωmt)) + (Vf cos(ωft)) (Vm cos(ωmt))2

Now, we can expand Equation 4.8 to obtain all the harmonic at the output. Until
now, we have carried out equations for the output harmonics of a nonlinear circuit.
Another important issue in a nonlinear amplifier is named as intermodulation (IM).
Our IM of interest is IM3 which is the intermodulation product caused by third-order
nonlinearity. Regarding two inputs as v1 = Vf cos (ωft) and v2 = Vm cos (ωmt) as to
adjacent channels, with respect to Equation 4.4, we then reach to

VO =aVm cos(ωmt) + aVf cos(ωft) + bVm2 cos2 (ωmt) + bVf2 cos2 (ωft) (4.9)
+ 2bVfVm cos(ωft) cos(ωmt) + cVm3 cos3 (ωmt) + cVf3 cos3 (ωft)
+ 3cVm2Vf cos2 (ωmt) cos(ωft) + 3cVmVf2 cos(ωmt)cos2 (ωft)

Then the third order IM components will be obtained as

3 3
VIM = cVm2Vf cos((2ωm − ωf )t) + cVmVf2 cos((2ωf − ωm )t) (4.10)
4 4
Figure 4.4 depicts the signal spectra at the input and the output of the nonlinear
amplifier.
As Figure 4.4 suggests by the virtue of nonlinearity in the amplifier, different
mixing products of the two input signals are generated at the output. However, in this
derivation, we have merely taken into account a polynomial of third order. Magnitude
of each component in Figure 4.4 can be easily computed by Equation 4.9. The
green component in Figure 4.4 is called the IM product of third order, because this
4.2 Third Order Intermodulation Concept in a Nonlinear Amplifier 173

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Figure 4.4: Representation of mixing products for two input adjacent channels.

term is generated due to the cubic term of the polynomial. This component can be
troublesome in wide-band receivers and we then linearize the amplifier to mitigate
this effect. As an example, suppose we have two adjacent channels with the frequency
of ωf = 2π × 100.2 MHz and ωm = 2π × 100 MHz. Thus, IM3 components reside at
2ωf − ωm = 2π × 100.4 MHz and 2ωm − ωf = 2π × 99.8 MHz. As each channel is
normally modulated by a random signal, the intermodulation products (IM3) could be
considered as a random noise for either of the channels. Thus, this might be a drawback
in receivers which can degrade signal-to-noise ratio (SNR) of the alternative channel.
Assuming the magnitude of adjacent channel equal to V , Equation 4.9 suggests that the
IM3 competent grows by V 3 and each channel power grows by V . This is an important
point which exacerbates more the SNR. Note, if the power of each channel is added
by 1 dB, IM3 component power will be added by 3 dB. This concern is mitigated by
linearizing nonlinear circuit.

4.2.1 Characteristic of Third-Order IM and Measurement Method

The evolution of the aforementioned concept is shown in Figure 4.5. The upper
nonlinear curve demonstrates the compression of the output signal with respect to
the increase of the input signal. Its slope for lower values of the input signal is

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Figure 4.5: Intercept point of first harmonic and third-order intermodulation.

174 Chapter 4. Mixers

approximately equal to one (or 10 dB/dec). The lower nonlinear curve shows the
evolution of the IM products level with respect to the input level. Its slope at the lower
values of the input is about three times of that of the main output (30 dB/dec). Both
of these curves saturate (experience a decrease in their respective slopes) at the high
levels of the input signals.
If one draws the tangents at the two curves at lower signal levels and extends them
far enough towards the higher levels, the two lines would intersect at a point which we
call the third input-intercept-point (IIP3 on the abscissa). Moreover, the output point is
called oip3 . Figure 4.5 shows a real compression of the output signal which is denoted
by the green line. In fact, the IIP3 point is a practical indication of the nonlinearity
of the amplifier. The higher it is, the more linear is the amplifier. The lower it is, the
more nonlinear is the amplifier. Another point of interest is the saturation point of the
amplifier and that point is where the difference between the linear input/output (tangent
line) characteristic and the nonlinear (the real) input/output characteristic comes to
1 dB difference value, is called the compression point. It is another indication of the
linearity of the amplifier. The higher the compression point, the more linear is the
amplifier. Regarding the compression point refer to (equ compression),

3
vmo = aVm + cVm 3 cos (ωmt) (4.11)
4

3
vfo = aVf + cVf 3 cos (ωft) (4.12)
4

Normally, in physical electronic devices, c/a is negative. As such, while increasing

the input, the slope of the output signal level decreases. This phenomenon is called the
compression in amplifier gain.

4.3 Basic Concept of Third-Order IM in a Basic Mixer

Till now, we have carried out computations for a nonlinear amplifier with two inputs.
However, in a mixer, we may have two adjacent channels at one port and the large-
signal LO at another port. Here, for the sake of simplicity, we assume that all the
signal components are added up at a single input port. Furthermore, we assume that
the device’s input capacitance is small enough such that its reactance is much larger
than the source resistance of the input signal. The nonlinear I −V characteristics for
the mixer are assumed to be a polynomial of the fourth order. Furthermore, a tuned
circuit is employed at the output to select the desirable components. Here we try to
demonstrate the same concepts of IM and compression for a mixer.
As it is obvious from Figure 4.6, the LO signal with two adjacent channels (namely,
the mother (vm ) and the father signal (vf )) are applied at the input of the nonlinear
mixer. We now compute the frequency content at the output. Using the mentioned
I −V characteristics, we arrive at Equation 4.13:
4.3 Basic Concept of Third-Order IM in a Basic Mixer 175

RS i=av+bv2+cv3+dv4
+ +
Vmcosωmt
+ i L C R
Vfcosωft Ci v
+
VLcosωLt
-

Figure 4.6: An approximation of a mixer with three input signals.

i = a (Vf cos(ωft) +Vm cos(ωmt) +VL cos(ωLt)) (4.13)

2
+ b(Vf cos(ωft) +Vm cos(ωmt) +VL cos(ωLt))
+ c(Vf cos(ωft) +Vm cos(ωmt) +VL cos(ωLt))3
+ d(Vf cos(ωft) +Vm cos(ωmt) +VL cos(ωLt))4
Equation 4.13 shows a large number of mixing products at the output. However,
with enough suppression of unwanted products achieved by the high-Q output tuned
circuit, most of these products are eliminated. Finally, at the output, two desired
downconverted signals plus two third-order IM products remain at the output. To better
understand the effect of IM3 product in mixers, suppose two adjacent channels residing
at 901 MHz and 902 MHz with an LO frequency of 945 MHz. The desired IF signals
would be at 43 MHz and 44 MHz and the undesired IM3 components will be at 42 MHz
and 45 MHz. Equation 4.14 describes the desired components of the downconverted
signal in the mixer. The first term in each of these equations stands for the linearly
converted signal and the second terms describe the compressive components of the
desired output signal. Note that in physical electronic devices normally db < 0 so that
the second term in this equation is a compressive one:
3
vIF m = bVmVL R cos (ωL − ωm )t + dVm 3VL R cos (ωL − ωm )t (4.14)
2
3
vIF f = bVfVL R cos (ωL − ωf )t + dVf 3VL R cos (ωL − ωf )t (4.15)
2
Equations 4.16 and 4.17 describe the third-order IM product in this mixer. As it is
obvious, both of them increase with a slope of 30 dB/dec with respect to the input
signals:
3
vIM m = dVm 2VfVL R cos (ωL − 2ωm + ωf )t (4.16)
2
3
vIM f = dVmVf 2VL R cos (ωL − 2ωf + ωm )t (4.17)
2
Figure 4.7 shows adjacent channels and LO frequency spectra.
176 Chapter 4. Mixers

This configuration of input signals may be troublesome in receivers and degrade

the performance of the receiver. The signals in Figure 4.7 are shown to be incident at
the receiver of Figure 4.8 of a desired channel with a frequency of 900 MHz.
In Figure 4.8, the desired channel is at 900 MHz. The desired signal at the output
of the first mixer will be at 45 MHz. The subsequent filter has suppressed the other
products and passes the signal with a 2 MHz bandwidth. Next, the downconverted
signal mixes again with 45.455 MHz LO and is downconverted to 455 kHz for final
filtering. Here, the problem arises from two alternative strong channels which are at
901 MHz and 902 MHz. These two channels give in mixing products at the mixer
output at 44 MHz and 43 MHz, as well as IM3 products at 42 MHz and 45 MHz. The
second IM3 product is atop of our desired downconverted signal and corrupts its SNR.
Figure 4.9 depicts this problem clearly.

4.3.1 The Desired Channel Blocking with the Third-Order IM Component

Since mixer circuits generate lots of IM components, we should take into account the
effect of those affecting our desired channel SNR. This component is the last term of
Equation 4.13. If we expand this term, we then arrive at Equation 4.18,

d(· · · + 12Vf 2 cos2 (ωft)Vm cos(ωmt)VL cos(ωLt) (4.18)

2 2
+ 12Vf cos(ωft)Vm cos (ωmt)VL cos(ωLt) + · · ·)

Now, if we just look at the low-pass signal components of Equation 4.18, we can obtain

ω1 = −2ωf + ωm + ωL , ω2 = −2ωm + ωf + ωL (4.19)

,QSXW 2XWSXW
VSHFWUXP VSHFWUXP

I0+] I0+]

Figure 4.7: Input/output signal spectrums at the mixer ports.

0+]“0+] .+]“.+]

5)
'HVLUHG 0+]
,QWHUIHUHU 0+]
/2 0+] /2 0+]

,QWHUIHUHU 0+]

Figure 4.8: IM3 product problem in DAMPS.

4.3 Basic Concept of Third-Order IM in a Basic Mixer 177

î

2XWSXW

î
î
VSHFWUXP

I0+]

0+] 6WURQJLQWHUIHUHUV

0+] 'HVLUHGVLJQDO
0+] 'HVLUHG,)VLJQDOZLWKXQGHVLUHG,0RIWKHLQWHUIHUHUV

Figure 4.9: The spectrum of signals for the mixer of Fig. 4.8.

The frequency components in Equation 4.19 are IM3 which should be taken into
account from linearity perspective. Whenever we record the input–output characteristic
of a linear system, we reach to a line with the slope of one which shows the small-signal
constant gain. In other words, if the input grows with just 1 dB, the output will be added
by the same value. However, in nonlinear systems, IM3 component will experience
3 dB growth with 1 dB input increase. For a highly linear mixer, the IIP3 value is
high. The problem that may arise is in the fading case of the desired signal and the
presence of high-level adjacent interfering (blocker) channels. The IM3 components of
the strong adjacent channels might fall within the reception bandwidth of the receiver.
This may be troublesome in radio systems. In the real world, however, this issue can
be alleviated by frequency hopping and the use of error-correcting codes. The presence
of a strong blocker (interferer) signal in a nonlinear mixer is a challenge. One way to
handle this challenge is to linearize the mixer.
Another IM component is IM5 that increases by 50 dB/dec of input increase and
has emerged by virtue of a term with the sixth order in the nonlinear model of the
transconductance. As stated earlier, IIP3 is the parameter which gives a measure of
linearity in a system, thus we intend to find an easy method to compute it through
input/output measurement. It can be proved that this value can be written as
∆dB
IIP3dBm = inputdBm + (4.20)
2
where in Equation 4.20, ∆dB is the difference between lines of output signal (slope one)
and output intermodulation (slope three), please refer to Figure 4.11. This equation is
proved in the next subsection.

4.3.2 Special Content: IM with Any Nonlinear Circuit as a Mixer

Consider Figure 4.10 which depicts how two signals are added at the input of the
mixer.
In the mixing mode, the output merely has the components of sum and differ-
ence frequencies of the input signal with the LO. To take into account just the IM3
component, consider Figure 4.11.
178 Chapter 4. Mixers

R2 VLcos(ȦLt)
V1=Vmcos(Ȧmt) R1

-
Output
V2=Vfcos(Ȧft) R1 + VA

VA=-(R2/R1)(V1+V2)

Figure 4.10: Implementation of signals’ sum to be applied to a mixer input.

2XWSXW
G%P ǻ

2,3

ǻ
1RLVH
OHYHO ,QSXW
G%P
,,3
,QSXW
OHYHO

Figure 4.11: Interpolation of the output signal and the intermodulation curves
to obtain third-order intercept point (IIP3 ).

Our goal is to derive a simple equation for IIP3 . To obtain IIP3 , first of all choose
a point which is in the low input power region for both lines. This is done for a
better approximation of the slopes of the tangents to those curves. Then, by a simple
subtraction of the dB levels recorded on those two lines, divide it by two, and adding
this value to the selected point operating value, we reach to IIP3 . That is
∆P (dB)
IIP3 (dBm) = Pin (dBm) + (4.21)
2
where ∆P is the signal to IM ratio in dB.
IIP3 could be roughly estimated at 7 dBm for a silicon diode mixer in the 50 Ω
system. In a silicon bipolar transistor Gilbert cell, it varies between −20 dBm and
−12 dBm at the input, and for its MOS counterpart, this value is in the range of
−15 dBm to −5 dBm. For applications which necessitate highly linear mixers, IIP3
can be up to 14 dBm. High IIP3 mixer is of great importance in radio systems. In
nonlinear systems and in the presence of interfering channels, signal detection is
somehow tough. In reality, the lines in Figure 4.11 never reach to one another due
to the compression phenomenon; however, the tangent lines give us the measure of
nonlinearity. If one decreases the level of the input signal, such that the desired output
component goes under the noise floor, that point determines the mixer sensitivity. On
the other hand, if we increase our input signal such that the output goes beyond the
compression point, and the resulting distortion in the signal causes error in the received
4.3 Basic Concept of Third-Order IM in a Basic Mixer 179

bits, that point is considered as the saturation point of the mixer. The difference in dB
between those mentioned levels defines the dynamic range of the mixer. To check the
accuracy of ones measurement, one may increase the signal by 1 dB and check the
IM3 component to increase by 3 dB. Another important point in Figure 4.11 is the 1 dB
compression point which is noted by p1 dB . Due to nonlinearity, the gain of the mixer
will be decreased, and the point where the gain drops by 1 dB is of great importance.
In practical system design, we usually work at a back-off (at a level 6 dB–10 dB lower
than the compression point to assure the required linearity) of roughly between 6 dB
and 10 dB with respect to compression point to prevent compression. In modern
applications, we need new techniques to manipulate IM component for better signal
detection. Figure 4.12 depicts a conventional receiver example.
We can also use a mixer to upconvert the signal, in a transmitter which is shown in
Figure 4.13.
In transmitters, both the LO and IF signal are large signals. 900 MHz band-
pass filter is placed to attenuate the other component of mixing residing at 990 MHz

900 MHz 900 MHz 45 MHz

LO2=945 MHz

Figure 4.12: Typical heterodyne conventional receiver block diagram.

LO,I=45 MHz

45 MHz 900 MHz 900 MHz

I

LO2=945 MHz
LO,Q=45 MHz

Figure 4.13: Typical conventional quadrature transmitter block diagram.

0 dB

200 30dB
KHz 60dB

400 KHz

899.6 899.8 900 900.2 900.4

MHz MHz MHz MHz MHz

Figure 4.14: Wide-band spectrum standard for GSM and ACPR effect.
180 Chapter 4. Mixers

alongside other components made up due to mixing process. In radio regulation

specifications, there are exact power versus frequency transmission windows which
are specified by the regulatory organizations in which a transmitter should fit its own
signal. Figure 4.14 illustrates the standard specification for one channel of the GSM.
In this standard, the base station may have seven different power levels which are
adjusted with respect to distance of the users.
In far distances, due to high-power transmission, the device battery will be dis-
charged fastly. The transmitted signal has a finite skirt in the frequency domain. By
virtue of nonlinearity in the receivers, the leaked spectrum may be troublesome for
adjacent channels. This effect is called adjacent channel power ratio (ACPR). Thus,
we have more complex consideration in transmitter design than the receiver, because
the leaked signal may act as an interferer for the other channel. It can be stated that in
both receiver and transmitter, mixers are crucial. If one desires to have a highly linear
mixer, they can use a diode mixer at the cost of lower gain. However, nowadays given
the availability of good MOS switches, we are able to design highly linear active and
passive switching mixers. In the next section, we discuss simple methods to analyze
those kinds of mixers.

4.4 Bipolar Transistor Active Mixer

A typical bipolar transistor mixer is depicted in Figure 4.15. The transistor is biased
in its active region. As it is seen in this figure, the input RF or IF signal is applied to
the base of the transistor and the local oscillator signal is applied to the emitter of the
transistor.
Assuming an exponential nonlinear characteristics for the emitter–base junction,
one can write

ie (t) = IES eqvBE /kT (4.22)

VCC
-

R1 C R L Vo

+
CB
Q2

+
VScosωSt R2
RE CE

VLcosωLt
+

Figure 4.15: A typical bipolar transistor mixer in its active region.

4.4 Bipolar Transistor Active Mixer 181

Here, the total base–emitter voltage consists of a DC voltage, a local oscillator voltage,
and an input signal voltage:

vBE = VBEQ + vS + vL (4.23)

By substituting the corresponding values of DC, LO, and input signal voltages in
Equation 4.22, we obtain

ie (t) = IES eqVBEQ /kT eq(VS cos(ωS t))/kT eq(VL cos(ωL t))/kT (4.24)

Expanding Equation 4.24, we obtain

" #
∞
ic (t) = αIES eqVBEQ /kT I0 (y) + 2 ∑ Im (y) cos (mωSt)
m=1
" #
∞
I0 (x) + 2 ∑ In (x) cos (nωLt) (4.25)
n=1

Here, In (x) or Im (y) are modified Bessel functions of the first kind which exponentially
increase with respect to their argument. It is noteworthy that I0 (x) tends to unity when
its argument tends to zero. In (x) for n ≥ 0 tends to zero when its argument approaches
zero. Furthermore, I1 (x) ≈ x/2 for x < 1. It should be added that
In+1 (x)
< 1, f or x > 0, n ≥ 0 (4.26)
In (x)
Equation 4.25 can be simplified to
" #
∞
qVBEQ /kT Im (y)
ic (t) = αIES e I0 (y) I0 (x) 1 + 2 ∑ cos (mωSt)
m=1 I0 (y)
" #
∞
In (x)
1+2 ∑ cos (nωLt) (4.27)
n=1 I0 (x)

Let’s denote the DC current, IE0 , by

IE0 = IES eqVBEQ /kT I0 (y) I0 (x) (4.28)

The collector current can be expressed as

I1 (y) I1 (x)
ic (t) = αIE0 1 + 2 cos (ωSt) + · · · 1 + 2 cos (ωLt) + · · · (4.29)
I0 (y) I0 (x)
Or

I1 (y) I1 (x)
ic (t) = αIE0 1 + 2 cos (ωSt) + 2 cos (ωLt)
I0 (y) I0 (x)

I1 (y) I1 (x)
+4 cos (ωSt) cos (ωLt) + · · · (4.30)
I0 (y) I0 (x)
182 Chapter 4. Mixers

Considering small-signal input and a large-signal LO, and given the fact that I0 (y) ∼
= 1,
I1 (y) y
I (y) ≈ 2 , one can rewrite the collector current expression as
0

I1 (x) I1 (x)
ic (t) = αIE0 1 + y cos (ωSt) + 2 cos (ωLt) + 2y cos (ωSt) cos (ωLt) + · · ·
I0 (x) I0 (x)
(4.31)
By separating the different components of the collector current, one can deduce from
Equation 4.31 that each component of the collector current appears through a certain
transconductance as it is followed.
The input signal frequency component would appear in the collector through a
small-signal transconductance, namely, gm :
IS = αIE0 y = gm vS (4.32)
The local oscillator frequency component would appear in the collector through a
large-signal transconductance, namely, Gm (x):
2I1 (x) 2I1 (x)
IL = αIE0 = gm vL = Gm (x) vL (4.33)
I0 (x) xI0 (x)

As it is seen in Figure 4.16, the large-signal transconductance of a bipolar transistor

decreases monotonically with the input large-signal voltage. So the large-signal
transconductance is generally smaller than the small-signal operating transconductance.
The large-signal transconductance goes from a normalized unity value, for the small
signal case, toward zero for very large values of the input LO signal.
The mixing products (sum or difference frequencies) would appear in the collector
through a conversion conductance, namely, gC :
I1 (x) I1 (x)
IωL ±ωS = αIE0 y = gm vS = gC vS (4.34)
I0 (x) I0 (x)

2I1(x)/(x.I0(x))
Gm(x)/gm
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0 x
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Figure 4.16: The normalized large-signal transconductance of a single bipolar

transistor stage as a function of the normalized local oscillator voltage.
4.4 Bipolar Transistor Active Mixer 183

The conversion conductance, gC , is

IIF IRF I1 (x)
gC = = = gm (4.35)
VRF VIF I0 (x)
As it is seen in Figure 4.17, the conversion conductance of a bipolar mixer increases
monotonically with the input large-signal local oscillator amplitude. It goes from zero
value for the small-signal LO to a saturating normalized value of unity with respect to
the operating point transconductance.
If the output RLC circuit is a high-Q one and it is tuned to the corresponding
mixing product (the sum or the difference frequency), the output voltage would have
either of the following forms
vO = VCC − gCVS RL cos ((ωS + ωL )t) (4.36)
which is used for an upconverting mixer.
vO = VCC − gCVS RL cos ((ωS − ωL )t) (4.37)
which is used for a downconverting mixer. As such, our active mixer would have a
gain of gC RL .
It is noteworthy that other unwanted signal components would appear at the output
if the Q factor of the RLC circuit is not sufficiently high. As an example, the unwanted
LO component and the unwanted RF signal component would have the following
values
VL,out = −Gm (x)VL ZL ( jωL ) (4.38)

VS,out = −gmVS ZL ( jωS ) (4.39)

I1(x)/I0(x)
gc/gm
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0 x
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Figure 4.17: The normalized conversion conductance of a single bipolar tran-

sistor stage as a function of normalized input LO voltage.
184 Chapter 4. Mixers

4.5 Mixer types Based on Switching Circuits

In this part, we introduce very useful methods to analyze mixers. This method is
based on the assumption of complete switching in the transistors that are driven by the
large LO signal. In our analysis, we use a Fourier series expansion of the switching
signal. Consider Figure 4.18 which shows three configurations of mixer circuits for
both bipolar and MOS implementation. Note that in all these figures, the required DC
bias of the LO and the RF signals is not shown.
For Figure 4.18, mixers (a) and (d) which are called unbalanced mixers, both RF
and LO signal leak to the output. Mixers (b) and (e) are called single-balanced mixers
from which RF signal leakage is removed (the LO signal appears at the output in
addition to the mixing signals). Finally, mixers (e) and (f) are called double-balanced
mixers where the RF and the LO components are nonexistent at the output of the mixer.
We will return back to this point later.

5/ 5/ 5/ 5/ 5/
9RXW
9RXW 9RXW
4 4
9/2 4 4 4 4
9/2 4
9/2

95) 4
4 4
95) 4 95)
,((

D E F

5/ 5/ 5/ 5/ 5/
9RXW
9RXW 9RXW
0 0
0 0 0 0
9/2 0 9/2
9/2

95) 0
0 0
95) 0 95)

,((

G H I

Figure 4.18: Different mixer circuit topologies, (a) bipolar unbalanced, (b) bipo-
lar balanced, (c) bipolar double-balanced, (d) MOS unbalanced, (e) MOS
balanced, and (f) MOS double-balanced.
4.5 Mixer types Based on Switching Circuits 185

4.5.1 Conversion Gain and Local Oscillator Leakage

To analyze the operation of the mixers, we first need to know Fourier series coefficients
of a square-wave signal. It can be shown that for a pulse signal toggling between 1 and
−1 with the period of TLO , the signal and its corresponding Fourier series coefficients
can be expressed as Equation 4.40:
∞
s (ω0t) = ∑ an cos (nω0t) (4.40)
n=1
sin nπ

2
an = nπ
4
where Equation 4.40 is valid for odd values of n; however, for even values of n,
coefficients are zero. Now, with respect to Fourier series coefficients, we perform our
computations for three different mixer configurations. Note for a pulse signal toggling
between 1 and 0 the Fourier series will have a 12 as the DC component and the AC
components of its Fourier series will be half of the AC component of the bipolar pulse
signal.

Unbalanced Mixer
One may obtain the output signal of mixers (a) and (d), considering a nonlinear power
series transconductance for the lower transistor switched by the LO driven upper
transistor in Figure 4.18 as
2
1 2 2
Vout = a + bVRF + cVRF + · · · + cos (ωLOt) − cos (3ωLOt) + · · · (4.41)
2 π 3π
Equation 4.41 is written using Equation 4.40. To simplify the operation of the mixers,
we can state that Q2 turns on and off by the LO signal. This implies that when this
transistor is on, the RF signal appears at the output; otherwise, the output is tied to the
supply voltage. Thus, we can assume that the RF signal is multiplied by a square wave
with the amplitude of 0 and 1 by the LO period. Therefore, we can attain a new set of
coefficients as
1
b0 = (4.42a)
2
an
bn = (4.42b)
2
Equation 4.41 suggests that there will be lots of mixing products at the output of the
mixer. Thus, we usually employ a low-pass filter at the output to suppress the unwanted
products. Moreover, note that the leakage of RF and LO signals to the output has come
from the DC within the parenthesis terms in Equation 4.42.

Single-Balanced Mixer
We can derive the output signal of mixers
(b) and (e) in Figure 4.18 as for Equation
4.43,
4 4
Vout = a + bVRF + cVRF 2 + · · ·

cos (ωLOt) − cos (3ωLOt) + · · · (4.43)
π 3π
The important point in Equation 4.43 is the effect of differential circuit on the Fourier
series of the LO frequency. It seems that the RF signal now is multiplied by a square
wave with the alternative amplitudes 1 and −1. Thus, no DC component at LO Fourier
series coefficients suggests no RF feedthrough at the output.
186 Chapter 4. Mixers

Double-Balanced Mixer
Finally, the output of mixers (c) and (f) in Figure 4.18 can be written as

3 4 4
Vout = (bVRF + dVRF + · · ·) cos (ωLOt) − cos (3ωLOt) + · · · (4.44)
π 3π

Equation 4.44 introduces no DC components at both LO and RF sides, thus the concept
of double-balanced mixer which doesn’t permit these signals to appear at the output
mixer is obvious. In fact, with this powerful analysis, we are able to compute any
mixing product gain and moreover understand the port-to-port leakages. Nonetheless,
with inevitable mismatches and offset voltages, a finite leakage signals would be
present at the output of the mixer. Today, MOS process offers very fast switches due to
lower capacitances and on-resistances which can operate for high frequencies. One
of the most important specifications of mixers is their linearity issue which has come
from the nonlinear transconductance of the input transistor which converts the input
RF voltage to the current that passes through the switch loads. LO signal applied to
the other transistors just turns them on and off and roughly doesn’t affect the linearity
issues. Another type of mixer which is called a passive switching mixer is shown in
Figure 4.19.
These circuits manifest better linearity because of no transconductance device
between the switch and the load. In other words, the signal itself is chopped by means
of switches and reaches the output. Figure 4.20 depicts a differential implementation
of a passive mixer which is somehow alike active ones without transconductance.

9/2
9/2 5 5
56 56
9,) 9,)

9/2 5 5
95) 95)
9/2

Figure 4.19: Passive switching mixer circuits.

VLO+

VLO+ VLO-
VRF -
VLO- VRF-
R R
VRF+ VLO+ VRF+
VLO- VLO+

VLO-

Figure 4.20: Differential implementation of passive mixer circuits.

4.5 Mixer types Based on Switching Circuits 187

Now, we present a set of relations to compute the small-signal conversion gains of

the mixers in Figure 4.18 (here, we have considered the transconductance for the
transistors is linear). For mixers (a) and (d) we may obtain

1 2
Vout = VCC − RL (IBias + gmVin cos (ωRt)) + cos(ωLt)
2 π

2 2
− cos(3ωLt) + cos(5ωLt) − · · · (4.45)
3π 5π

Equation 4.45 confirms the previously mentioned port-to-port leakage in an unbalanced

mixer and we can compute LO and RF leakage amplitudes as 2/πRL Ibias and 0.5gm RL ,
respectively. We can also attain the same equation for single-balanced mixers (b) and
(e) as

4 4 4
Vout = RL (IBias +gmVin cos (ωRt)) cos(ωLt) − cos(3ωLt) + cos(5ωLt) − · · ·
π 3π 5π
(4.46)

Equation 4.46 shows that input signal does not appear at the output and the LO leakage
is equal to 4/πRL Ibias . Finally, the double-balanced mixer output signal for mixers
(c) and (f) can be calculated as

4 4 4
Vout = gm RLVin cos (ωRt) cos(ωLt) − cos(3ωLt) + cos(5ωLt) − · · ·
π 3π 5π
(4.47)

where it shows there is no leakage to the output. However, with the definition of
conversion gain, i.e., the gain from IF signal to RF can be carried out as

Vout (IF) 1
= gm RL for unbalanced (4.48a)
Vin (RF) π
Vout (IF) 2
= gm RL for single-balanced (4.48b)
Vin (RF) π
Vout (IF) 2
= gm RL for double-balanced (4.48c)
Vin (RF) π
Note that the coefficient 4/π has come from the Fourier series expansion and 1/2 is
due to one of the sum or difference components obtained out of the multiplication
of cosines. Nowadays, double-balanced mixers are more frequently applied due to
suppression of port-to-port leakages. MOS devices present proper switches for mixing
purposes; however, their quadratic I −V characteristics are such that for a given bias
current, MOS devices have lower transconductance than their bipolar counterparts.
Moreover, note that their output impedance is lower than those of bipolar devices which
is not a merit. It is instructive to note that the main parameter in mixers is their linearity
issue rather than their conversion gain. Moreover, to alleviate the linearity issue, we
should linearize the input active device, because the upper side in the aforementioned
188 Chapter 4. Mixers

mixers is just switches. Figure 4.21 shows a bipolar unbalanced mixer with a tuned
circuit load.
In Figure 4.21, LO signal is connected to the base of Q1 and RF signal is applied
to Q2 . LO signal is large and might have the amplitude of a few hundred millivolts or
more and the RF signal is small. Transistor Q1 will roughly be on and off within each
LO period. When this device is on, it let the current flow to reach the resonant load
and the output voltage appears across the tuned circuit load. However, when Q1 is off,
the current passing through the Q2 collector is nearly zero and the output will be tied
to VCC . Figure 4.22 illustrates the concept of mixing in the mixer in Figure 4.21.
In each cycle, the following happens:
1. Q1 is off (negative half cycle of LO): in this case IC = 0.
2. Q1 is on (positive half cycle of LO): in this case IC = IE0 + gmVR , where IE0 is
VBB2 −VBEQ
IE0 = (1 + β ) (4.49)
R2
Then, in sum, the collector current of Q2 can be expressed as
iC (t) ' [IE0 + gmVR cos (ωRt)] S (ωLt) (4.50)

VCC

C R L

Vo
R2
Q2
+
VRcosωRt
VBB2

R1
Q1
+
VLcosωLt
VBB1

Figure 4.21: Bipolar unbalanced mixer functioning on the LO switching basis

(downconverter).
TLO
fRF=8fLO

TRF

Figure 4.22: A rough approximation of the output signal of Figure 4.21.

4.5 Mixer types Based on Switching Circuits 189

where S (ωLt) is a monopolar square wave varying between zero and one at the rate of
LO. Then

qIE0
iC (t) ' IE0 + VR cos (ωRt) S (ωLt)
kT

qIE0 1 2
= IE0 + VR cos (ωRt) + cos (ωLt)
kT 2 π

2 2
− cos (3ωLt) + cos (5ωLt) + · · · (4.51)
3π 5π

Finally, if the RLC circuit is tuned to the difference frequency, the output AC voltage
becomes
RL qIE0
vout ' VR cos ((ωR − ωL )t) (4.52)
π kT
In another mode of operation, a similar circuit topology can be used as an upconverting
mixer. Here a bypass capacitor CE is used between the Q2 emitter and the ground
(Figure 4.23). This capacitor should be sufficiently large to be short at the LO frequency
and adequately small to be open at the IF frequency. As such, the transistor Q1 acts as
a time-varying current source biasing Q2 at the rate of IF. Here, we have

VBB1 −VBEQ +VIF cos (ωIFt)

iE = (4.53)
RE

VCC

C R L

Vo
R2
Q2
+
VLcosωLt
VBB2

Q1 CE
+
VIFcosωIFt
VBB1 RE

Figure 4.23: Bipolar unbalanced mixer based on time-varying transconductance

(upconverter).
190 Chapter 4. Mixers

As the LO signal is considered to be a large signal, we should use the large-signal

transconductance of the bipolar transistor. That is

2I1 (x)
Gm (x) = gm (4.54)
xI0 (x)
qVL
where x = kT , and
q
gm = (IE0 + IEIF cos (ωIFt)) (4.55)
kT
and
VIF
IEIF = (4.56)
RE

The Q2 collector current becomes

q 2I1 (x)
iC (t) ' (IE0 + IEIF cos (ωIFt)) VL cos (ωLt) (4.57)
kT xI0 (x)

Finally, the output voltage of the mixer (if the RLC circuit is tuned to the sum frequency)
becomes
RLVIF I1 (x)
vout ' cos ((ωL + ωIF )t) (4.58)
RE I0 (x)

Mixers introduce a large amount of mixing products within the frequency spectrum
of the output current by virtue of device nonlinearity. However, the desired signal
is usually ωRF − ωLO component which is selected by the tuned band-pass filter.
This nonlinearity generates mixing products by two main sources. First, two adjacent
interferers may cause an undesired signal atop the desired signal due to IM3 component
as described before. Secondly, considerable leakage of LO and RF at the output causes
difficulties in extracting the desired signal. Another way to mix the two signals can be
implemented by applying both LO and RF signals to the base of a bipolar transistor.
Similarly, we can apply the LO signal at the emitter of a bipolar transistor and the
RF signal to its base. Finally, the exponential I −V characteristics of the device will
produce our desired mixing product. Figure 4.24 depicts a differential implementation
of a bipolar mixer which is single-balanced.
It should be noted that these mixers can also be implemented by MOS devices.
The important point in Figure 4.24 is the need for lower signal amplitude to achieve
the switching of Q2 and Q3 . In fact, in these devices, the RF current is applied to each
branch with a rate of LO signal. It can be roughly with a voltage of (VLO ) between
100 mV and 500 mV, the upper tree can be switched efficiently. In Figure 4.24, the RF
signal in each cycle appears at either of output terminals, while the other terminal is
grounded. Thus, we can assert the RF signal is multiplied by +1 or −1 alternatively.
Our objective is to obtain an equation for the output of the single-balanced mixer in
which the RF signal appears in common mode in the differential output. Since the
4.5 Mixer types Based on Switching Circuits 191

VCC VCC VCC

C R L L R C L R C
Vout
+
Vout
+ Q2 Q3
VLcosωLt
+1 or -1

Q1 Q1
+ +
VRcosωRt VRcosωRt
VBB1 RE VBB1 RE

Figure 4.24: Single-balanced bipolar mixer.

LO drive is 180◦ out of phase, with respect to the base terminals, its leakage will be
present at the differential output. One may obtain the output of the single-balanced
mixer of Figure 4.24 as follows

vC2 = VCC − iC2 ∗ ZL (4.59)

and

vC3 = VCC − iC3 ∗ ZL (4.60)

The output voltage becomes

vout = vC3 − vC2 = (iC2 − iC3 ) ∗ ZL (4.61)

Here ∗ sign stands for the convolution in the time domain or equivalently multiplication
of the corresponding impedances and current harmonics in the frequency domain. The
currents in each branch of the upper tree can be described as

IC VL cos (ωLt)
iC2,3 = 1 ± tanh (4.62)
2 2VT

The bias current of the upper tree is

VBB1 −VBEQ +VR cos (ωRt)

IC = (4.63)
RE
The differential output current becomes

1 VL cos (ωLt)
∆IC = iC2 − iC3 = [VBB1 −VBEQ +VR cos (ωRt)] tanh (4.64)
RE 2VT
192 Chapter 4. Mixers

For VL VT , one can write

1
∆IC ' [VBB1 −VBEQ +VR cos (ωRt)] S (ωLt) (4.65)
RE
where S (ωLt) is the bipolar switching function or the bipolar square wave toggling
between +1 and −1 with a rate of LO, where its Fourier expansion becomes as follows

1 4 4
∆IC ' [VBB1 −VBEQ +VR cos (ωRt)] cos (ωLt) − cos (3ωLt)
RE π 3π

4
+ cos (5ωLt) + · · · (4.66)
5π
Finally, the output voltage, if the RLC circuits are tuned to the difference frequency,
becomes as follows
2 RL
vout ' VR cos ((ωR − ωL )t) (4.67)
π RE
At last, we introduce the well-known Gilbert cell as a possible candidate for double-
balanced mixer. Figure 4.25 depicts the Gilbert cell. The output of this mixer can be
described in the same way as Equation 4.47. By the fact that the output is loaded by
CL , the low-pass term of Equation 4.47 would appear at the output of the mixer.

VCC
RL CL RL

Q3 Q4 Q5 Q6
V2

Q1 Q2
V1
IEE

Figure 4.25: Double-balanced mixer.

Example 4.1 Since the mixer circuit has three ports, how can we define power
in its ports? Moreover, discuss the IM3 component for two alternate interfering
channels with different spacings.

Solution:
Consider Figure 4.27.
4.5 Mixer types Based on Switching Circuits 193

Rin Rout
Rs RL
+
VRF

R1
+
VLO

Figure 4.26: Mixer circuit.

If we have matching at the input and at the output, we have Rin = Rs , Rout = RL ,
and then we may write the conversion power gain

VIF 2
2RL
GP = (4.68)
VRF 2
2Rin

Suppose that the desired channel resides at 900 MHz and the LO signal is at
945 MHz. Therefore, the IF signal will be at 45 MHz.
(a) Consider the interfering channels are at f1 = 901 MHz and f2 = 902 MHz,
and (b) imagine the two interfering channels are at f1 = 900.03 MHz and
f2 = 900.06 MHz. Both of these channels could make IM3 components (e.g.,
ωLO − (2ω1 − ω2 )) atop of the desired signal. One way to mitigate this issue is the
implementation of a band-pass filter at the mixer’s input to eliminate those inter-
fering channels. Figure 4.27 depicts the structure in this case. Using a band-pass
filter with 1 MHz bandwidth, it is possible to eliminate the interfering channels
in the case (a). But having a band-pass filter of 60 kHz bandwidth at 900 MHz is
practically impossible and eliminating the interfering signals would become impos-
sible in case (b) at this stage (in this case, either the linearity of the mixer should be
improved or the wireless standard should require the levels of the adjacent channels
to be less than a predetermined value).
Rin Rout
Rs RL
+
VRF

R1
+
VLO

Figure 4.27: Employing a band-pass filter to suppress input blockers in

order to avoid the resulting IM3 component.

194 Chapter 4. Mixers

4.6 Matching in Mixers

As in any RF circuit for the maximum power transfer, it is required that the input RF/IF
port and the output IF/RF port of the mixer to be matched to the source and to the load,
respectively. For this purpose, standard step-up or step-down LC matching circuits
could be used. Consider Figure 4.28 as an example of the input and output matching.
As Figure 4.28 suggests, a capacitive matching circuit along with an inductor
is placed at the input of the mixer to transform 1 kΩ input impedance of the mixer,
to 50 Ω source impedance value. Likewise at the output, another matching has been
realized to transform 1500 Ω output impedance of the mixer to 50 Ω value of load.
Here the mixer block could be replaced by a Gilbert cell, for example.

4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer

In this section, we investigate the nonlinear behavior of active devices to obtain the
input intercept point level. Suppose Figure 4.29 that shows a transistor which has a
bias of VBB and two input signals.
The I −V characteristic of the amplifier is approximated by a polynomial of third
order to obtain a IIP3 level. Let

i(t) = α0 + α1V + α2V 2 + α3V 3 (4.69)

Applying two input signals as in Figure 4.29 and substituting in Equation 4.69, we
then obtain

i(t) = α0 + α1 (A1 cos (ω1t) + A2 cos (ω2t)) (4.70)

2 3
+ α2 (A1 cos (ω1t) + A2 cos (ω2t)) + α3 (A1 cos (ω1t) + A2 cos (ω2t))

1000Ω 1500Ω

50Ω 50Ω

R1
+ +
VRF Rs= VLO R L=
50Ω 50Ω

900MHz 45MHz

Figure 4.28: Typical matching circuit for a mixer, step-up capacitive input
matching, and step-down capacitive output matching.
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer 195

i(t) i(t)

+ +
V2cosω2t V2cosω2t
+ +
V1cosω1t V1cosω1t

VBB VBB

Figure 4.29: Applying two large signals to a nonlinear device (bipolar or MOS
transistors) to compute the compression point and the third-order intercept
point.

If we expand Equation 4.70, it results in

 
signal compression
z }| {
 3 3 
i(t) = IBias + α1 A1 + α3 A31 + α3 A1 A22  cos(ω1t) (4.71)
 
 4 2 

3 3 3 2
+ α1 A2 + α3 A2 + α3 A2 A1 cos(ω2t)
4 2
3α3
+ A2 A21 (cos((2ω1 + ω2 )t) + cos((2ω1 − ω2 )t))
4
3α3
+ A1 A22 (cos((2ω2 + ω1 )t) + cos((2ω2 − ω1 )t))
4
α3 α3
+ A31 cos(3ω1 )t + A32 cos(3ω2 )t
4 4
As stated earlier, one of the important parameters in the nonlinear amplifiers is their
measure of linearity which is obtained by means of a two-tone test. In this test, by
increasing the amplitude of tones, the output will be compressed and the low-level
slopes of the first- and the third-order terms will intersect at a point which we call
the intercept point. The term shown in Equation 4.71. is called signal amplitude
compression term which has a nonlinear relation with the input level and causes the
decrease in the amplifier gain as the input level is increased. Figure 4.30 illustrates
two different curves, one traces the fundamental harmonic term at the output as a
function of input level, and the other illustrates the output third-order intermodulation
amplitudes as a function of the input too, both on the log–log scale.
The −1 dB compression point is a point where the output fundamental level is
1 dB less than the presumed linear fundamental output level. Given A1 = A2 = A, the
compression point is computed as
3 3 −1
α1 A + α3 A3 + α3 A3 = 10 20 .α1 A (4.72)
4 2
196 Chapter 4. Mixers

Log(i)
20log(α1Ain)
OIP3 20log(0.75α3Ain3)

1dB

Log(Ain=A1=A2)

Pin,1dB IIP3

Figure 4.30: Output current of the amplifier versus its input signals’ amplitudes.

or
9 α3 2
A = −0.11 (4.73)
4 α1
Note that for the nonlinear amplifier to be compressive, we should have
α3
<0 (4.74)
α1

Otherwise, for αα31 > 0, the amplifier would be expansive which is generally a nonphys-
ical amplifier. Therefore, in the case compressive (physical) amplifier, we would have

r
α1
A1 dB = 0.22 − (4.75)
α3
Note that this is the “two-tone” compression point. It can be easily shown, by putting
A2 = 0, that a single-tone compression point can be expressed as
r
α1
A1 dB = 0.38 − (4.76)
α3
Verification of the above equation is left to the reader. From Figure 4.30, we are able
to compute IIP3 by the intersection of the two linear terms (tangents) as

3α3 3
20 log (α1 Ain ) = 20 log − Ain (4.77)
4
which finally gives the corresponding amplitude as
s r
4 α1 4 α1
AIIP3 = = − (4.78)
3 α3 3 α3
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer 197

Note that in the above computations, we have assumed that A1 = A2 = A. Furthermore,

notice that in a physical compressive amplifier, α3 /α1 is always negative.
Equation 4.78 states that an amplifier with high fundamental harmonic content
(large α1 ) and a low third harmonic content (small absolute value of α3 ) results in high
level of IIP3 , that is, an amplifier with better linearity.

4.7.1 Compression Point and IIP3 in a Nonlinear Transconductance Mixer

Consider a nonlinear transconductance mixer with a fourth-order nonlinearity:

i(t) = α0 + α1 v + α2 v2 + α3 v3 + α4 v4 (4.79)

If we consider an input with the following form

v = V1 cos (ω0t) +VS cos (ωSt) (4.80)

Then the output current will have the following expression

i(t) =α0 + α1 (V1 cos (ω0t) +VS cos (ωSt)) (4.81)

2
+ α2 (V1 cos (ω0t) +VS cos (ωSt))
+ α3 (V1 cos (ω0t) +VS cos (ωSt))3
+ α4 (V1 cos (ω0t) +VS cos (ωSt))4

By sorting out only the desired output components at ω0 − ωS , we will have

i(t) =α2V1VS cos ((ω0 − ωS )t) (4.82)

3
+ α4V1VS3 cos ((ω0 − ωS )t)
2
3
+ α4V13VS cos ((ω0 − ωS )t)
2
+···

Therefore, the desired mixer output will have the following form

3 α4 2 3 α4 2
vout = α2V1VS RL 1 + V + V cos ((ω0 − ωS )t) (4.83)
2 α2 S 2 α2 1
As it is obvious from the above equation, the output signal is compressed both with
respect to VS and with respect to V1 . So we define the −1 dB compression point as a
two-variable equation as follows
3 α4 2 3 α4 2 −1
1+ V + V = 10 20 = 0.891 (4.84)
2 α2 S 2 α2 1
Or
2 α2
VS2 +V12 = −0.11 × (4.85)
3 α4
198 Chapter 4. Mixers

9

Į
U
Į
U

96

Figure 4.31: The locus of the saturation voltages in the VS -V1 plane.

Or in another form
r
1 α2
VS2 +V12 2 = 0.269 − (4.86)
α4

This describes the compression effect in a mixer, which depends both on the LO
level and the signal level. This equation also describes a circle in the V1 ,VS plane
(Fig. 4.31). For example, if one considers the signal as a small input, he/she would
obtain the compression point by putting VS = 0 in the above equation, and obtain
the compression point in terms of V1 . Otherwise, if one considers the LO as a small
signal, he/she would obtain the compression point by putting V1 = 0 in the above
equation, and obtain the compression point in terms of VS . In a more general manner,
one can consider any proportion between V1 and VS , and compute the compression
point through Equation 4.86.

Two-tone –1 dB compression point in a nonlinear mixer

If we consider an input with the following form
v = V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t) (4.87)
Then the output current will have the following expression
i(t) =α0 + α1 (V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t)) (4.88)
2
+ α2 (V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t))
+ α3 (V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t))3
+ α4 (V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t))4

By sorting out only the desired output components at ω0 − ωS1 and at ω0 − ωS2 , we
will have

3 α4 2 α4 2 3 α4 2
vout =α2V1VS1 RL 1 + V + 3 VS2 + V cos ((ω0 − ωS1 )t)
2 α2 S1 α2 2 α2 1
(4.89)

3 α4 2 α4 2 3 α4 2
+ α2V1VS2 RL 1 + V + 3 VS1 + V cos ((ω0 − ωS2 )t)
2 α2 S2 α2 2 α2 1
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer 199

In a similar manner, as described in the computation of the −1 dB compression point

for a single-tone, one can show that the −1 dB compression point can be computed
through the following equations for either of the two tones

2 2 2 α2
VS1 + 2VS2 +V12 = −0.11 × (4.90)
3 α4
and
2 2 2 α2
VS2 + 2VS1 +V12 = −0.11 × (4.91)
3 α4
These two equations describe the compression phenomenon in a nonlinear mixer for
two-tone excitation. If one considers VS1 = VS2 = VS , the above equations simplify to
the following
2 α2
3VS2 +V12 = −0.11 × (4.92)
3 α4
Or in another form
r
12 α2
3VS2 +V12 = 0.269 − (4.93)
α4
This describes an elliptical contour in the V1 − VS plane. That is the contour which
describes a predetermined compression value (here, 1 dB) in the V1 −VS plane.

IIP3 calculation in a nonlinear mixer

If we consider an input with the following form
v = V1 cos (ω0t) +VS1 cos (ωS1t) +VS2 cos (ωS2t) (4.94)
For a fourth-order nonlinear transconductance, the desired downconverted components
of the signal would be approximately (ignoring the saturating components of the
signals)
vIF = α2VS1V1 RL cos ((ω0 − ωS1 )t) + α2VS2V1 RL cos ((ω0 − ωS2 )t) (4.95)
The third-order IM components would be then
3
vIM = α4VS1 2VS2V1 RL cos (Ω0 − 2ωS1 + ωS2 )t+
2
3
α4VS1VS2 2V1 RL cos (ω0 − 2ωS2 + ωS1 )t (4.96)
2
With the same reasoning as in section 4.7, and considering VS1 = VS2 = VS , the IIP3
for a mixer is deduced
r
2 α2
AIIP3 = VS = − (4.97)
3 α4
α2
It is noteworthy that in a physical mixer whose characteristics is compressive, α4 is
always negative.
200 Chapter 4. Mixers

Normalized differential
VCC
collector current
∆I/IEE
ZL ZL
1
I1 I2
Vout 0.5
+
Q1 Q2
+ v/Vt
v -10 -8 -6 -4 -2 2 4 6 8 10 Normalized
-0.5 differential
IEE -1 input voltage

Figure 4.32: A typical differential bipolar stage and its corresponding nonlinear
transfer characteristics.

4.7.2 IIP3 of Differential Pair Amplifiers

As an example, we investigate the linearity of a differential pair bipolar transistor. We
can write for each branch of this cell’s current

I
I1 = EE (4.98a)
1 + exp − V cos(ωt)
Vt
I
I2 = EE (4.98b)
V cos(ωt)
1 + exp Vt

and subtracting the first equation from the second equation in Equation 4.98, we obtain
the differential current as

V cos(ωt)
∆I = IEE tanh (4.99)
2Vt
If we employ the Taylor expansion of tanh {.} as

x3
tanh(x) = x − +··· (4.100)
3
Now, the current–voltage characteristic becomes
3
V 1 V
∆I = cos (ωt) − cos (ωt) + · · · (4.101)
2Vt 3 2Vt
which results in
v
u
u4 1
2Vt
AIIP3 = t 1
= 4Vt ≈ 100 mV (4.102)
3
24Vt 3
4.7 Calculating IIP3 in Nonlinear Amplifier/Mixer 201

Normalized differential
VDD drain current
∆I/I0
ZL ZL 1
I1 I2
Vout 0.5
+
M1 M2 v/(VGS0-VTH)
+
v -5 -4 -3 -2 -1 1 2 3 4 5 Normalized
-0.5 differential
I0 -1 input voltage

Figure 4.33: A typical differential MOS stage and its corresponding nonlinear
transfer characteristics.

As another example for a MOS differential pair, one can write with a good
approximation
v 2 v
I1 = k VGS0 + −VTH for < VGS0 −VTH (4.103)

2 2
and
2
−v v
I2 = k VGS0 + −VTH for < VGS0 −VTH (4.104)

2 2

Note for 2v > VGS0 −VTH , one of the transistors goes to saturation and the other one

goes to cut-off. Here VGS0 is the common DC bias voltage of either of the transistors
whose value is obtained by the following
r
I0
VGS0 = VTH + (4.105)
2k
Then
2
I1 VGS0 + 2v −VTH
= 2 (4.106)
I2 VGS0 − 2v −VTH
Given
I1 + I2 = I0 (4.107)
Then
" 2 #
VGS0 − v/2 −VTH
I1 1+ = I0 (4.108)
VGS0 + v/2 −VTH
202 Chapter 4. Mixers

and
I0
I1 = 2 (4.109)
VGS0 −v/2 −VTH
1+ VGS0 +v/2 −VTH

similarly

I0
I2 = 2 (4.110)
VGS0 +v/2 −VTH
1+ VGS0 −v/2 −VTH

Finally, the differential output current would have the following form, for 2v <

VGS0 −VTH
 
v
VGS0 −VTH
∆I = I1 − I2 = I0   (4.111)
v2
1+
4(VGS0 −VTH )2

Otherwise

I1 = I0 v
for > VGS0 −VTH (4.112)
I2 = 0 2

This means ∆I = I0 for v > 2 (VGS0 −VTH ).

and

I1 = 0 v
for < − (VGS0 −VTH ) (4.113)
I2 = I0 2

This means ∆I = −I0 for v < −2 (VGS0 −VTH ).

The current in Equation 4.111 attains its maximum value of I0 once v/2 = VGS0 −
VTH . If v/2 > VGS0 −VTH , the transistor M1 goes to saturation and transistor M2 goes
to cut-off and the differential current remains at I0 . If −v/2 > VGS0 −VTH the transistor
M2 goes to saturation and transistor M1 goes to cut-off and the differential current
remains at −I0 . For a rough estimate of the IIP3 , one can write
" 2 #
vI0 v
∆I ≈ 1− (4.114)
(VGS0 −VTH ) 2(VGS0 −VTH )

Consequently, the third-order input intercept point amplitude is calculated as

v  
u
1
u4  = 4(VGS0 −V )
u
(VGS0 −VTH )
AIIP3 =t  1
√ TH = 2.31(VGS0 −VTH ) (4.115)
3 3
4(VGS0 −VTH )3
4.8 Linearization Methods in Mixers 203

4.8 Linearization Methods in Mixers

For now, we have learned that the nonlinearity is one of the most important issues in
the mixer design. In this section, we introduce methods to increase IIP3 in mixers.
One practical method is merely adding a small resistor in the emitter (or the source) of
the input transistors. This resistor is called the degeneration resistor due to decrease
in the conversion of gain of the mixers. This, however, alleviates linearity problems in
the mixers. Nevertheless, these resistors’ drawbacks are the worse noise figure and
lower conversion gain. Figure 4.34 compares the linearity of a bipolar transistor and a
MOS transistor pairs.
Not surprisingly, however, MOS devices versus bipolar show better linearity due to
quadratic I −V characteristics of the former versus the exponential characteristics of the
latter. Moreover, Figure 4.34 shows that the acceptable peak-to-peak range for linear
operation in bipolar devices is roughly 4Vt and this value for MOS is 2.3 (VGS0 −VTH )
peak-to-peak, which is normally larger, given the fact that the bias voltage above the
threshold of the currently used MOSFET’s is much larger than the thermal voltage
of the bipolar transistors. Thus, we can employ MOS device for the input RF signal
to achieve a better IIP3 . As stated earlier, one method to mitigate the nonlinearity is
to add degeneration resistor in the emitter/source which is shown in Figure 4.35. As
Figure 4.35 suggests, resistors R decrease the signal on the base–emitter junction of

Vout,Diff

BJT
MOS

Vin,Diff

4Vt

2.3(VGS0-VTH)

Figure 4.34: Input–output voltage characteristic of MOS and bipolar devices.

RF- M2 M3 RF- RF+ Q2 Q3 RF-

R R R R

I I

Figure 4.35: Degeneration resistor implementation to achieve linear behavior.

204 Chapter 4. Mixers

Q2 and Q3 transistors or gate–source terminal of M2 and M3 MOS transistors, thus

reducing the nonlinearity. The required condition to linearize the differential stage is
that the series resistance should be much larger than the inverse of the transconductance
of each transistor as the following
IEE RE
gm RE 1 or 1 (4.116)
2Vt
To determine the large-signal characteristics of the differential stage with the degenera-
tion resistors, given the above condition, one can write
IEE v
ie1 = + (4.117)
2 2RE
IEE v
ie2 = − (4.118)
2 2RE
Then
v
∆iee = ie1 − ie2 = for |v| ≤ RE IEE (4.119)
RE
∆iee = ie1 − ie2 = IEE for |v| > RE IEE (4.120)
The overall transfer characteristics of the differential stage are depicted in Figure 4.36.
The required condition to linearize the differential MOS stage is that the series
degeneration resistance should be much larger than the inverse of the transconductance
of each transistor, as follows
p
gm RS 1 or RS 2kI0 1 (4.121)
To determine the large-signal characteristics of the differential MOS stage with the
degeneration resistors, given the above condition, one can write
I0 v
id1 = + (4.122)
2 2RS
I0 v
id2 = − (4.123)
2 2RS

Differential
collector current
∆I

IEE

1/RE
-REIEE
vin
REIEE Differential
input voltage
-IEE

Figure 4.36: The transfer characteristics of a differential stage with degeneration

resistors.
4.8 Linearization Methods in Mixers 205

Then
v
∆idd = id1 − id2 = for |v| ≤ RS I0 (4.124)
RS
∆idd = id1 − id2 = I0 for |v| > RS I0 (4.125)

The overall transfer characteristics of the differential MOS stage are depicted in
Figure 4.37.
A drawback of the structure depicted in Figure 4.35 is reduction in voltage head-
room which is wasted on these resistors. Therefore, we can modify Figure 4.35 to
solve this problem which is shown in Figure 4.38.
This structure doesn’t consume DC power in the resistor and it is a good prototype
for a more linear mixer. Note that in any case the conversion gain of the mixer with
degenerative resistors would be reduced with respect to nondegenerative mixer. That
is the conversion gain of the mixer goes from a maximum value obtained for RE = 0
or RS = 0 to zero for RE 1/gm or RS 1/gm .

Differential
drain current
∆I

I0

1/RS
-RSI0
vin
RSI0 Differential
input voltage
-I0

Figure 4.37: The transfer characteristics of a differential MOS stage with

degeneration resistors.

RF- M2 M3 RF- RF+ Q2 Q3 RF-

2R 2R

I/2 I/2 I/2 I/2

Figure 4.38: Degeneration resistor implementation without voltage-headroom

usage.
206 Chapter 4. Mixers

Example 4.2 Find the input and output power alongside conversion voltage
gain for the single-balanced downconverting mixer. Here the capacitors, C, are
considered to be short-circuit at RF and the LO frequencies, and they are considered
as open-circuit at the IF frequency. Furthermore, RC is small compared to RL .

9&& 9&&

5& 5/ 5/ 5&
& &

9RXW

4 4
9/2FRVȦ/2W

56
4

95FRVȦ5W
9LQ
9%%

Figure 4.39: Single-balanced mixer.

Solution:
For computing the input power, we can write
1
Vin = VR (4.126)
1 + gin RS

where gin is the input transconductance of the transistor Q1 . Then

Vin2rms
Pin = ginVin2rms = (4.127)
Rin

Given the fact that C in open at the IF frequency, for the output power, we can write

2
V√
out
2
Vout
2 2
PoutIF = ×2 = (4.128)
RL 4RL

Finally, for the conversion gain, given the fact that the upper tree is switched at the
LO rate,one may write

4 1 2
AV = gm RL = gm RL (4.129)
π 2 π

4.8 Linearization Methods in Mixers 207

Example 4.3 In the given mixer circuit, the LO is at 2.4 GHz with 1 V differential
for the upper tree and the RF frequency is at 2.41 GHz.
(a) With 1 mV signal for RF amplitude, find the IF component amplitude.
(b) If the input amplitude for RF signal is 1 mV, find the capacitor C in order to
attenuate the adjacent channel with the same amplitude residing at 2.45 GHz by
6 dB. The desired channel bandwidth is 2 MHz.
(c) Calculate the amplitude of LO signal without the capacitor C at the output.
(d) Suppose the double-balanced Gilbert cell and write its advantage.
(e) While in single-balanced given circuit only one branch has the RF current, why
the RF leakage is zero?

& 5 Nȍ 5 Nȍ &

9RXW

4 4
9/2

,(

4 ȍ

P$ &’ 95)

Figure 4.40: Single-balanced mixer.

Solution:
(a) Considering complete switching of the differential pair, we have
2
gC = gm (4.130)
π
KT
rin = = 52 Ω (4.131)
qIE
rin 1 2 1 mV 2 0.5 mA
Vin = VBE ≈ VRF VIF = gm R × = 3 k×0.5 mV
rin + RS 2 π 2 π 25 mV
= 19.1 mV (4.132)

(b) To have 6 dB attenuation for the adjacent channel, we should have

ω2 ω2 1 ω2
−20 log = −6 ⇒ = 2 ⇒ ωc = = (4.133)
ωc ωc RC 2

where ωc is the cut-off frequency of the output filter. Consequently, the value for
capacitor will be
208 Chapter 4. Mixers

2 2
C= = = 2.12 pF (4.134)
Rω2 3000 (2π) 50 106

(c) For the LO leakage (without consideration of load capacitance, the LO will
have a square-wave form, then), we have

Vout = R IEDC + IRF cos ω0t S (ω0t) (4.135)

4 4
Vout = R IEDC + IRF cos ω0t cos ω0t − cos 3ω0t + · · · (4.136)
π 3π

where
VRF
IRF = (4.137)
50 + re

Then
4
VLO = RIEDC = 1.9 V (4.138)
π
(d) An important feature of double-balanced Gilbert cell is removing the LO and
RF leakage to the output.
(e) As it is seen from the above equations, only the LO and the mixing components
appear at the output and because the RF signal is common mode, no RF signal will
emerge at the output (even without C).

One of the most practically applied mixers is the MOS Gilbert cell shown in Figure 4.41.
This mixer doesn’t show second-order nonlinearity due to its symmetry. Moreover,

VDD
RL RL

M3 M4 M5 M6
+
V2
-

M1 M2
+

VRF VRF
2 2

RS
VBB

Figure 4.41: MOS double-balanced mixer.

4.9 Calculating Third-Order Input Intercept Point in Cascaded Stages 209

since it has no current source at the source of input devices, it provides a larger linear
range operation for the RF signal.

4.9 Calculating Third-Order Input Intercept Point in

Cascaded Stages
Till now, we have introduced useful parameters to understand the nonlinearity of an
amplifier or a mixer as a black box. In this section, we discuss the cascaded nonlinear
blocks’ behavior. The input–output relation of the two nonlinear blocks could be
assumed as

y1 (t) = α1 x (t) + α2 x2 (t) + α3 x3 (t) (4.139a)

2 3
y2 (t) = β1 y1 (t) + β2 y1 (t) + β3 y1 (t) (4.139b)

Replacing x(t) by a two-tone input signal, and computing y1 (t) as before, and then
replacing y1 (t) by the computed result, we would obtain a sinusoidal expansion for
y2 (t). Then, by following the same procedure as described in section 4.7, it can be
shown that IIP3 voltage will be
s
4 α1 β1
AIP3 = 3
(4.140)
3 α3 β1 + 2α1 α2 β2 + α1 β3

4.9.1 Third-Order Input Intercept Voltage of Cascaded stages in

Terms of Single-Stage Intercept Voltage
One can rewrite Equation 4.140 to obtain

1 1 α1 2 3α2 β2
≈ + + (4.141)
A2 IP3 A2 IP3,1 A2 IP3,2 2β1

Note that, given the fact that most of practical mixers/amplifiers use differential pairs
which have odd symmetry in their transfer characteristic, chances are that α2 and β2
are nearly zero. So, the third term in Equation 4.141 could be neglected with respect
to the first two terms. Equation 4.141 gives us an explicit equation to obtain IIP3 of
two cascaded stages. An important point is the effect of nonlinearity in subsequent
stages which will be more severe. We can compare Equation 4.141 with equivalent
resistance of parallel resistors, and by the assumption that the third term is neglected,
we can generalize Equation 4.141 to give the equivalent IP3 point for multiple stages
(here for three stages or more) as Equation 4.142:

1 1 α1 2 α1 2 β1 2
≈ + + +··· (4.142)
A2 IP3 A2 IP3,1 A2 IP3,2 A2 IP3,3

Here, it could be seen that the total IIP3 of cascaded stages is lower than each of them
in Equation 4.142. In other words, by the assumption of sufficient gain for previous
stages, the total IIP3 will be lower than the third stage IIP3 divided by previous gains.
210 Chapter 4. Mixers

In the above equation AIIP3 being the signal (voltage) amplitude and α1 and β1 being
the voltage gains, for a fixed input impedance system (e.g., 50 Ω), one can reexpress
Equation 4.142 in another form in terms of IIP3 powers and the power gains of the
stages as follows
−1 −1 −1 −1
PIIP 3 ,total
= PIIP3 ,1
+ PIIP G + PIIP
3 ,2 P,1
G G +...
3 ,3 P,1 P,2
(4.143)

4.9.2 Combination of Amplifier and Mixer

In many receivers’ applications, we use a structure of cascaded low-noise amplifier
and a mixer. As Equation 4.142 suggests, the IIP3 of total chain will be less than the
IIP3 of the mixer divided by the gain of LNA.

Example 4.4 The given architecture is for a global positioning system receiver.
The received signal frequency is 1575 MHz and has a 2 MHz bandwidth and its
power is −130 dBm. The LO frequency is 1579 MHZ which downconverts the RF
signal to a 4 MHz carrier. With the given specifications, find
(a) The overall noise figure and overall IIP3 .
(b) If the mixer is linear, with the given two interferer signals, how much the
interferers’ IM3 component is lower than the desired GPS signal.
(c) We consider the effect of IIP3 of the mixers and the LNA, what is the input
interferer signal level which results in an IM3 component with −140 dBm power
level at the output.
The system impedance is 50 ohms.

*Y G%
1) G%
,,3 G%P I 0+]

0+] ,
%: 0+]
$
I 0+]
0+] 4
G% 1) G%
,,3 G%P ʌ %: 0+]
* G%
G%P
/2

G%P
I0+]

Figure 4.42: Typical GPS receiver architecture and the neighboring interfer-
ing signals.
4.9 Calculating Third-Order Input Intercept Point in Cascaded Stages 211

Solution:
(a) For the noise figure of cascaded stages one can write (see cascaded noise figure
expression in section 9.5)

100.8 − 1

F2 − 1
F = L × F1 + = 100.2 × 100.3 +
G1 101.5
= 1.58 × (1.99 + 0.16) = 3.42 (4.144)
FdB = 10 log (3.42) = 5.35 dB

To calculate IIP3,tot , we have

AIIP3 2
 
2R
IIP3 = 10 log   (4.145)
1 mW

Converting dBm level into Volts, in a 50 Ω system we can write

q q
IIP3 IIP3
AIIP3 = 10 10 × 1 mW × 2R = 10 10 −1 (4.146)

For overall IIP3 we have

1 1 G1 2
= + (4.147)
AIIP3tot 2 AIIP31 2 AIIP32 2

Given the fact that there is a 2 dB loss ahead of the LNA, then the IIP3 of the
combined filter and LNA would be

IIP31 = 2 − 12 = −10 dBm (4.148)

Finally, for the overall IIP3 , we will have

26
1 1 G1 2 1 10 20
= + = −10 −1 + −20 −1 ⇒ AIIP3tot = 7.06 mV
AIIP3tot 2 IIP3
1 −1
IIP3
2 −1 10 10 10 10
10 10 10 10

(4.149)

 
A2IIP
3tot
2R
IIP3tot = 10 log   = −33 dBm (4.150)
 
1 mW
212 Chapter 4. Mixers

(b) At the LNA input, we have a pair of −57 dBm interfering signals. From
Equation 4.77, it can be seen that

3
AIM3 = α3 A3 (4.151)
4
or it can be rewritten as
3 α3 1
AIM3 = α1 A3 = α1 A3 (4.152)
4 α1 AIIP3 ,LNA 2

Now, the amplitude of the IM3 component, at the LNA output, can be computed as
q 3
1 3 1 15 −57 −1
AIM3 = α1 A = −12 −1 10 20 × 10 10 = 79.4 nV (4.153)
AIIP3 ,LNA 2 10 10

The desired GPS signal level at the output of the LNA (with 13 dB total gain)
would be
q
−117
AGPS = 10 10 −1 = 447 nV (4.154)

Since

447
20 log = 15 dB (4.155)
79.4

Therefore, the desired signal is 15 dB higher than the third-order IM of the interfer-
ing signal.
(c) To obtain an IM level of −140 dBm at the output, we should have

3 α3 1 1 33
AIM3 = α1 Ain 3 = 2
α1 Ain 3 = −33 10 20 × Ain 3 = 31.6 nV ⇒
4 α1 AIIP3 ,tot 10 10 −1

(4.156)
Ain = 32.9 µV
Ain 2
!
2R
Pin = 10 log = −79.7 dBm
1 mW

4.10 Important Point in RF Circuit Simulation

One of the most important parameters in any circuit simulation is the computation
time. It is quite clear that more points of simulation in each period result in much more
4.12 References and Further Reading 213

computation time. The important point is to decrease the ratio of the highest operating
frequency of the signal to its lowest frequency component. Once we have two exciting
tones with small frequency difference, their beat frequency will be very small. As such
in simulations related to IIP3 , it is recommended to increase the frequency distance
between the exciting tones. By this, we will avoid the requirement of too many points,
in the simulation, to differentiate between the frequencies of the exciting tones (and
consequently the beat frequency).

4.11 Conclusion
In this chapter, we have studied the different mixer topologies normally used in RF
circuits. The main application of the mixer block is to downconvert RF signal to IF for
detection in the receiver, or upconvert the IF signal to the RF in the transmitter.
It was shown that each mixer operates by virtue of its nonlinearity or switching
characteristics at the LO rate; however, evaluating the generated components needs
careful considerations to suppress unwanted mixing products. Moreover, a parameter
was introduced which is a measure of nonlinearity and was named 1 dB compression
point. Furthermore, in the presence of multiple input signals, another quantity was
introduced as the IIP3 , for computation of which analytical relations were presented.
Three different mixer topologies were studied, namely, unbalanced, single balanced,
and double balanced, and relations for port-to-port signal conversion were carried out.
Finally, methods to improve linearity in mixers by means of degeneration resistors
were investigated.

4.12 References and Further Reading

1. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog
Integrated Circuits, fifth edition, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
2. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
3. F. Farzaneh, RF Communication Circuits (in Persian), Tehran: Sharif University
Press, 2005.
4. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
5. R. Chi-Hsi Li, RF Circuit Design, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
6. J.R. Smith, Modern Communication Circuits, second edition, New York, NY:
McGraw Hill, 1997.
7. D.O. Pederson, K. Marayam, Analog Integrated Circuits for Communications,
Boston, MA: Kluwer Academic Publishers, 1990.
8. R. Dehghani, Design of CMOS Operational Amplifiers, Norwood, MA: Artech
House, 2013.
9. P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits,
Norwell, MA: Kluwer Academic, 1998.
10. J. Everard, Fundamentals of RF Circuit Design with Low Noise Oscillators,
United Kingdom: J. Wiley & Sons, Inc., 2000.
214 Chapter 4. Mixers

4.13 Problems
Problem 4.1 In the mixer circuit depicted in Figure 4.43,
1. Determine the output IF signal amplitude at 10.7 MHz for the case where the
RF current is iRF = 100 µA sin (2π × 100 MHz × t) and the LO signal is
VLO = 300 mV sin (2π × 89.3 MHz × t).
2. If the input signal has two components of the same amplitude one residing at
100 MHz and the parasitic one at 111.3 MHz, find the required 3 dB bandwidth
of the output low-pass filter. In order that the downconverted component of
the parasitic signal is 6 dB lower than the desired IF component, in this case,
calculate the appropriate value of C.
3. If the output low-pass filter has a 3 dB bandwidth of 11 MHz, find the parasitic
LO component at the output.
4. If the input has two components of 100 MHz and 100.1 MHz, compare the
conversion gain in dB for the output components at 10.7 MHz and 10.8 MHz
in comparison with the gain of IM3 components residing at 10.6 MHz and
10.9 MHz. In this case, we have
VRF = 50 mV sin (2π × 100 MHz × t)+50 mV sin (2π × 100.1 MHz × t) and the
bias current is 500 µA.

3V
RL=1kΩ RL=1kΩ
C

+ Q2 Vout Q3
vLO
-

iRF

Q1
+
VRF
ibias=500µA
VBB

Figure 4.43: Single-balanced differential pair mixer.

Problem 4.2 In the circuit in Figure 4.44, a single-ended mixer with the input and
output matching networks is depicted.
1. Determine the values of L1 and C1 in order to match the RF input to 50 Ω, assume
that the input impedance of the transistor is 2 kΩ. Furthermore, determine the
values of L2 and C2 in order to match the output to 50 Ω. Suppose that the
output impedance of the transistor is 200 Ω. The RF frequency is 1900 MHz
and the IF frequency is 200 MHz. Assume that the capacitances CB1 and CB2
are RF short-circuit.
2. If the signals at the base of the transistor are VRF < VT and VLO > 10VT , calculate
the IF output current alongside the RF leakage current at the output in terms of
4.13 Problems 215

transistor’s gm and find an expression for the IF output voltage and the output
leakage voltage in this case.
Note that the RF trap circuit is open circuit at the RF frequency and short circuit at
other frequencies, and the the LO trap circuit is open circuit at the LO frequency and
short circuit at other frequencies.

VCC
R2 C
R1 B2

CB1
L1 L2 C2
IF-out

Q1
50Ω C1 50Ω
LO
RF
vRF trap
trap
50Ω
vLO

Figure 4.44: Single-transistor mixer with corresponding matching circuits.

Problem 4.3 In the given mixer circuit depicted in Figure 4.45,assume the I − V
characteristics are described by i1 − i2 = 0.4vRF − 0.01vRF 3 tanh v2VLOT ,

1. Considering two signals of 50 mV amplitude at 104 MHz and 104.1 MHz at the
RF input, obtain the output components at 10.7 MHz and 10.6 MHz, consider-
ing a rectangular LO voltage in the upper tree (how?). The LO frequency is
114.7 MHz.
2. Compute the IM3 components at the output, and obtain the IIP3 point.

VCC

i1 RL=5kΩ RL=5kΩ i2
Vout

Q3 Q4 Q5 Q6
VLO

Q1 Q2
VRF
IEE

Figure 4.45: Gilbert cell double-balanced mixer.

216 Chapter 4. Mixers

Problem 4.4 In the circuit depicted in Figure 4.46, determine the IIP3 through
ADS computer simulation. To save the computation time, use two distant tones with
150 MHz and 155 MHz frequencies as an example. The LO frequency is 225 MHz.
Note that the output low-pass filter has a cut-off frequency of 75 MHz which affects
the outputs. If one employs two close tones with 150 MHz and 150.1 MHz frequencies,
for example, he/she might obtain the same results with a much larger computation time
(why?). Choose bipolar transistors with a fT greater than 5 GHz in this simulation.

+9V
2.12pF 1kΩ 1kΩ 2.12pF

47Ω 47Ω
Q3 Q4 Q5 Q6
LO

220pF 220pF
VRF+ Q1 50Ω 50Ω Q2 VRF-
50kΩ 50kΩ

1mA

-9V

Figure 4.46: Gilbert cell double-balanced mixer with a degenerative resistor.

Problem 4.5 Consider the differential pair MOS mixer circuit depicted in Figure 4.47
where the RF input signal is applied to the gate of M1 , the LO signal is applied between
the gates of the differential pair, and the output-tuned circuits are tuned to the difference
frequency. Considering the RF signal as VS cos (ωSt) and the LO signal as V0 cos (ω0t).
Find an expression for the output IF signal. Here consider that the RF signal is a small
signal and the LO signal is a large signal with V0 ≤ 14 (VGS0 −VTH ) where VGS0 is the
bias voltage of the MOS differential pair transistors. All the MOS transistors are biased
in the active region.

9''

/ & & /
7XQHGWRȦȦ6 7XQHGWRȦȦ6
4 4
9RXW
0 0

Y

&’
0

Y6 5 5

9''

Figure 4.47: Differential pair MOS balanced mixer.

4.13 Problems 217

Problem 4.6 In the downconverting mixer depicted in Figure 4.48, consider β of the
transistors is sufficiently large such that 2rπ ≥ 25 kΩ, and L = 765 nH with QL = 10.
Find the appropriate values of C1 and C2 for matching the 50 Ω RF source to the input
of the mixer. Furthermore, determine the required value of I to achieve a conversion
(10.7 MHz)
power gain GPC = PPout(104 MHz) = 12 dB. Note that the RF signal at the input of the
in
center tapped capacitor is vRF = 1 mV cos (2π × 104 MHz × t). Moreover, the quality
factor of the capacitors is assumed to be large.

VCC

89.2 0.3 2.48 2.48 0.3 89.2

nH kΩ nF nF kΩ nH
Vout

Q3 Q4 Q5 Q6
LO

C∞
Q1 Q2
50Ω C2 C∞
L 5kΩ I 5kΩ
C1
1.5V 1.5V
mV MHz
vLO=200 cos(2π×114.7 t)
Figure 4.48: Gilbert cell double-balanced mixer with input matching.

Problem 4.7 In this problem, we try to learn how to simulate the IIP3 point deter-
mination. In order to have a lower simulation time, we should choose two-tones far
enough for more time-efficient simulation. To begin the simulation (e.g., by ADS or
Cadence IC design), run the transient simulation for two different low-power signals
to obtain points A and B depicted in Figure 4.51. At the same time, find points C and
D through the IM3 component computation. By extrapolating the two straight lines,
you may find the IIP3 point. Note that a common-mode 2.5 V bias is applied to the LO
port. Furthermore, that you can use the following relations in your simulations:
2 2 2
(Va ) (Vb ) (Vout )
va = Va cos 2π (103 MHz)t, vb = Vb cos 2π (102 MHz)t, Pin = 8(R = 8(R , Pout = 2(R
in ) in ) out )
where Rin = 50 Ω and Rout = 1 kΩ.
Hint: choose a small value for Va and Vb while Va = Vb , and increase both of them
gradually.
218 Chapter 4. Mixers

5V
1kΩ 1kΩ
+ V -
out

Q3 Q4 Q5 Q6
LO

50Ω 100nF 100nF 50Ω

Q1 Q2
50Ω 50Ω
+ 5V +
Va 10kΩ 1mA 10kΩ Vb

1.5V 1.5V

LO=200(mV)cos(2π×114.7(MHz)t) LO-CM=2.5V

Figure 4.49: A matched Gilbert cell double-balanced mixer to test the IIP3 .

RFC
+ LO+
C∞ +
VLO/2
VLO -
VDC +- RFC - +
VDC +- VLO/2
-
C∞ LO-

(a) (b)

Figure 4.50: LO bias implementation, (a) practical implementation, and (b) LO

and bias application in the simulations.

G%'
VORSH
3RXWG%P G%'
VORSH
%
$

'

&
3LQG%P
,,3

Figure 4.51: IIP3 point determination through computer simulation.

4.13 Problems 219

Problem 4.8 If in an amplifier for the input signal pair of −70 dBm level, we obtain
output signals of −50 dBm and output IM3 components of −80 dBm,
1. Determine the IIP3 of a single-stage amplifier in dBm and its gain in dB (Hint:
use formula IIP3 = ∆p2 + pin ).
2. If two similar stages of the same amplifier are cascaded, determine the overall
IIP3 in dBm, and the output IM3 components in dBm in case of −70 dBm input
signals.

Problem 4.9 If the output spectrum of the first mixer in the receiver chain depicted
in Figure 4.52 is like what is shown in the figure,
1. Determine the IIP3 for the first mixer, if it has a conversion gain of 10 dB. (Input
signals reside at 899.97 MHz and 899.94 MHz. Moreover, fLO,1 = 945 MHz,
and fLO,2 = 45.455 MHz).
2. Assuming the second mixer having the same nonlinear characteristics as the
first mixer, find the spectrum of the output of the third filter and then given
unequal input signals, find the IM3 components at the output of the second
mixer (the transfer function of the third filter is also shown).
3. Find the output spectrum of the fourth filter.

LNA 3rd filter 4th filter

A B C D E F G
1st filter 2nd filter

fLO1 fLO2
|HBPF3| |HBPF4|

0dB 0dB
A B
-60dBm
-12dB/oct -12dB/oct
-90dBm
f(MHz) f(MHz) f(kHz)
45
45.03
45.06
45.09

44.97 45 45.03 425 455 485

Figure 4.52: The receiver chain intended for IM3 computation.

Problem 4.10 In the given receiver depicted in Figure 4.53, determine the overall
noise figure and the overall IIP3 (see section 9.5 for the expression for the noise figure
of the cascaded stages). You may determine the noise figure and the IIP3 of the first
four blocks, then those of the last two blocks, and consequently the overall noise figure
and the overall IIP3 . Then, suppose that the desired signal power is −60 dBm at the
input. If two interferer signals both with a power of −50 dBm at 60 kHz off the desired
signal and 120 kHz off the desired signal, respectively, appear at the receiver input,
calculate their effect at the output of the IF amplifier. What kinds of unwanted signals
appear at the output of the IF amplifier? How much the unwanted signals are lower
than the desired signal?
220 Chapter 4. Mixers

1) G% *Y G% *Y G%

,,3 G%P 1) G% 1) G%
* G% ,,3 G%P ,,3 G%P
0+] 0+] 0+]

0+] 0+] .+]

G% G% G%
I 0+]
)LOWHU
ȍȍ ȍ ȍ ȍ ȍ ȍȍ ȍ UHVSRQVH

_+%3)_
G%RFW

G%

ORJI
N+]
N+]
N+]

N+]

Figure 4.53: Receiver chain for determination of the overall noise figure and
overall IIP3 .

Problem 4.11 Considering a modulated IF input signal vs and a carrier signal v1 as

follows
vs = 50mV 1 + 0.8 cos 2π × 104t cos 2π × 10.7 × 106t

v1 = 1.5V cos 2π × 10.7 × 106t

determine the output voltage as shown in Figure 4.54.

10V
1kΩ 5nF

Vout
Si
Q1 α≈1 Q2
+
vs

3.3kΩ
+ Si
v1 α≈1

-10V

Figure 4.54: A mixer used as a synchronous detector.

4.13 Problems 221

Problem 4.12 Determine the main mixing component at the output. Furthermore,
calculate the LO leakage signal at the output of the mixer circuit depicted in Figure 4.55.

vs

+
Vout
+ +
v1 V 100Ω i C R L

i=0.1V+0.3V2+0.01V3 A L=50µH
V1=2cos(5×106t) V C=20nF
Vs=5[1+0.5f(t)]cos(9×106t) mV R=2kΩ

Figure 4.55: A transconductance harmonic mixer.

Problem 4.13 In the mixer circuit depicted in Figure 4.56, the LO signal is a square-
wave pulse train as depicted in the figure. Determine the output voltage at the sum
frequency and the unwanted component at the difference frequency.

v1(t) Rs
Vout
1kΩ
C R L
1V + +
t vs v1

-1V 1.5V Vdd=10V

T0=2π×10-8s
T0 vs=50(mv)[1+0.6cos(103t)]×cos107t L=826.4nH
MOS Parameters: C=100pF
VTH=1V R=2kΩ
K=2mA/V2

Figure 4.56: A switching upconverting mixer.

Problem 4.14 A transconductance mixer of Figure 4.57 has the I −V characteristics

as follows

i = αV + βV 2 + γV 3 (4.157a)
where
α = 2 mA/V (4.157b)
2
β = 0.5 mA/V (4.157c)
3
γ = −0.2 mA/V (4.157d)
222 Chapter 4. Mixers

Find the downconverted IF component and the parasitic component at ω = 1.4 ×

108 rad/s. Note that there is an inherent negative feedback in this mixer (how?), so you
should first find the time-variant transconductance of the nonlinear device.

M12 V

L1 L2
C1 R1 L0 C0 R0
is

vLO

R1=2kΩ R0=1kΩ
C1=100PF C0=1nF
L1=1μH L0=2.5μH
L2=100nH vLO=3cos1.2×108t V
M12=300nH
Is=50(1+0.5f(t))cos108t μA

Figure 4.57: A downconverting mixer using a series nonlinear device.

Problem 4.15 Consider the nonlinear transconductance with the specified I − V

characteristic in Figure 4.58. First, find the large-signal time-varying transconductance
and then determine an expression for the output signal of the mixer. Furthermore, find
an expression for the parasitic component at ω0 + ωs in this scenario.

vs
Rs
+

Vout
+ +
v1 Ri v i C R L

v1=V1 cosω0t Q>>1

vs=Vs cosωst Output circuit tuned to 3ω0+ωs
i=αv+Yv2+σv4

Figure 4.58: A harmonic upconverting mixer.

5. Modulation/Demodulation of Amplitude/Phase

Baseband signals are generally band-limited low-pass signals which cannot be directly
transmitted over the transmission medium. Furthermore, a huge number of different
signals should be transmitted simultaneously in a transmission medium (apparently
the air or other transmission medium), so it is imperative that the baseband signals to
be modulated over the radio carriers at different frequencies before being transmitted
over the air, with antennas of limited sizes. This allows different modulating signals
to be differentiated or to be distinct in the frequency domain. In this chapter, we
discuss the conventional modulation schemes alongside modern digital modulations
with high bandwidth efficiency. Moreover, we investigate the receiver structures for
the signal demodulation. One of the long-existing modulation schemes which is used
even today is the amplitude modulation (AM) for long-distance broadcasting. In this
method, the data are embedded on the amplitude of the signal, therefore it is sensitive
to amplitude noise. Furthermore, we introduce circuits to demodulate AM signals. One
of the applicable modulations is the phase modulation (PM). In this modulation, the
baseband data are embedded in the phase of the radio signal enabling high data rates.
We will then discuss quadrature amplitude modulation (QAM) which is one of the
most applied modulation schemes in modern radios, phase modulator and demodulator
in this chapter. Finally, a few special modulation schemes are investigated.

5.1 AM Modulation
We can represent a sinusoidal AM-modulated signal as follows

VAM = A cos(ωCt) (1 + m cos(ωmt)) (5.1)

where A cos(ωCt) denotes the carrier signal, m is the modulation index, and cos(ωmt)
is the baseband signal. For AM modulation signal, modulation index is equal to or less
than unity. Figure 5.1 depicts a typical AM-modulated signal. As it is obvious from
Figure 5.1, the baseband signal is embedded as the envelope of the signal. Moreover,
224 Chapter 5. Modulation/Demodulation of Amplitude/Phase

1+m

1-m

Figure 5.1: Sinusoidal AM-modulated signal.

Amplitude
spectrum

Baseband ωc
signal

f
LSB USB

Figure 5.2: Typical baseband and AM modulator output spectrum.

signal amplitude is limited between 1 + m and 1 − m values. Notice that we can expand
Equation 5.1 to achieve
m m
VAM = A cos(ωCt) + A cos(ωCt − ωmt) + A cos(ωCt + ωmt) (5.2)
2 2
Equation 5.2 shows that three frequency components appear at the output which are
ωC ± ωm , and ωC . If we assume that the baseband signal has a finite spectrum (low
pass spectrum), the output will be similar to what is shown in Figure 5.2.
Figure 5.2 illustrates the fact that the baseband signal is upconverted around the
carrier signal, and also subscripts LSB and USB refer to the lower sideband and the
upper sideband, respectively. This shows that the baseband signal is present at both
sides of the carrier.

5.2 AM Demodulation
The easiest method to demodulate the AM signal is to extract the baseband signal from
the envelope of the received RF signal. This can be done using a diode and a capacitor
which is shown in Figure 5.3.
In Figure 5.3, the antenna receives the AM-modulated signal, and develops an AM
voltage at the diode input. The R −C low-pass filter extracts the low-pass components
of the rectified signal which is the envelope of the RF signal. Figure 5.4 illustrates the
behavior of the circuit presented in Figure 5.3. As in Figure 5.4, the envelope of the
5.2 AM Demodulation 225

R C

Figure 5.3: Simple AM demodulator.

Figure 5.4: The concept of AM demodulation using a diode with R–C circuit.

1
Output signals (V)

-1
RC=50ns
RC=500ns
-2
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time (µs)

Figure 5.5: A failure-to-follow distortion once the modulation index is at its

maximum.

RF signal is proportional to the baseband data. As such, the nonlinearity might affect
the demodulation process. Figure 5.5 illustrates an AM signal with the modulation
index of unity.
In Figure 5.5, the carrier frequency is selected to be 10 MHz and the baseband
signal is assumed to be 1 MHz. A problem arises once the R-C time constant of
the output circuit is too long with respect to the period of the modulating signal. In
this case, a failure-to-follow distortion is caused once the R-C low-pass bandwidth is
insufficient. That is
1
≤ ωm (5.3)
RC
226 Chapter 5. Modulation/Demodulation of Amplitude/Phase

1
the output distortion will occur, so normally one should choose ωc RC ≥ ωm to have
less distortion.

5.3 Generating AM Signals

In this section, we introduce circuits which generate AM signals. Consider Figure 5.6
where the baseband signal is injected to the base of Q1 and generates a corresponding
baseband current which flows through the upper differential tree. If we assume that the
operation of the differential pair is switching (i.e., V1 >> Vt ), the baseband signal is
upconverted to the carrier frequency. Care should be taken such that the input transistor
does not enter the nonlinear region, so that the modulation process is held linear. On
the other hand, the RF signal imposed at the upper tree’s differential pair input can
be large enough to bring the pair into the nonlinear region. In this case, the carrier
and its harmonics will be modulated by the baseband signal. By virtue of the output
band-pass filters, the harmonics of the carrier can be suppressed. We now present a
detailed analysis of the modulation phenomenon. The time-varying bias current of the
upper tree, IE (the collector current of Q1), is expressed as

VBB +Vm cos ωmt −VBEQ

IE = (5.4)
RE

Defining the normalized RF input voltage amplitude of the upper tree as x

qV1 V1
x= = (5.5)
kT Vt

VCC VCC

C R L L R C
Vout
+ -
iE1 iE2
+ Q2 Q3
V1cos(ωct)
-

Q1 IE
+
Vmcos(ωmt)
VBB RE

Figure 5.6: Implementation of the AM modulator.

5.3 Generating AM Signals 227

The collector currents of the transistor pair (Q2 and Q3) can be expressed as

IE x
iE1 = 1 + tanh cos (ωct) (5.6)
2 2
IE x
iE2 = 1 − tanh cos (ωct) (5.7)
2 2
The time-domain differential output voltage can be described as

Vout = VCC − iE1 ∗ zL (t) − (VCC − iE2 ∗ zL (t)) (5.8)

where zL (t) is the impulse response of the load impedance, and ∗ stands for the
convolution process. The output voltage reduces to

Vout = (iE2 − iE1 ) ∗ zL (t) (5.9)

or
x
Vout = −IE tanh cos (ωct) ∗ zL (t) (5.10)
2
The load impedance in the frequency domain can be expressed as

R
ZL ( jω) = (5.11)
1 + jQ ω
ωc − ωωc

For harmonic components of the input frequency, the load impedance can be described
in terms of harmonic frequencies (i.e., for the nth harmonic). Note that the output
tuned circuits should be tuned to ωc
R nR − jnR
ZL ( jnωc ) = = ≈ (5.12)
1 + jQ n − 1n n + jQ (n2 − 1) Q (n2 − 1)

The output voltage in terms of harmonic frequencies can be expressed as

∞
Vout = ∑ [IE2 (nωc ) − IE1 (nωc )] × |ZL ( jnωc )| cos (nωct + ∠ZL ( jnωc )) (5.13)
n=0

Once the input RF voltage is sufficiently small (less than 50 mV for a bipolar differential
pair), the harmonics become negligible and the above expression is reduced to

IE (t)
Vout = − x cos (ωct) × R (5.14)
2
And the output in this case becomes the following which is apparently an AM-
modulated signal

R (VBB −VBEQ ) Vm qV1
Vout = − 1+ cos (ωmt) cos (ωct) (5.15)
2RE VBB −VBEQ kT
228 Chapter 5. Modulation/Demodulation of Amplitude/Phase

The modulation index of the above amplitude-modulated signal is

Vm
m= (5.16)
VBB −VBEQ
In the case where the RF input signal is a large signal, the transistors Q2 and Q3 will
be switched on and off sequentially. The differential output current can be written as
IE (t)
∆iout = S (ωct) (5.17)
2
where s (ωct) is a bipolar RF square wave with a radian frequency, ωc . Given the tuned
circuit loads, the output voltage will have the following form
2
Vout = − IE (t)R cos (ωct) (5.18)
π
Or

1 R (VBB −VBEQ ) Vm
Vout = − 1+ cos (ωmt) cos (ωct) (5.19)
π RE VBB −VBEQ
The harmonics of the carrier can be modulated by the baseband signal as well if the
output-tuned circuit is tuned to the either of the harmonics (3rd, 5th, 7th, etc.). This
phenomenon is shown in Figure 5.7. However, once the bandpass filter is tuned to
the carrier frequency, its harmonics will be attenuated by the output band-pass filters.
In any case, it is possible to compute the harmonic components at the output. Note
that in AM modulation we have always a carrier component, ωc , and two sidebands at
ωc + ωm and ωc − ωm .

Amplitude
spectrum
Input baseband signal

ωm

Amplitude
spectrum Output spectrum with
the effect of BPF
ωc
3ωc

Figure 5.7: The input baseband spectrum and the output spectrum of an AM
modulator (the two sidebands and the carrier are distinct in the output spectrum).
5.4 Double- and Single-Sideband Suppressed Carrier Generation 229

5.4 Double-Sideband and Single-Sideband Suppressed

Carrier Generation
We are able to remove the carrier signal at the output of the AM modulator by just
multiplying the baseband and the carrier signal in a balanced modulator. This can be
achieved by a balanced pair of AM modulators. Since the carrier itself is absent at the
output, this scheme is called double-sideband suppressed carrier (DSBSC). For this
case, the AM signal can be expressed as

VAM = kVc cos (ωct) . (Vm cos (ωmt)) (5.20)

where k is the mixer’s output proportionality factor. As Equation 5.20 suggests at the
output, we have two frequency components as ωc ± ωm and there is no effect of the
carrier signal itself. Since the AM signal has components at both sides of the carrier
(it has two sidebands) which transmit the same amount of information, the idea of
removing one of the sidebands comes to mind in order to have a more bandwidth-
efficient modulation. This modulation is called single-sideband suppressed carrier
(SSBSC). We can implement SSBSC by the block diagram shown in Figure 5.8.
Assuming sinusoidal baseband, for the sake of simplicity, the outputs of each of
the mixers become
π
V1 = kVcVm cos ωmt + cos (ωct) (5.21)
4
π
V2 = kVcVm cos ωmt − sin (ωct) (5.22)
4
and the total output after the summer becomes
h π π i
Vout = kVcVm cos ωmt + cos (ωct) + sin ωmt + sin (ωct) (5.23)
4 4
or
π
Vout = kVcVm cos (ωc − ωm )t − (5.24)
4

Vccosωct

-90º
V1
45º
Baseband
signal Vout
-45º SSB-AM-SC
V2

Figure 5.8: Block diagram implementation of the SSBSC AM signal.

230 Chapter 5. Modulation/Demodulation of Amplitude/Phase

which is apparently an SSBSC signal. The structure in Figure 5.8 occupies half of the
bandwidth of the DSBSC AM signal; however, its drawback is the implementation
of precise wideband phase shifter circuits which should have more than two decades
of bandwidth, for example, from 100 Hz to 12 kHz. To mitigate this problem, we
can implement the phase shifters after the upconverters. Finally, Figure 5.9 can be
presented as a modified version of Figure 5.8.
As Equation 5.24 suggests, the carrier and the upper sideband are not present at
the output and as a result, a better spectral efficiency is achieved.
Figure 5.10 illustrates an AM modulator where the LO signal is not present at the
output (suppressed carrier) because of the symmetry of the circuit at the baseband.
Here, the bias current of the upper tree becomes a function of the carrier voltage:
VBB +Vc cos (ωct) −VBEQ
IE = (5.25)
RE
The output of the upper tree becomes
Vout = (iE2 − iE1 ) ∗ zL (t) (5.26)
Assuming Vm ≤ Vt , we can write
IE qVm
Vout = − cos (ωmt) × R (5.27)
2 kT
In another form
Vc qVm R Vc Vm R
Vout = − cos (ωmt) cos (ωct) = − cos (ωmt) cos (ωct) (5.28)
2RE kT 2RE Vt
The carrier signal is suppressed at the output because it is the common mode at the
upper tree as stated in Chapter 4.

Vccosωct

-90º

45º
Baseband
signal Vout
-45º SSB-AM-SC

Figure 5.9: Block diagram implementation of the SSBSC AM signal with phase
shifters at the carrier frequency.
5.5 Synchronous AM Detection 231

VCC VCC

C R L L R C
Vout
+ -
iE1 iE2
+ Q2 Q3
Vmcos(ωmt)
-

Q1 IE
+
Vccos(ωct)

VBB RE

Figure 5.10: Circuit implementation of the DSBSC AM modulator.

5.5 Synchronous AM Detection

In this section, we introduce a number of circuits to detect the AM signal. Consider
Figure 5.11.

CL RL RL CL
- Vout +

Q3 Q4 Q5 Q6
v2

Q1 Q2
v1
AM Signal IEE

Figure 5.11: AM signal demodulator.

232 Chapter 5. Modulation/Demodulation of Amplitude/Phase

The circuit in Figure 5.11 is a synchronous AM demodulator based on a Gilbert

cell multiplier. In this circuit, the received AM signal is converted to RF current at
collector outputs of the lower tree. Using the Gilbert cell, these currents are multiplied
by the differential input of the upper tree. An important assumption here is that the
generated carrier frequency at the receiver, v2 , is phase locked to the carrier of the
transmitter. The analysis of the detection process is as follows.
The differential output current of the Gilbert cell is described as
qv qv
1 2
∆IE = IEE tanh tanh (5.29)
2kT 2kT

The output voltage will be in general form as

Vout = ∆IE ∗ zL (t) (5.30)

Assuming small-signal inputs, such that the Gilbert cell functions in the linear range,
the output simplifies to

qv qv
1 2 v1 v2
Vout = IEE ∗ zL (t) = IEE ∗ zL (t) (5.31)
2kT 2kT 2Vt 2Vt

Assuming the input voltages as

v1 = V1 (1 + m cos (ωmt)) cos (ωct) (5.32)

and

v2 = V2 cos (ωct) (5.33)

The low-pass output voltage simplifies to

V1V2
Vout = IEE RL m cos (ωmt) (5.34)
8Vt2

If we assume a large signal for V2 (i.e., hard switching of the upper tree), the AM
signal is in effect multiplied by a square wave of the carrier frequency, and as such, the
carrier harmonics are multiplied by the AM signal and the low-pass component will
appear at the output with a form as follows

2 V1
Vout = IEE RL m cos (ωmt) (5.35)
π Vt

The output is clearly proportional to the modulating signal. Figure 5.12 illustrates the
demodulation process.
5.5 Synchronous AM Detection 233

Amplitude
spectrum
RF input spectrum
ωc

Amplitude
spectrum
IF spectrum after LPF

ωm

Figure 5.12: AM demodulation alongside low-pass filtering of the output.

5.5.1 A Synchronous AM Detection (with carrier extraction)

While AM demodulation needs the carrier signal, we are able to use the input RF signal
to generate a proper LO (carrier) signal. Now, consider Figure 5.13.
We can amplify the input RF signal and limit it to obtain the LO (carrier) signal to
downconvert AM signal. The red amplifier is a limiting amplifier which suppresses
the modulating data and acts as a proper LO, carrier generator (limiters are covered in
Chapter 6). This receiver architecture is a low power consuming one because it does
not need a PLL circuit. The degeneration resistor Rs is placed for the sake of linearity
to decrease the level of baseband distortion at the output of the demodulator.
The upper tree’s differential pair current can be expressed as

∆ID = kv1 v2 (5.36)

The input AM voltage at the lower tree is

v1 = V1 (1 + m cos (ωmt)) cos (ωct) (5.37)

The AM signal voltage is limited to VL , by the limiting amplifier, so the input voltage
of the upper tree becomes

v2 = VL cos (ωct) (5.38)

234 Chapter 5. Modulation/Demodulation of Amplitude/Phase

VDD

C RL RL C
+ Vout -

M3 M4 M5 M6

GA M1 Rs Rs M2

+ +
v1 GB v2
-
-

Figure 5.13: Synchronous AM demodulation using a limiting amplifier.

The low-pass component of the product of the above two voltages at the output becomes

k
Vout = V1VL (1 + m cos (ωmt)) (5.39)
2

5.6 Gilbert Cell Applications

Gilbert cell is one of the most widely used circuits in RF communications. Table 5.1
shows its application with respect to input signal magnitude.
The same application could be implemented for the MOS Gilbert cell if we replace
Vt for the BJT by Veff = VGS0 −Vth for MOS devices. In Gilbert cell, as a phase detector,
the upper tree is operating as a switch and the lower tree is fed by a large signal. In
multiplier mode, both lower and upper trees of the circuit are fed by small signals.

Table 5.1: Gilbert cell applications (BJT).

Mixer Multiplier Phase Detector

Upper tree large-signal Upper tree small-signal Upper tree large-signal
Lower tree small-signal Lower tree small-signal Lower tree large-signal
VRF < Vt ,VLO >> Vt VRF < Vt ,VLO < Vt VRF >> Vt ,VLO >> Vt
5.7 Modern Practical Modulations 235

Finally, the most applicable usage of Gilbert cell which is a mixer is achieved by
prefect switching of the upper tree and small-signal injection at the lower tree.

5.7 Modern Practical Modulations

The aforementioned modulation schemes are not power efficient, and therefore they
don’t have further usage in today’s RF communications except for legacy radio and
television broadcasting. Today, the widespread modulations are QAM, M − QAM,
PSK, QPSK, and GMSK. These modulation techniques are visualized by means of
signal constellation. In signal constellation, each point has a unique amplitude and
phase which is corresponding to its transmitted or received signal. Figure 5.14 shows
signal constellation of 64-QAM which represents 64 points on the I − Q plane.
Moreover, we are able to demodulate these signals by the received constellation
point. If we know the amplitude and the phase of the received signal, based on
the constellation, we are able to understand the baseband transmitted data. In the
following subsections, we focus on these modulation schemes with their corresponding
constellation.

5.7.1 Binary Phase Shift Keying

This modulation has two points on its constellation. Figure 5.15 depicts the BPSK
signals and its own constellation.
This modulation scheme is capable of transmitting one bit per symbol on the
quadrature constellation. Its main drawback is hopping from 0◦ to 180◦ which is not
bandwidth efficient. It occupies more bandwidth in comparison with other high data
rate modulation schemes. In this scheme, we can say that bit “1” is transmitted by
A cos (ωct) and bit “0” by −A cos (ωct).

5.7.2 Quadrature Phase Shift Keying

This modulation scheme employs 4 symbols in its constellation. Figure 5.16 depicts
the QPSK constellation.
This scheme can send two bits per symbol, thus it has a higher bit rate than BPSK
in the same bandwidth. In QPSK, each unique two bits are transmitted by a signal as
mentioned in Equation 5.40a.

4
$HMij



,

Figure 5.14: 64-QAM signal constellation.

236 Chapter 5. Modulation/Demodulation of Amplitude/Phase

π
11 : A cos ωct + (5.40a)
4
3π
10 : A cos ωct + (5.40b)
4
π
00 : A cos ωct − (5.40c)
4
3π
01 : A cos ωct − (5.40d)
4
Figure 5.16 depicts the RF symbols in QPSK modulation for a 4 MHz carrier (as an
example) and 1 M symbol per second (2 Mbit/s) data rate, where all of them have the
same amplitude; however, all adjacent symbols are orthogonal to each other.

5.7.3 Quadrature Amplitude Modulation (16 – QAM)

In this modulation, the constellation has 16 symbols. Figure 5.18 illustrates its 16-QAM
constellation.
Generally, the relation between the symbol rate and the bit rate is

Rb = SR log2 m (5.41)

Q Acos(ωct)

0 1

* * I

I=1 I=-1 I=-1 I=1

Q=0 Q=0 Q=0 Q=0

Figure 5.15: Signal constellation of BPSK modulation and its corresponding

time-domain waveform.

10 11
* *45
0
I
01 00
* *
Figure 5.16: Constellation of QPSK modulation.
5.7 Modern Practical Modulations 237

Acos(ωt+π/4)
1

0.5
Output signals (V)

11 10 00 01

-0.5

-1
0 0.5 1 1.5 2 2.5 3 3.5 4
Time (µs)

Figure 5.17: Signal waveform in QPSK modulation and the corresponding

assigned bits.

* * * *
* * * * I
* * * *
* * * *
Figure 5.18: 16 − QAM constellation.

where Rb is the bit rate, SR is the symbol rate, and m is the number of symbol levels
(normally, the transmission bandwidth, BW , is chosen about the symbol rate). This
modulation transmits four bits per symbol. Thus, 16-QAM has a higher bit rate with
respect to the QPSK within the same bandwidth. In this scheme, each four bits are
transmitted by a single symbol. For the symbols, there are 3 different amplitude levels
and 12 different phase levels as shown in Figure 5.18. In this case there are 16 distinct
symbols, and therefore, Rb = 4SR .

5.7.4 Quadrature Amplitude Modulation (64 – QAM)

In this modulation, there are 64 symbols in the constellation. Figure 5.19 illustrates
64-QAM constellation.
This modulation transmits 6 bits per symbol. Thus, it has a better bandwidth
efficiency than 16-QAM. Symbols in this scheme have 10 different amplitude levels
and 52 different phase levels as shown in Figure 5.19.
It is noteworthy that the more bits per symbol are transmitted (more complex
modulation), the larger amount of SNR is needed to discern a symbol from its adjacent
one. That is to say, higher modulation levels need higher levels of transmission power.
238 Chapter 5. Modulation/Demodulation of Amplitude/Phase

* * * * * * * *
* * * * * * * *
* * * * * * * *
* * * * * * * * I
* * * * * * * *
* * * * * * * *
* * * * * * * *
* * * * * * * *
Figure 5.19: 64 − QAM constellation.

5.7.5 Generating Binary Phase Shift Keying Signal

Consider Figure 5.20.
The feed current of the differential pair in this figure is a function of the Q1 base’s
input RF signal:

VBB −VBEQ +Vc cos (ωct)

IE ≈ (5.42)
RE

The input baseband signal of the differential pair is expressed as

VBB = Vm f (t) (5.43)

VCC

C
Q2 Q3
RL
Baseband

Q1 IE
+
Vccos(ωct)
VBB RE

Figure 5.20: Circuit implementation of a BPSK modulator using a differential

pair.
5.7 Modern Practical Modulations 239

where f (t) is a random binary signal which varies between +1 and −1, and Vm is the
logic amplitude. The difference current of the differential pair (if VVmt < 1) becomes

IE Vm f (t)
∆iEE = (5.44)
2 2Vt

The analog output voltage across the load-tuned circuit becomes

VcVm RL
Vout = f (t) cos (ωct) (5.45)
4Vt RE

which is apparently a BPSK signal. As such, in Figure 5.20, the baseband signal, which
is equal to ±1, is upconverted to RF frequency and goes through the air by the antenna.
Then, the coupled signal with the BALUN (balanced to unbalanced) feeds two antenna
branches.

5.7.6 Generating and Detecting the Quadrature Phase Shift Keying Signal
It is possible to have a structure to transmit the baseband in QPSK form. The required
architecture is shown in Figure 5.21. Each point on the constellation can be conceived
→
−
by a vector such that V = Aejϕ . As a result, Figure 5.21 makes it possible to generate
each point
√ of the constellation.
√ For instance, for QPSK modulation, we can choose
I = ± 2/2 and Q = ∓ 2/2 and the modulated signal would have the following form

√
2
vc (t) = ai (t) cos ωct − aq (t) sin ωct (5.46)
2

FRVȦFW
%3)

,
6HULDOWR
SDUDOOHO
%LQDU\ FRQYHUWHU 2XWSXW
GDWD 4

%3)
VLQȦFW

Figure 5.21: Implementation of a QPSK generator.

240 Chapter 5. Modulation/Demodulation of Amplitude/Phase

FRVȦFW
/3)

, %LQDU\
,QSXW 3DUDOOHOWR
GDWD
VHULDO
FRQYHUWHU
4

/3)
VLQȦFW

Figure 5.22: QPSK receiver architecture.

Likewise, an architecture as depicted in Figure 5.22 can be used for QPSK demodula-
tion. The output voltages of the demodulator mixers can be expressed as
√
2
vo1 (t) = KVc (t) × cos ωct = K ai (t) + ai (t) cos(2ωct) − aq (t) sin(2ωct)
4
(5.47a)
√
2
Vo1,LP = K ai (t) (5.47b)
4 √
2
vo2 (t) = K Vc (t) × sin ωct = K ai (t) sin(2ωct) + aq (t) − aq (t) cos(2ωct)
4
(5.47c)
√
2
Vo2,LP = K aq (t) (5.47d)
4
where K is the proportionality constant of the mixer.
In this architecture, the in-phase and the quadrature bit streams are synchronously
detected and they are applied to the parallel to serial converter at the output of the
low-pass filters.

5.8 Effect of Phase and Amplitude Mismatch on the

Signal Constellation
In this section, we investigate the frequency response and the bandwidth efficiency
of modern digital modulation schemes. Of the most important parameter of digital
modulators is the trade-off between the bandwidth occupancy and the symbol rate.
For instance, QPSK and 64-QAM modulations having the same bandwidth of 50 kHz
to transmit the baseband data. The former would have a 100 kb/s bit rate and the
latter would have a 300 kb/s bit rate. A transmitter shown in Figure 5.23 is called
direct-conversion transmitter and it is used for modern digital modulation.
Figure 5.23 shows a quadrature transmitter. At the input, the serial-to-parallel
converter maps the baseband bits two by two at the input of the mixers. Then, the
upconverted signals are added at the output and drive the power amplifier to provide the
5.8 Effect of Phase and Amplitude Mismatch on the Signal Constellation 241

FRVȦW

%3)
“
, %3)
6HULDOWR
SDUDOOHO
'DWD FRQYHUWHU
4
“
%3)
VLQȦW

Figure 5.23: Direct-conversion transmitter architecture.

signal to be transmitted through the air. One of the main considerations in transmitter
design is quadrature mismatches which can be frequency- and time-dependent. These
errors cause the points on the constellation to change their phase/amplitude, and this
results in difficult signal detection. Moreover, it also degrades the detection probability
at the receiver. This phenomenon is shown in Figure 5.24. Here it is observed that
if the SNR is diminished, each symbol in the constellation might interfere with its
adjacent symbols, and therefore, introduce errors in the detection process.
Another assumption is the operation of mixers which act as ideal switches.
However, in reality, this may not happen and RF harmonics might be troublesome.
Figure 5.25 depicts the receiver for I/Q detection. Here it is assumed that the I and
the Q channels introduce an amplitude error of ∆G/2 and a phase error of ∆ϕ/2 on
each path.
Since the frequencies of transmission and reception in the direct-conversion sys-
tem are the same, the oscillators and mixers can be used for both purposes. This
architecture is called a coherent transceiver. Another drawback in this structure is
frequency variations due to temperature. Suppose the outgoing signal is at 900 MHz
which is generated by a temperature-compensated crystal oscillator (TCXO) which
has a 3 ppm frequency variation. This means that a frequency error of 2.7 kHz may

Q
High
SNR

* *
I

* *

Figure 5.24: Phase and amplitude error effect in QPSK modulation due to
noise, in two cases, low SNR and high SNR.
242 Chapter 5. Modulation/Demodulation of Amplitude/Phase

FRVȦWǻij
*ǻ* /3)

%3)
3DUDOOHOWR 'DWD
VHULDO
FRQYHUWHU

*ǻ* /3)
VLQȦWǻij

Figure 5.25: Quadrature receiver’s architecture.

occur during the operation of the circuit. This frequency deviation will result in the
rotation of the points on the constellation which in fact increases the probability of
error in detection. To mitigate this issue, one of the solutions is using a PLL to lock the
phase and the frequency of the LO to the received signal. Finally, we can summarize
the signal distortions in the following
(1) Gain mismatch results in rectangular constellation distortion (shown in
Figure 5.26).

** ** Ideal constellation

I Rectangular constellation

** **
(∆ G/2 gain mismatch
in each path)

Figure 5.26: Rectangular constellation distortion due to ∆G/2 gain mismatch

in each path of the quadrature receiver.

(2) Phase deviation results in parallelogram constellation (rotation) (shown

in Figure 5.27).

** ** Ideal constellation

I Parallelogram constellation

** (∆φ /2 phase mismatch

**
in each path)

Figure 5.27: Parallelogram constellation distortion due to ∆ϕ/2 phase mis-

match in each path of quadrature receiver.
5.8 Effect of Phase and Amplitude Mismatch on the Signal Constellation 243

(3) In QAM receivers, it is necessary to have a PLL to lock the LO to the

input signal.

5.8.1 Improvement of bandwidth efficiency

Consider Figure 5.28 which depicts signals in quadrature modulation.
By looking at the spectrum of Figure 5.28, a sinc(u) function with side lobes will
appear. However, if we assume that in QPSK modulation, a transition will happen that
results in 180◦ phase shift between two signals, it makes stronger side lobes which is
not desired. One of the methods to suppress this effect is to use offset QPSK (OQPSK),
its concept is shown in Figure 5.28. If we insert a delay equal to half of the bit period,
the mentioned transition will never happen and as a result, a lower side lobe may
be achieved. Furthermore, the fast transition itself between data bits may result in
more bandwidth occupancy. Nowadays, another efficient modulation is used which
is called Gaussian minimum shift keying (GMSK). In this scheme, in addition to the
above delay, we use a Gaussian low-pass filter to smooth the transition between data
bits to lower the side lobes. The transmission standards limit the level of the side
lobes, thus improving them is of great importance. The Gaussian filter has a low-pass

ž
SKDVHVKLIW

, ,

4 4

%LWSHULRG 7E 7E
7E
D436. E2436.

Figure 5.28: Signals in quadrature phase modulation, (a) a QPSK signal pair
with a 180◦ phase change, and (b) an OQPSK signal pair where the 180◦ phase
shift is avoided.

0DJQLWXGH 3KDVH

I I

*DXVVLDQOLNH /LQHDUSKDVH

Figure 5.29: Frequency response of a Gaussian filter (magnitude and phase).

244 Chapter 5. Modulation/Demodulation of Amplitude/Phase

FRVȦW

*)
%3)
6HULDOWR
SDUDOOHO
'DWD FRQYHUWHU
7E *)

VLQȦW

Figure 5.30: GMSK transmitter architecture.

Magnitude QPSK
OQPSK
GMSK

Figure 5.31: The comparison of the spectra of QPSK, OQPSK, and GMSK
signals.

magnitude behavior and a linear phase response which is equivalent to a constant delay.
Figure 5.29 shows the frequency response of a Gaussian filter (GF).
A typical GMSK transmitter block diagram is shown in Figure 5.30.
Figure 5.31 shows a comparison of the spectra of the three types of quadrature
modulations. As it is obvious, the GMSK has the lowest side-lobes’ level.
Although, nowadays, analog amplitude and FM for legacy radio and television
broadcasting are used, there are modern digital receivers with compatible analog
techniques for their detection, as well. The following example describes this issue to
detect frequency-modulated signal with I/Q demodulator.
R
Example 5.1 If we consider FM-modulated signal as X = A cos ω0t+k Vm
0
0
cos ωmt dt +φ , the instantaneous frequency will be ω0 + kVm cos(ωmt). Sug-
gest an structure to demodulate an FM signal with quadrature zero IF receiver (note
that this can be done by two analog multipliers, two differentiators, and a voltage
subtractor). In cell phones, FM signals are demodulated with this structure with
digital signal processing right after the mixers.

Solution:
We can use the structure shown in Figure 5.32 for FM detection.
5.8 Effect of Phase and Amplitude Mismatch on the Signal Constellation 245

cos(ω0t)
LPF LPF
A D

d/dt -
Xout
d/dt +

B C
LPF LPF
sin(ω0t)

Figure 5.32: Quadrature FM demodulator.

For the signals at nodes A and B, with the assumption of filtering out other
mixing products, we will have the low-pass components as

Z
A 0
0
XA = cos k Vm cos ωmt dt + φ (5.48a)
2
Z
A 0
0
XB = − sin k Vm cos ωmt dt + φ (5.48b)
2

By taking the derivatives of Equation 5.48, we then reach to

Z
d A 0
0
XA = − kVm cos (ωmt) sin k Vm cos ωmt dt + φ (5.49a)
dt 2
Z
d A 0
0
XB = − kVm cos (ωmt) cos k Vm cos ωmt dt + φ (5.49b)
dt 2

Finally, signals in nodes C and D with the assumption of low-pass filter at the
output will be

A2
XC = kVm cos (ωmt) (5.50a)
4
A2
XD = − kVm cos (ωmt) (5.50b)
4
A2
⇒ Xout = XC − XD = kVm cos (ωmt) (5.50c)
2
Using digital signal processors, this process can be implemented in digital domain
as well, as such a digital receiver could be compatible with an analog modulation
technique.
246 Chapter 5. Modulation/Demodulation of Amplitude/Phase

Example 5.2 For the zero IF receiver shown in Figure 5.33, given the fact that
the in-phase and quadrature detectors’ carriers are locked to the input carrier, prove
that the output will be the AM detected signal if m < 1.

Solution:
Consider the given receiver in Figure 5.33.

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;, ;,/3
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9ROWDJH
;LQ ;RXW
DGGHU

;4 ;4/3
/3)
VLQȦFW

Figure 5.33: Zero IF quadrature receiver.

One may write the input signal as

Xin = A cos (ωct + φ ) (1 + m cos (ωmt)) (5.51)

Then, for the output signal, we will have

XI = A (1 + m cos (ωmt)) cos (ωct + φ ) cos (ωct) (5.52a)

XQ = A (1 + m cos (ωmt)) cos (ωct + φ ) sin (ωct) (5.52b)
Xout = XI,LP + XQ,LP

where LP stands for the low-pass component of the signal.

A A
Xout = cos (φ ) (1 + m cos (ωmt)) − sin (φ ) (1 + m cos (ωmt)) (5.53)
2 2
A
= (1 + m cos (ωmt)) (cos (φ ) − sin (φ ))
2
√
2A π
= (1 + m cos (ωmt)) cos φ +
2 4

The above equation suggests that the output signal is dependent on the phase of the
input AM-modulated signal. For instance, if this phase is 45◦ , the output will be
zero. To solve this problem, indeed we should use a PLL to lock the LO signals
to the transmitted carrier signal. In other words, the received signal is injected
to a PLL, and then the phase values of the in-phase and the quadrature LO input
of the mixers are chosen in order to make the maximum amplitude which is a
5.8 Effect of Phase and Amplitude Mismatch on the Signal Constellation 247

phase difference of −45 ◦ between the LO and the carrier signal. That is to say, the
√
maximum value of 22A (1 + m cos (ωmt)) is achieved for φ = −45.
In case of digital signal processor implementation of the detection process, one
could implement the following relation
q A
Xout = XI2 + XQ2 = (1 + m cos (ωmt)) (5.54)
2
Apparently here, the use of a PLL is not needed.

Example 5.3 For the given synchronous AM detector presented in Figure 5.34,
the modulated signal has a form presented in Figure 5.35. Calculate the output
detected signal amplitude and the unwanted second harmonic component at 2 MHz.

9
& 5/ 5/ &
Q) Nȍ Nȍ Q)

4 4 4 4
Y Y
Y
5 5

Y 4 5( ȍ 4 Y

5 5
P$ P$

9
9&0 9

Figure 5.34: Zero IF synchronous detector.

t1=1ms
800mV

400mV

t2=1μs

Figure 5.35: The input AM signal waveform (v2 ).

248 Chapter 5. Modulation/Demodulation of Amplitude/Phase

Solution:
One can express the differential current of the Gilbert cell multiplier as (note that
here there is a linearizing resistance, RE = 500 Ω, between the emitters of the lower
tree)

IEE v1 v2
∆IEE = tanh (5.55)
1 + gm R2E 2Vt 2Vt

The large-signal input voltage of the upper tree switches the value of hyperbolic
tangent between +1 and −1 , so the differential output current can be expressed as

IEE v1
∆IEE = S (ω0t) (5.56)
1 + gm R2E 2VT

The switching signal in terms of its Fourier series can be described as

4 1 1
S (ω0t) = cos (ω0t) − cos (3ω0t) + cos (5ω0t) − · · · (5.57)
π 3 5

As such, the low-pass component of the output signal becomes

2 V1 (1 + m cos (ωmt)) gm
Vout = RL (5.58)
π 10 1 + gm R2E

It can be seen from Figure 5.35, the AM signal frequency is 1 kHz and the carrier
frequency is 1 MHz. The modulation index is also 0.333. The input voltage has the
following form

Vin = 600 (1 + 0.333 cos (ωmt)) cos (ω0t) (mV) (5.59)

The output voltage can be calculated as

1 + 0.333 cos (2π × 1000 × t) 2 0.04
Vout = 600 1000 (5.60)
10 π 1 + 0.04 × 250
= 139 (1 + 0.333 cos (2π × 1000 × t)) (mV)

The unwanted second harmonic (2 MHz) component at the output can be calculated
by considering the second harmonic current and the load impedance at 2 MHz. The
second harmonic component amplitude is the same as the DC current amplitude
(why?). The load impedance for the second harmonic component becomes

RL
ZL ( jω) = (5.61)
1+ jω ω
cut−off
5.10 References and Further Reading 249

where
1
ωcut−off = = 2π × 10 kHz (5.62)
RLC

RL
ZL ( j2π × 2 MHz) ≈ − j (5.63)
200
The unwanted 2 MHz output voltage will take the following form
π
Vout (2π × 2 MHz) = 0.2 1 + 0.333 cos 2π × 103t cos 4π × 106t −

(mV)
2
(5.64)

5.9 Conclusion
In this chapter, the AM modulation and demodulation techniques as well as double-
sideband suppressed carrier AM and single-sideband suppressed carrier generation
were studied. Different digital modulation techniques such as BPSK, QPSK, and
QAM were presented as well. The quadrature digital modulator architecture as well as
quadrature digital receiver were studied. The synchronous AM detection was presented
and the quadrature demodulator was used for AM and FM detection as shown in the
examples. Normally, the best modulation technique is the one that has the higher data
rate within the specified bandwidth. The maximum achievable data rate is specified by
the information theory formula Rb = BW × log2 (1 + S/N). This means that the more
we increase the discrete levels of digital modulation (in order to transmit more bits of
data within a symbol), the higher S/N level we need to be able to distinguish between
different symbol levels.

5.10 References and Further Reading

1. L.W. Couch, Digital and Analog Communication systems, eighth edition, New
Jersey: Prentice-Hall, 2013.
2. D.H. Wolaver, Phase-Locked Loop Circuit Design, United Kingdom: Prentice
Hall, 1991.
3. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
4. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
5. R.E. Ziemer, R.L. Peterson, Digital Communication and Spread Spectrum
Systems, New York, NY: MacMillan, 1985.
250 Chapter 5. Modulation/Demodulation of Amplitude/Phase

6. D.O. Pederson, K. Marayam, Analog Integrated Circuits for Communications,

Boston, MA: Kluwer Academic Publishers, 1990.
7. Robert Gallager, course materials for 6.450 Principles of Digital Communica-
tions I, Fall 2006. MIT OpenCourseWare (http://ocw.mit.edu/), Massachusetts
Institute of Technology.
5.11 Problems 251

5.11 Problems
Problem 5.1 In the QPSK transmitter/receiver system shown in Figure 5.36 using
MATLAB software,
1. Determine the transmitted spectrum with the random bit sequence generator at
the input of the baseband data. Assume that the LO is locked by a PLL.
5E .ELWVHF
5%6* 5DQGRPELWVHTXHQFHJHQHUDWRU
$FRVȦW
$FRVȦW
,W 4 4
I 0+] I 0+] ,U
“

6SOLWWHU
63
5%6*
FRQYHUWHU

“
4U
4W ,QSXW
,W
$VLQȦW
$VLQȦW
4W

Figure 5.36: QPSK 90 MHz trnsmitter/receiver system.

Note that the band-pass filters’ can be modeled as H( jω) = 1

ω
1+ jQ ωω − ω0
0
where we have ω0 = 2π (90 MHz) and Q = 10. Suppose the low-pass filters’
3 dB cut-off frequency is near 1 MHz and they are ideal.
2. For different values of It and Qt , derive the constellation for the received signal.
3. If the gain in the It path is multiplied by 1.1, while the gain in Qt path is unity,
draw the constellation again.
4. If the phase of A sin (ωt) at the transmitter varies by 5◦ in the transmitter, how
the constellation changes and what happens?

Problem 5.2 An AM signal is applied between the bases of Q1 and Q2 in the analog
multiplier as shown in Figure 5.37,

9
& Nȍ Nȍ &
9RXW

4 4 4 4

/2

4 Nȍ 4

5)

P$ P$

9
/2 P9FRVʌî.+]W
5) P9FRVVLQȦEWFRVʌî.+]W

Figure 5.37: Double-balanced synchronous detector.

252 Chapter 5. Modulation/Demodulation of Amplitude/Phase

1. Determine the capacitor C such that the second carrier harmonic at the output is
30 dB lower than the desired signal.
2. Determine the baseband component at the output. Assume that ωb = 2π ×1 kHz.

Problem 5.3 In the 16-QAM modulator depicted in Figure 5.38, two double-balanced
analog multipliers are employed like the one used in problem 2, terminated on 3 kΩ
loads.
1. Find the necessary amplitude for the input I and Q channels to achieve a
maximum output level of 100 mV. The LO signal has an amplitude of 200 mV
at 1 MHz frequency. Furthermore, determine the output spectrum about 1 MHz
for a bit rate of 4 kbit/s. (Note that in 16-QAM each symbol represents 4 bits of
information).
2. If the quadrature signal has a finite phase error of 5◦ , draw the generated
constellation. Moreover, if the resistor on the Q input path has a 10% error (that
is, it turns into 1.1 kΩ), how the constellation will be deformed.

9
Nȍ Nȍ Nȍ Nȍ
9RXW 9RXW

4 4 4 4 4
4
4
4

/2, /24

4 Nȍ 4 4
Nȍ 4

, 4

P$ P$ P$ P$

9

4
WROHYHO
““ 7R,LQSXW
FRQYHUWHU
“
63


'DWDLQ
FRQYHUWHU

,
“ WROHYHO
““ 7R4LQSXW


FRQYHUWHU


Figure 5.38: A typical 16QAM modulator using two balanced analog
multipliers.

Problem 5.4 The circuit depicted in Figure 5.39 is a balanced AM modulator. Con-
sider the MOS transistors have a threshold voltage VTH and K = 21 µnCox WL , furthermore
vS = VS cos (ωmt) and vRF = VRF cos (ωRFt).
1. Determine the modulation index of the current source, and then find an expres-
sion for the output voltage in terms of the input voltages, vs and vRF . Assume
VRF VGS −VTH and the DC voltage of the gate source junction is VGS0 .
2. If the RF voltage is sufficiently large to completely switch the differential pair,
find an expression for the output in this case.
5.11 Problems 253

3. If the capacitor C is equal to 5 pF and the carrier frequency is 1 GHz, determine

the required value of the inductors and the required value of the resistors in
such a way that while the output circuits resonate at the RF frequency, the third
output harmonic voltage will be 40 dB lower than the main harmonic.

VDD

R L C C L R
- Vout +

+
vRF
-

iS
RS

vS
-VDD

Figure 5.39: A balanced MOS differential pair AM modulator.

Problem 5.5 The circuit depicted in Figure 5.40 shows an envelope detector for
AM signals. The input voltage is vin = 4V (1 + 0.8 cos (2π fmt)) cos (2π f0t) where
fm = 10 kHz and f0 = 1 MHz.
1. Find the spectrum of the output signal near 10 kHz, 1 MHz, 2 MHz, and 4 MHz
through computer simulation.
2. What consideration must be taken into account for the values of R and C to have
minimum distortion?

Ge
V0=0.2 Vout

+
vin R 1.2kΩ C 13.3nF
-

Figure 5.40: AM Ge envelope detector.

Problem 5.6 In the circuit depicted in Figure 5.41, which is a synchronous AM

detector, the input is of the following form Vin = cos (ωct) (1 + m cos (ωmt)).
1. Describe the operation of the circuit.
2. Determine the proper cut-off frequency for the load filters and the RC avalue.
3. Considering the value of the tail currents and the degeneration resistor, deter-
mine the maximum input voltage swing for the proper operation of the detector.
4. Find an expression for the first, the second, and the fourth parasitic RF harmon-
ics at the output.
254 Chapter 5. Modulation/Demodulation of Amplitude/Phase

9&&

5 & & 5

4 4 4 4
/2

/LPLWHU
4 56 4

YLQ

+LJK
JDLQ$PS *$ ,66 ,66
9&&

Figure 5.41: Self-carrier generating balanced synchronous AM detector.

Problem 5.7 Determine the output signal in the circuit of Figure 5.42 where the
inputs are V1 = 20mv f (t), and V2 = 700mv cos 2π × 107t for two cases:
1. f (t) is a normalized analog voice signal of 10 kHz bandwidth limited to ±1.
What kind of modulation is realized in this case?
2. f (t) is a digital signal of 20 kbit/s rate, varying between ±1. What kind of
modulation is realized in this case?

9
9RXW 9RXW
/ ȝ+

& S)

Nȍ

4 4 4 4
ȍ

9

4 4
ȍ

9

$OOVLOLFRQ
WUDQVLVWRUVZLWK P$
Į 9

Figure 5.42: A double-balanced amplitude modulator.

5.11 Problems 255

Problem 5.8 In the amplitude detector depicted in Figure 5.43 for the given input
voltage, determine the output voltage.
Hint: Note that the input amplifier stage (given the unbypassed emitter resistor RE )
operates in the linear region. Furthermore, the envelope detector loads the output-tuned
circuit at the RF frequency by a value of ZL ( jω0 ) = R0 /2.

Ge
M12 V0=0.2 Vout
12V

R1 R0 C0
L1 L2 4kΩ 400pF
46kΩ 2kΩ 2.5nF

60nF
Si
α≈1 ZL(jω0)
Rs
50Ω R2 RE
+ L2=633nH
10kΩ 1.2kΩ
vs M12=1.9μH
L1=5.7μH

vS=1.2v(1+0.5cos105t)cos(2π×107t)

Figure 5.43: An envelope detector with the input RF amplifier.

6. Limiters and Automatic Gain Control

Amplifiers and limiters are among the important building blocks of communication
circuits. In this chapter, we deal with two different types of amplifiers which are
limiting amplifiers and automatic gain controlled amplifiers. The former category has
a high gain and we have introduced a few of its applications in Chapter 5; however,
the latter is concerning methods to control and change the gain of amplifiers which is
quite useful in radio receivers.

6.1 Limiting Versus Automatic Gain Control

The main amplifier goal is to amplify the received signal from a transimpedance
amplifier. Amplification level must be enough to satisfy the required input signal for
subsequent stages such as clock and data recovery circuits. Signal level for this goal is
roughly a few hundred millivolts. The main amplifier is also called back-end amplifier
because it is usually placed at the end of a receiver chain. Due to advantages of
differential amplifiers such as higher signal swing and common-mode noise rejection,
the main amplifiers are designed as fully differential at both the input and output.
In different applications, signal distortion due to nonlinearity may be specified by a
certain standard. However, automatic gain control (AGC) will adjust the circuit to
mitigate the nonlinearity effect.

6.1.1 Limiting Circuits

When a small-signal is applied to an amplifier, we may assume a linear response
without any distortion at the output. However, large-signal inputs might drive the
amplifier into nonlinear operation and cause distortion at the output. In differential
pair circuits which are of interest, part of the headroom voltage is dropped across the
tail current source. At large input levels due to switching behavior of the pairs, the
signal will be chopped. A limiter is a circuit which has a linear gain for small signals
258 Chapter 6. Limiters and Automatic Gain Control

and whose gain is reduced with increasing amplitude of the input. The characteristics
of a typical limiter are shown in Figure 6.1.
As Figure 6.1 suggests, for small-signal input, the limiter has merely a linear
response; however, while the input enters the large-signal regime, the output amplitude
will be then limited to a certain value.
As an example, for a differential pair limiter, one could write

vO = (VCC − RL ic1 ) − (VCC − RL ic2 ) = RL (ic1 − ic2 ) (6.1)

αIEE RL vi
vO = tanh (6.2)
2 2VT

It is obvious here that for small values of vi , the output would be linearly related to the
input and for large values of vi , the output will be saturated to a voltage of αRL IEE /2.

6.1.2 AGC Amplifiers

AGC circuits are usually made of an amplifier in which its gain can be adjusted and a
mechanism to control that gain for different input signals provides a desired output
signal. Unlike the limiter which limits the large-signal input, AGC circuits decrease its
own gain to suppress the effect of nonlinearity in circuits due to the large-signal input.
Figure 6.2 depicts typical characteristics of an AGC.

9&&
9R
5 5

9R
L& L&

9,3 9,1 9L

,(

Figure 6.1: (a) A typical limiting differential amplifier. (b) Input–output

characteristics of a limiting amplifier.

9R ,QFUHDVLQJ
LQSXW
DPSOLWXGH

9L

Figure 6.2: Input–output characteristics of an AGC.

6.2 Total Bandwidth with Multistage 259

6.2 Total Bandwidth with Multistage

One of the most important parameters in amplifiers is the gain bandwidth product or
briefly GBW. To achieve high data rate, we may need an amplifier with very high GBW
which may be greater than its unity-gain frequency. We can attain more GBW by
cascading amplifiers. Unlike operational amplifiers which need stability check under
feedback condition, the open-loop behavior of cascaded amplifiers doesn’t have this
restriction. The only feedback which is applied for these amplifiers is the offset cancel-
lation feedback that has a low-frequency nature. We now focus on frequency response
of cascaded amplifiers which have the same transfer function. Consider an amplifier
with the DC gain of A and a dominant pole at f0 . Thus, cascading will lead to a DC gain
equal to sum of the all gains (in decibels) and a cut-off frequency, f0 .

Example 6.1 Verify that a single-stage amplifier with an overall gain of 30 dB

and 3 dB cut-off frequency of 3 GHz achieves a GBW product of 95 GHz and
then determine the required GBW of each single stage, in a three-stage amplifier
configuration, in order to achieve the same GBW of 95 GHz. Assume that all the
amplifiers have a single dominant pole in their frequency response.
Solution:
Case I(n = 1): In this case, the overall GBW will be equal to single-stage gain
times its bandwidth, in other words
30
GBW S = GBW tot = 10 20 × 3GHz = 95GHz (6.3)

Case II(n = 3): The gain of an amplifier with a single dominant pole, in decibels,
as a function of frequency can be expressed as

A0
AdB (ω) = 20 log r 2 (6.4)
1 + ωωC

where ωC is the 3 dB cut-off frequency of the amplifier and A0 is the DC gain of

the amplifier. Now if we consider to have three stages of amplifiers to have the
same GBW, we should consider the 1 dB bandwidth of each stage (because the
overall frequency response will be the product of the frequency responses of each
stage). It is noteworthy that if one equates Equation 6.4 to 0.891A0 , he/she would
obtain the 1 dB cut-off frequency as ωC1dB = 0.5ωC3dB . Therefore, we would need
three stages of amplifiers with a 3 dB bandwidth of 6 GHz and a DC gain of 10 dB
each to achieve the same overall GBW. So, the GBW product of each stage is
10
GBWS = 10 20 × 6 GHz = 19 GHz (6.5)

In this case, the GBW of each stage is decreased approximately to one-fifth with
respect to the first case, which is of great interest.
Note that here the expression for the frequency response, in case II, would be
of the following form
260 Chapter 6. Limiters and Automatic Gain Control

03
A0
AdB (ω) = 20 log s (6.6)
2 3
1 + ωωC

0
where A0 is the DC gain of each stage (here, 10 dB).

The question which may arise is that is it possible to increase the number of stages
to achieve the same total GBW by lower GBW of each stage? This procedure may
continue till each stage has a gain more than unity. But care must be taken that in the
case of amplifiers, cascading the overall bandwidth would be reduced with respect to
each stage’s bandwidth as demonstrated in the previous example. In a real amplifier,
the nature of frequency response due to finite resistance and capacitance of subsequent
stage will be low-pass. Due to internal feedback at high frequencies and inductive
loads, this behavior of trading gain for bandwidth may change. Thus, increasing the
bandwidth may have an upper bound.

Example 6.2 Suppose an amplifier with a low-frequency gain of 12 dB and the

given transfer function. Obtain an equation for frequency response for increasing
number of stage for f0 = 1 GHz and H( jω) = 4/(1 + jω/ω0 ).
Solution:
General equation for the magnitude of n cascaded amplifier stages can be written as

 n
 4 
|Htot ( jω)| = 
r

2  (6.7)
1 + ωω0

Figure 6.3 illustrates the magnitude of frequency response of these cascaded

amplifiers.

3dB cut-off frequency

50 n=4
40 n=3
30
n=2
20
|H|(dB)

10 n=1
0
-10
-20
-30
-40
10 102 103 104
Frequency (MHz)

Figure 6.3: Magnitude of frequency response of the cascaded amplifiers.

6.3 Offset Compensation Circuits 261

As Figure 6.3 suggests when the number of stages increases, their overall
bandwidth decreases. Why all the curves pass through the same point at 0 dB
gain?

6.3 Offset Compensation Circuits

One of the most prominent effects which should be resolved in limiters is the offset
problem. As a rule of thumb, we can state that this value must be roughly lower
than 100 µV and if this value increases, it has a destructive effect on the receiver’s
performance. A bipolar amplifier usually has a 3 σ offset voltage of 1 to 2 millivolts,
where σ is the standard deviation of the offset voltage. This value reaches about
10 mV for high-speed MOSFET transistors. Both types of transistors have a very high
offset voltage which obliges us to provide a method to cancel it out. Now, consider
Figure 6.4.
Figure 6.4 shows a number of cascaded amplifiers. If we assume that due to
inevitable process variations there is an offset voltage, the high gain value of A will
saturate the final stages. Figure 6.5 illustrates an offset cancellation feedback loop
which is also capable of setting the input impedance near to R0 (note that feedback
circuit capacitors are AC short-circuit).

VOS
VIN VOP
VIP VON

Figure 6.4: Offset voltage at the input of the limiting amplifiers.

R0

R0 C1 C1
R1 R1
C
VIP VOP
VIN VON
C

Figure 6.5: Offset cancellation loop with negative feedback, where R0 = 300 Ω,
C1 = 0.1 µF, and R1 = 20 kΩ.
262 Chapter 6. Limiters and Automatic Gain Control

Limiting amplifiers are mostly used at the back-end of a receiver and thus are
low-frequency (e.g., 455 kHz) building blocks in communication circuits. The input
impedance in a limiter for a ceramic filter at 455 kHz might be near to 1.5 kΩ or for
a ceramic filter at 10.7 MHz might be 300 Ω. As a result, the matching resistor in
Figure 6.5 is shown to be 300 Ω. Moreover, Figure 6.5 shows the offset cancellation
loop which extracts the undesired DC component at the output and returns a fraction
of it (ideally 1/A of it) with correct sign to the input. Another configuration for offset
cancellation is depicted in Figure 6.6.
Input capacitances in Figure 6.6 are AC short and the 50 Ω impedance at the load
of the error amplifier is for the matching purpose. Thus, the intrinsic output impedance
of the error amplifier must be negligible. However, due to finite output resistance of the
error amplifier, one may decrease 50 Ω resistance to attain a good matching. The loop
mechanism is such that the low-pass filter at the end of the circuit extracts the offset
error voltage and then the error amplifier amplifies the error voltage and returns it to
the input with the opposite polarity. This feedback continues till the DC offset error
reaches zero ideally. Another technique for offset cancellation is shown in Figure 6.7.
As Figure 6.7 shows, the input main amplifier has two differential inputs, the main
input and the auxiliary feedback ones. The error amplifier (A1 ) is placed for the sake
of offset cancellation. Note that the matching criteria is satisfied by 50 Ω brute-force
matching. There are two reasons that the structures shown in Figures 6.6 and 6.7
cannot completely remove the offset voltage. The first reason is the finite gain of the
error amplifier and the second one is their own offset voltages VOS1 for amplifier A1 .
We can easily develop a relation for the overall offset voltage in Figure 6.7 as
q s
0 VOS 2 + A1 2VOS1 2 VOS 2

VOS1 2

V OS = ≈ + (6.8)
AA1 + 1 AA1 A
where in Equation 6.8 offset voltages are considered as random functions with Gaussian
distribution and standard deviation of σ and those are also assumed to be independent.

(UURU
DPSOLILHU
5
$

5 & &
5 5
&
9,1 923
9,3 921
&

Figure 6.6: Offset cancellation loop with active negative feedback, where
R0 = 50 Ω.
6.3 Offset Compensation Circuits 263

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$

& &
5 5

& 923
9,1 921
9,3
&
5 5 $

Figure 6.7: Offset cancellation loop with negative active feedback and two
differential inputs, where R0 = 50 Ω.

An approximation for Equation 6.8 is valid for the condition of AA1 1. This is also
valid for Figure 6.6, if the gain of the differential input main amplifier is the same for
two paths. Note that the offset voltage of the main amplifier is decreased by the closed-
loop gain; however, unfortunately the offset voltage of error amplifier is just divided
by the main amplifier gain. These gains, however, are low-frequency gains. Thus, if
the offset voltage of the error amplifier is not negligible (i.e., VOS 1 VOS /A1 doesn’t
hold), this component will be dominant. While using high-speed error amplifiers are
not necessary for offset cancellation, we can use larger devices with good matching to
decrease their offset voltage. Finally, note that based on the degree of offset cancellation
needed, we might employ either high-gain error amplifier A1 > 1, or a buffer amplifier
A1 = 1, or a feedback loop without an amplifier.

6.3.1 Lower Cut-off Frequency of the Amplifier with

Offset Compensation Loop
In Figures 6.6 and 6.7, the feedback loop of offset cancellation might eliminate the
low-frequency components of the input signal. The transfer function for the negative
feedback amplifier depicted in Figure 6.7 can be written as
A (1 + R1C1 s)
H1 (s) = (6.9)
1 + AA1 + R1C1 s
The lower cut-off frequency for this amplifier becomes
1 + AA1
fco1 = (6.10)
2πR1C1
The transfer function for the input AC coupling response can be written as
R0Cs
H2 (s) = (6.11)
1 + R0Cs
264 Chapter 6. Limiters and Automatic Gain Control

The lower cut-off frequency for this transfer function becomes

1
fco2 = (6.12)
2πR0C

Obviously, the overall lower cut-off frequency of this amplifier would be the maximum
of fco1 and fco2 , or

1 + AA1 1
fLF = MAX , (6.13)
2πR1C1 2πR0C

Regarding the amplifier in Figure 6.6 as there is a voltage division at the output of the
error amplifier, A1 is replaced by A21 in Equation 6.10, and therefore, the lower cut-off
frequency in this amplifier becomes
( )
1 + AA2 1 1
fLF = MAX , (6.14)
2πR1C1 2πR0C

The above results suggest that for proper operation of the circuit, we should choose
1/ (2πR1C1 ) very lower than the required fLF . For instance, with a loop gain of 100,
and if we need a lower cut-off frequency of 250 kHz, then the loop bandwidth should
be lower than 2.5 kHz. It is possible to decrease the loop bandwidth by employing a
Miller capacitance in the feedback to obtain a large capacitance, as C1 = (A1 + 1)CF ,
at the input of the error amplifier (Figure 6.8). Like any feedback structure, we
need to examine the stability condition for both the differential and the common-mode
operation. Fortunately, regarding the open-loop gain, the dominant pole of the feedback
circuit is sufficiently near the origin and it is far from the dominant poles of the main
amplifier; as such, it doesn’t pose any challenge to the stability condition.

Cf

50Ω
A1

50Ω
R1 R1
C Cf
VIN VOP
VIP VON
C

Figure 6.8: Offset cancellation loop with negative feedback and use of a Miller
capacitance (instead of a large capacitance) in the feedback amplifier.
6.4 Automatic Gain Control 265

6.4 Automatic Gain Control

An amplifier which employs AGC is composed of a variable-gain amplifier alongside
a DC feedback loop proportional to the output to control the amplifier gain, both are
shown in Figure 6.9.
Similar to limiting amplifier circuits, AGCs are implemented as multistage am-
plifiers to achieve an optimum GBW product. Unlike limiters, here the gain of the
circuit is controlled via VAGC . The output signal amplitude is extracted by an amplitude
detector and the corresponding voltage, compared to a VREF , is applied to amplifiers to
control their gain. The speed and the stability of this loop are dependent on the cut-off
frequency of R −C low-pass filter of the feedback loop. For the sake of simplicity, we
assume VAGC is applied to all the amplifiers and it is assumed to have the same value
for all of them. However, in real applications, there might be some amplifiers to which
the control signal is not applied. In the following sections, we discuss the gain stages
and the detector circuit in detail.

6.4.1 Gain Control Methods

Single-stage gain can be controlled with different techniques. It is noteworthy that
while changing the gain of a single stage, it should not affect drastically other pa-
rameters such as bandwidth, input dynamic range, noise figure, and common-mode
rejection. Moreover, we expect the output to be linear (away from clipping) for the
lowest gain and the maximum input, and for highest gain, we expect the noise figure to
be minimum. In the subsequent sections, we introduce a number of popular techniques
to control the gain of an amplifier stage.

Changing the transconductance of a transistor

It can be generally said that the gain of a single-stage amplifier is equal to gm RL , thus
we can alter gm to change the value of the gain. One of the methods to change gm is
changing the value of the tail current source which is shown alongside a differential
pair in Figure 6.10.
It is possible to change the value of the tail current source to change the gm of
transistors. Unfortunately, changing the current source to a lower value results in the
change of the voltage drop across the load resistors and increases the common-mode

VIN VOP
VIP VON

VAGC

C R
VREF

Figure 6.9: Automatic gain control structure.

266 Chapter 6. Limiters and Automatic Gain Control

VDD VDD

R R R R
VON I0/2 I0/2 VOP VON VOP
VAGC
VIP VIN
VIP VIN

IAGC/2 I0±IAGC IAGC/2 I0

± ±

(a) ( b)

Figure 6.10: Variable-gain stage with gm variation, (a) Through tail current
variations, and (b) Through second gate voltage variations.

voltage. To solve this problem, we can add two current sources from the outputs to
the ground. By this modification, the current reduced from the load is injected again
to make the common-mode level constant. The constant current is selected to be I0 /2
for both loads. The main drawback of this circuit is the decrease in the output voltage
swing of the circuit for lower gains. Moreover, since the gain is decreased, from input
referred noise point of view, it may result in lower SNR. It can be asserted that with
this technique, the amplifier bandwidth will be constant. Another method to decrease
the gm of the transistor is to push it in a triode region, which in fact lowers its output
impedance and consequently its gain. This can be implemented by a cascode structure
shown in Figure 6.10(b). The gate voltage of the cascode device is controlled by VAGC .
The gain and the cascode devices can be implemented via a single structure MOSFET
as dual-gate. In this method where the current source is not changed, the common-
mode level stays unchanged. However, the input dynamic range will be decreased.
Moreover, this circuit can show an extreme nonlinear behavior for large-signal inputs.

Changing the load resistor

As stated earlier, the gain of an amplifier can be estimated as gm RL , thus another
parameter that can be modified to change the gain is the load resistor. Although
varying the load resistor itself alters the gain, this also changes the common-mode
voltage which is not of interest. This issue can be resolved by inserting a resistor
differentially. The resistor can be implemented by a MOS device which is biased in
the triode region. The circuit is shown in Figure 6.11(a) which has a constant input
dynamic range alongside proper noise behavior. The main drawback of this structure
is the increase in the bandwidth due to the decreased gain.

Changing the amount of feedback

Figure 6.11(b) depicts a variable-gain stage with series feedback. As this figure shows,
two current sources are tied to the sources of the transistors. Alternatively, we could
tie equivalently the current source (I0 ) to the middle of RAGC . The main advantage of
two current sources is eliminating the voltage drop on the emitter resistor. However,
6.4 Automatic Gain Control 267

VDD VDD

R R R R
VON VOP VON VOP
VIP VIN
VIP RAGC VIN

I0 I0/2 RAGC I0/2

(a) (b)

Figure 6.11: Variable-gain stage with (a) load resistor, and (b) series feedback.

one current source implementation has the merit of eliminating the common-mode
noise whose elimination is of interest. The feedback resistor can be implemented by a
MOSFET operation in the triode region. This structure has a loosely fixed bandwidth
and a fixed common-mode voltage. Interestingly, decreasing the gain results in an
increment in the input dynamic range. Moreover, the degeneration resistor (RAGC )
improves the linearity of the amplifier.

Switching between amplifiers

Figure 6.12 shows a structure that makes it possible to achieve different gains by
turning on and off the corresponding switches. This can be achieved by a digital
control circuit. This structure is indeed an amplifier bank whose gain is digitally
controlled depending on the amplifiers which are switched in. The switches can be
implemented using single-MOSFET structures.

s1 s′1
g1

s2 s′2
g2
Input Output

sn s′n
gn

Figure 6.12: Implementation of automatic gain control circuit using multiple

switches.
268 Chapter 6. Limiters and Automatic Gain Control

6.5 Amplitude Detectors

Figure 6.13 illustrates a peak detector which somehow rectifies the input signal.
When the input signal rises and reaches a value higher than the output (plus the
cut-in voltage of the diode), it turns on and charges the capacitor to the peak value with
a time constant equal to the diode on-resistance times the capacitance (T0 = rDC). The
current source I discharges the capacitor slowly when the diode is off. The values for
C and I must be chosen to provide proper system time constant and proper voltage
drop across the load. This time constant can be evaluated as
VDC,out
τ0 = C (6.15)
I
Note, we should have τ0 1/ω0 . Otherwise, one can put a proper load resistance
instead of the current source constituting a sufficiently large RC time constant with
respect to the inverse of the carrier frequency (RC 1/ω0 ). However, this structure
can detect only the positive peaks of the signal and for detecting the negative peaks, we
need a modified version. To have half a discharge time and consequently less ripple,
one can consider a full-wave rectifier for this purpose. The full-wave rectifier is shown
in Figure 6.13(b). Here, the in-phase and the out-of-phase components of the input
signal are applied to the anodes of the two diodes. As such, despite the previous circuit,
this circuit’s operation is such that as if we use the absolute value of the signal at the
input. This input signal can be implemented differentially and with the assumption of
ideal diodes, the output voltage will be equal to the peak value of the input voltage.
The large capacitance at the output roughly filters out the ripples of the output signal.
One can observe that this circuit somehow solves the problem of output ripple. Note
that this circuit for proper operation needs a relatively large input signal amplitude,
that is, with an AM signal, one should have the following condition (to avoid distortion
in the detector).
4VD
VC ≥ (6.16)
1−m

VI VI VIP
VO VO

C I C I

VIN

VI VIN VIP VO
VO
VD VD

t t

(a) (b)

Figure 6.13: (a) Single-ended peak detector and (b) Full-wave peak detector.
6.5 Amplitude Detectors 269

9&& 9&&
9, 9,3

9%%
4
4
9, 4 4 4 4
9,1
92
92
/RZ
& ,( EOHHGLQJ &
FXUUHQW

D E

Figure 6.14: The implementation of a peak detector, (a) single-ended peak

detector, and (b) full-wave peak detector.

where VC is the carrier amplitude, VD is the diode cut-in voltage, and m is the mod-
ulation index. Using differential pair transistors, one can detect AM signals with an
amplitude less than VD (why?). The implementation of these peak detectors is shown
in Figure 6.14. In Figure 6.14(a), given the differential pair amplifier, one can detect
small-signal AM inputs, while in Figure 6.14(b), full-wave detection is realized. In
these two implementations, again a constant bleeding current is employed across the
charging capacitor for AM detection. Care must be taken that in these two circuits
a DC bias voltage is required at the input. Furthermore, in Figure 6.14(a), the input
bias should have approximately the same value as the output DC voltage, and the DC
bias of the base of the Q3 should be approximately 2VD +VDC,O . The discharge time
constant of the AM detection in this circuit is approximately
βVC
τ0 = C (6.17)
IE
where β is the current gain of Q4 and VC is the carrier voltage amplitude.
In the AM detector circuit depicted in Figure 6.14(b), a bias voltage larger than VD
is required at the input and the discharging time constant at the output is approximately
τ0 = C VIC , where VC is the carrier voltage amplitude. As mentioned earlier, the
advantage of these circuits with respect to the circuits of the Figure 6.13 is that both
of them can operate with an AC input signal voltage amplitude of a fraction of VD .
Note that the input differential signals should have a low offset voltage to operate
properly.

6.5.1 Logarithmic Signal Level Indicator

In this section, we introduce a structure to investigate the level of the signal passing
through the receiver chain of amplifiers. This is a common circuit that records the
signal strength, for example, in a common mobile phone receiver. Consider cascaded
amplifiers along with the corresponding amplitude detectors shown in Figure 6.15.
As the signal is amplified through the chain of cascaded amplifiers, the first detector
detects the highest levels of the signal and the last detector indicates the lowest levels
of the signal. The structure as a whole functions like a normal limiter.
270 Chapter 6. Limiters and Automatic Gain Control

9,1 923
9,3 921

9&& 9&& 9&& 9&&

'HW 'HW 'HW 'HW

4 4 4 4 4 4 4 4

, & , & , & , &

5HFHLYHGVLJQDOVWUHQJWKLQGLFDWRU566,

2XWSXWVLJQDO

Figure 6.15: The configuration of a signal strength indicator.

RSSI
(dB Volts)

Signal stage
gain in dB

RF (dBm)

Det4 Det3 Det2 Det1

Figure 6.16: Typical indicator output as a function of the input RF power.

Figure 6.16 shows the typical output of the indicator versus the input RF power.
As Figure 6.16 suggests, for low-power input signals, merely the final stages sense the
power; however, when the input signal increases, the initial stages sense the power
as well.

6.6 Amplifier Circuit with Gain Control Based on Analog

Multipliers
Figures 6.17 and 6.18 show the structure of an amplifier with variable gain which is
applicable in AGC circuit. In Figure 6.17, the signal is differentially applied to one
port and the control signal is applied to the other port of the Gilbert cell. It is also
possible to change the tail current source value to change the transconductance of the
6.6 Amplifier Circuit with Gain Control Based on Analog Multipliers 271

VCC

RF RF

QA QB QB′ QA′
VAGC

VIP Q1 Q′1 VIN

CE

RE RE

I0

Figure 6.17: Amplifier implementation with gain control based on a multiplier.

VCC

RF RF

VIP Q11 Q12 ′

Q12 ′
Q11
CE1 CE1
VIN

RE1 RE1 RE1 RE1

QA Q′A
VAGC RE RE

I0

Figure 6.18: Modified amplifier with gain control based on a multiplier.

stage; interestingly due to crossing of the outputs in the Gilbert cell, the common mode
is eliminated. If the control voltage VAGC is high, the currents of transistors Q1 and Q01
flow through the transistors QA and Q0A and a gain of A = RF /RE is obtained. However,
if the control voltage is small, the output current will tend to have small values and the
Gilbert cell output will tend to be zero and a very small gain will be observed. In a
special case where VAGC = 0, the currents totally cancel out each other and a zero gain
is obtained by the assumption of a complete match between the upper tree transistors.
In this circuit, the degeneration resistors RE are used to decrease the low-frequency
gain and increase the dynamic range through the lower tree. The capacitor CE is used
to bypass the degeneration resistors at high frequency and consequently increase the
gain at higher frequencies. The whole scenario is described by Equation 6.18.
272 Chapter 6. Limiters and Automatic Gain Control

vin vAGC


 tanh f fcutoff
R
E 2VT
∆IEE = (6.18)
 vin vAGC
 I0 tanh
 tanh f > fcutoff
2VT 2VT

where fcutoff = 1/4πRECE . Note that vout = ∆IEE RF .

In Figure 6.18, another circuit is proposed for the variable-gain stage. In this
structure, however, the control signal is applied to the lower tree and the differential
signal is applied to the upper tree of the Gilbert cell. Again, in this structure, the
degeneration resistors, RE1 , are bypassed by the capacitors, CE1 , so that the upper
tree stages will have a high-pass behavior. When the control voltage is decreased, the
current flows in both branches and it results in the lowering of the transconductance
and correspondingly the gain of the circuit is reduced. The above discussion is well
described in the following relations:
 vAGC vin
f fcutoff
 RE RE1 I0


2
∆IEE = (6.19)
v vin
 AGC tanh

 f > fcutoff
RE 2VT

where fcutoff = 1/4πRE1CE1 . Note that vout = ∆IEE RF .

Another implementation of the circuit is shown in Figure 6.19. In this implemen-
tation, no degeneration resistors are used and while the gain is high, the input dynamic
range is limited. Because the upper tree will be easily saturated with large input signals.
Furthermore, the gain control will be achieved by a larger gradient. Here, we have

vAGC vin
∆IEE = I0 tanh tanh (6.20)
2VT 2VT

9''

5 5

9,1 4 4 9,3 9,1 4 4 9,3

4 4
$*&
FRQWURO

Figure 6.19: Automatic gain control circuit without degeneration resistors

(without the high-pass response).
6.7 Increasing Bandwidth Methods 273

6.7 Increasing Bandwidth Methods

Although multistage amplifiers improve GBW product, we look for high-speed ampli-
fiers or devices with large unity current gain frequency. In the following, we propose
structures which can be used or combined to increase the bandwidth.

6.7.1 Employing High-Speed Transistors

To achieve high-speed stages, the optimum quiescent point and vital transistor topology
should be considered. The parameter which shows the maximum operating frequency
of a device which corresponds to unity current gain is defined by fT . Another param-
eter which denotes for unity power gain is fmax . For a bipolar transistor, fT can be
computed as

1 gm
fT = (6.21)
2π Cbe +Cbc

where in Equation 6.21, gm is the device transconductance, Cbe is the base–emitter

capacitance, and Cbc is the base–collector capacitance. The maximum oscillation
frequency ( fmax ) for a bipolar transistor then can be obtained as
r
1 fT
fmax = (6.22)
2 2πRbCbc

where in Equation 6.22, Rb is the intrinsic base resistance. With respect to

Equation 6.22, to achieve high-speed operation, we should decrease Rb and Cbc .
Similarly, unity current gain frequency for a MOSFET device can be written as

1 gm 3 µn
fT = ≈ (VGS −VTH ) (6.23)
2π Cgs +Cgd 4π L2

where in Equation 6.23, Cgs is the gate–source capacitance, Cgd is the gate–drain
capacitance, µn is the electron mobility, and L is the gate length. For high-speed
operation, NMOS transistors are preferred due to their better mobility. Moreover, the
shorter the length of the device channel and the higher the overdrive voltage the higher
unity current gain frequency, fT , would be obtained. We can also write the maximum
oscillation frequency of a MOS device as
s
1 fT
fmax = (6.24)
2 2πRgCgd

where in Equation 6.24, Rg is the gate resistance. In this equation, we have neglected
the effect of output resistance of the device due to channel length modulation. To
increase the maximum frequency of the transistor, we should increase fT and decrease
Rg and Cgd .
274 Chapter 6. Limiters and Automatic Gain Control

6.7.2 Increasing Unity Current Gain Frequency

The unity current gain frequency ( fT ) is inversely proportional to the carrier transit
time in the channel, that is, the carrier transient time. For a bipolar transistor, the
transit time with neglecting parasitic capacitances at the emitter and the collector is
τF = 1/ (2π fT ). The same phenomenon holds for a MOS device. Thus, to achieve
high-speed operation, we need short gate length devices with small access resistances
to the gate and to the source. In the following, we deal with the circuit-level methods
to increase the unity current gain frequency. As stated before, one can realize that this
parameter is loosely proportional to the device transconductance divided by its input
capacitance. Therefore, if one decreases the input capacitance while maintaining the
transconductance as unchanged, the higher-speed operation will be achieved. A fT
doubler circuit is shown in Figure 6.20.
In this circuit, the input signal is divided between transistors Q1 and Q3 . Since
half of the input voltage drops on the base–emitter junction of Q1 and the other half
drops on the base–emitter junction of Q3 , the collector current will not change and
the transconductance stays the same (the collector currents of Q1 and Q2 are added
with half-input voltages), while the input capacitance will be halved due to series
connection of Q1 and Q3 and in fact the unity current gain frequency will be multiplied
by 2. Figure 6.20 also shows a differential implementation of fT doubler. In this
topology, the input voltage is divided between nodes B and B0 in a manner that the
overall transconductance remains unchanged (because the collector currents are added).
However, the input capacitance is halved due to series connection of the two differential
stages. In practice, however, these circuits are not ideal due to parasitic capacitances
which also impose a finite phase shift and result in imperfection. Moreover, the base–
collector capacitance is not further reflected to the input through the Miller effect.
Another drawback of this structure arises from the fact that the collector–substrate
capacitance is doubled. This may adversely affect the improvement in fT doubler.
Moreover, it consumes twice the power of a single circuit.

6.7.3 Inductive Load (Shunt Peaking)

Consider Figure 6.21 which shows a common-source amplifier with inductive load
alongside a resistor.

JP9LQ & &഻

&

% 4 JP9LQ

9LQ

4 % %഻
9LQ 9LQ

4 9&0
9LQ 9LQ
9LQ
( (
D E

Figure 6.20: fT doubler, (a) single-ended, and (b) differential implementation.

6.7 Increasing Bandwidth Methods 275

VDD
VO/Vi
L L=RLCL
2

2
gmRL L=0.4RLCL
√2 gmRL L=0
R 2 BW

Vi VO
1.7×BW
f

Figure 6.21: Inductive peaking in the common-source amplifier with the

corresponding frequency response.

The inserted inductor is for canceling out the effect of the output capacitance. This
technique is called inductive peaking because it results in a peaking in the frequency
response of the output voltage. For instance, by choosing the value of the inductor as
L = 0.4R2CL , the bandwidth will be increased by 70% with respect to the pure resistive
0
load, i.e., BW = 1.7 BW. The optimum value of the inductor from the bandwidth
point of view doesn’t lead to peaking indeed; however, inductive peaking alleviates the
negative effect of multistage amplifiers in terms of bandwidth. It can be shown that by
increasing the value of the inductor, the bandwidth will be increased and eventually
reaches to its optimum point. If we continue to increase the inductor value, we will
not attain the required bandwidth efficiency anymore and a peaking in the response
will occur which makes the response nonflat. Regarding the inductor model itself and
its self-resonance frequency, as a rule of thumb, the inductor should be chosen such
that its self-resonance frequency is at least twice the cut-off frequency of the amplifier.
Moreover, it is possible to replace the bulky spiral on-chip inductor with its active
counterpart, however, at the cost of higher noise. Figure 6.22 shows the inductor model
with its active counterpart.
Given the equivalent circuit model in Figure 6.22(b), the admittance of the active
inductance circuit can be written as

gm + jCg ω
I =V (6.25)
1 + jRgCg ω

L RS Rg
Rg Rg/ωT
2CP 2CP
= + gmVgs =
Cg Vgs
- 1/gm

(a) (b)

Figure 6.22: (a) Passive (spiral) inductor model. (b) The active MOS inductor
topology and its equivalent circuit.
276 Chapter 6. Limiters and Automatic Gain Control

where Cg is the gate–source capacitance, and gm is the MOSFET’s transconductance.

For
1
Rg (6.26)
Cg ω
or

RgCg ω 1 (6.27)

The total admittance can be simplified to

gm gm
Y= 2 − j (6.28)
RgCg ω RgCg ω

and finally the total impedance can be simplified to

1 RgCg ω 1 Rg
Z= +j = +j ω (6.29)
gm gm gm ωT

which is evidently the description of an inductance in series with a resistance as shown

in Figure 6.22(b).

6.7.4 Decreasing Input Capacitance by Series Feedback

One of the main drawbacks in bipolar transistors is their speed issue which is due to
their input pole made up of intrinsic base resistance and the base–emitter capacitance.
For the sake of simplicity, we now neglect the effect of base–collector capacitance,
i.e., assume Cbc ≈ 0. We know that in bipolar transistors, the carrier injection in
base is low, and thus this may result in higher intrinsic resistance and consequently
lower input pole frequency. One may write the base–emitter capacitance from Cbe =
Cje +(IC /VT )·τF . Note that the base–emitter capacitance is proportional to the collector
current and will be increased linearly with the collector current. As an example,
suppose a bipolar transistor of Rb = 120 Ω, Cbe = 170 fF, gm = 40 mS, and fT = 30 GHz
which is operating at IC = 1 mA. In this case, the low-pass response of the base–emitter
input will have a 3 dB cut-off frequency of 7.8 GHz which is much lower than the unity
current gain frequency of the device. One of the well-known techniques to resolve this
issue is to insert a degeneration resistor at the transistor’s emitter as a series feedback
which is shown in Figure 6.23.
Due to series feedback, the emitter will follow the base voltage, and therefore
the equivalent capacitance seen from the base will be decreased. This phenomenon
pushes the input pole farther from the origin. Here, in a similar way to the fT doubler
circuit, the Miller effect decreases the input capacitance; however, due to lowering the
transconductance, no improvement in unity current gain frequency is achieved. It can be
shown that with neglecting the base intrinsic resistance and the output conductance of
the transistor, the gain from the base to the emitter can be written as gm RE / (1 + gm RE ).
Therefore, regarding the Miller effect, the equivalent capacitance can be computed as
Ceq = Cbe (1 − A), and we can write Ceq = Cbe / (1 + gm RE ), which results in pushing
the input pole farther by a 1 + gm RE factor. Interestingly, this will result in lowering
the capacitance seen from the previous stage which finally results in increasing its
6.8 Oscillation in Limiting Stages 277

RC RC

Rb Rb

Cin Cin
Cbe Cbe

BJT BJT
RE CE

(a) (b)

Figure 6.23: Decreasing device input capacitance via series feedback.

bandwidth. The side effect of series feedback is lowering the low-frequency gain
of the amplifier by a 1 + gm RE factor. However, it is possible to increase the load
resistance proportionally to maintain the gain of the amplifier as unchanged. However,
this may result in lowering the output pole frequency due to larger resistance of the
load along with parasitic capacitances. If this pole is not compensated, this would
lead to decrease in the amplifier bandwidth. It is instructive to note that if we choose
CE = 1/ (2π fT · RE ), the emitter capacitance produces a zero in the frequency response
which neutralizes the pole in the response and maintains the amplifier bandwidth. For
example, by insertion of a resistor RE = 100 Ω and a transconductance of 40 mS, the
input capacitance will be lowered by a factor of 5 and we obtain Cin = 34 fF which
results in a cut-off frequency of 39 GHz for the input low-pass response which is
higher than the unity current gain frequency. Now, to maintain the gain, we should
multiply the output resistance by 5, and to neutralize the high-frequency pole of the
emitter, we choose CE = 50 fF. It is possible to increase the emitter capacitance to
achieve more bandwidth which is called emitter peaking. The degeneration resistor
has a lot of advantages, in addition to lowering the input capacitance and increasing
the circuit bandwidth by moving the input pole farther, which are (1) precise gain
control with the ratio of resistors as A = − (RC /RE ) with the criteria of RE 1/gm ,
(2) increasing the input resistance, (3) improving the circuit linearity for large-signal
input, and (4) increasing the dynamic range for a differential stage. In the MOS design,
this issue is not of great concern due to the low intrinsic gate resistance provided by
a proper layout. However, in a similar way to bipolar devices, this resistor can be
employed for the gain control, the amplifier linearity, decreasing the input capacitance,
and increasing the bandwidth with peaking in the source.

6.8 Oscillation in Limiting Stages

In an amplifier, the amplified signal can leak from the supply voltage line, the ground,
the substrate, and the radiation through the air. For instance, with an assumption of
80 dB loss in the leakage and a signal amplitude of 200 mv at the output, the returned
278 Chapter 6. Limiters and Automatic Gain Control

300Ω

300Ω 0.1μF 0.1μF

20kΩ 20kΩ
Supply voltage line
C
VIN VOP
VIP VON
C
Ground line

Figure 6.24: The possible feedback leakage path and the oscillation issue in
multistage amplifiers.

signal to the input will have an amplitude of 20 µv. Thus, for the signals that have an
amplitude greater than 20 µv, the input signal captures the limiting amplifier circuit;
however, if this signal is less than the mentioned value, the returned signal captures
the circuit itself. Most of designers assume this issue is due to poor noise figure;
however, this may happen due to improper layout that worsens the feedback leakage
phenomenon. Furthermore, if the total gain of the amplifiers chain is greater than
80 dB, there would be a possibility of oscillation (if the feedback phase is constructive).
Figure 6.24 illustrates this issue. As it is seen here, there is a possibility of feedback
leakage through either the supply voltage line or the ground line to the input. This
regenerative feedback is one of the pitfalls of designing a limiting stage and thus proper
layout and isolation must be taken into account.

6.9 Conclusion
In this chapter, we discussed different types of limiter circuits. The limiter circuit is a
nonlinear circuit which has a high gain for a limited range of the input signal. When the
signal starts to become large, this circuit limits the signal amplitude to an upper value.
DC offset voltage is another intricate problem in an electronic circuit design. Since the
limiters provide a high gain, offset cancellation techniques are required. We discussed
different types of offset cancellation loops in this chapter. Limiter circuits are used
in FM applications to remove the unwanted amplitude modulation. The AGC in an
amplifier chain is another method to increase the dynamic range of the receiver. The
AGC control loop mainly consists of an amplitude detector plus a negative feedback
bias loop. Furthermore, analog multiplier circuits can be devised in such a way that
it realizes the AGC. The problem of bandwidth enhancement in the RF/IF amplifiers
was presented in this chapter as well. Different techniques were presented in this
6.10 References and Further Reading 279

regard, including fT doubling, inductive peaking, and input capacitance reduction. The
problem of signal leakage and the oscillations due to the feedback path was discussed
as well.

6.10 References and Further Reading

1. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
2. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog
Integrated Circuits, fifth edition, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
3. J.P. Alegre Pérez, S. Celma Pueyo, B. Calvo López, Automatic Gain Control:
Techniques and Architectures for RF Receivers, New York, NY: Springer, 2011.
4. R. Wu, J.H. Huijsing, K.A.A Makinwa, Precision Instrumentation Amplifiers
and Read-Out Integrated Circuits, New York, NY: Springer, 2013.
5. J.R. Smith, Modern Communication Circuits, second edition, New York, NY:
McGraw Hill, 1997.
6. B.Razavi, Design of Integrated Circuit for Optical communications , second
edition, Hoboken, NJ: J. Wiley & Sons, Inc., 2012.
7. J.F. Witte, K.A.A. Makinwa, J.H. Huijsing, Dynamic Offset Compensated
CMOS Amplifiers, New York, NY: Springer, 2009.
8. J. Dostal, Operational Amplifiers, second edition, Stoneham, MA: Butterworth-
Heinemann, 1993.
III
Part 3

7 Transmission Lines and Impedance Matching 283

7.1 An Introduction to Radio-Frequency Amplifiers in
Receivers
7.2 Wave propagation Equations in Transmission Line for R = 0
and G = 0
7.3 Characteristic Impedance of a Line
7.4 Terminated Transmission Lines
7.5 Special Cases of a Terminated Line
7.6 Source and Load Mismatch in Lossless Lines (A Reflection
Coefficient Perspective)
7.7 Impedance Transformer Based on λ /4 line (Impedance
Inverter)
7.8 Voltage Standing Wave Ratio
7.9 Impedance Matching: The L-Section Approach
7.10 Smith Chart Mapping
7.11 Conclusion
7.12 References and Further Reading
7.13 Problems

8 Scattering Parameters . . . . . . . . . . . . . . 349

8.1 Representation of Two-Port Networks
8.2 Measuring S-Parameters Using a Network Analyzer (For
Advanced Readers)
8.3 Conversion of Network Matrices
8.4 Conclusion
8.5 References and Further Reading
8.6 Problems

9 Amplifier Design Using S-parameters . . . . . 377

9.1 Amplifier Design Using Scattering Parameters
9.2 Specification of Amplifiers
9.3 Performance Parameters of an Amplifier
9.4 Power Gain Contours
9.5 Noise Behavior of a Two-Port Network
9.6 Constant Noise Figure Contours
9.7 Design of a Single-Stage Low-Noise Amplifier
9.8 Design of Two-Stage Amplifiers
9.9 Conclusion
9.10 References and Further Reading
9.11 Problems

10 Power Amplifier . . . . . . . . . . . . . . . . . . 425

10.1 PA Specification
10.2 PA Topologies
10.3 Linearization Techniques in Power Amplifiers
10.4 Conclusion
10.5 References and Further Reading
10.6 Problems
7. Transmission Lines and Impedance Matching

Transmission lines (T-lines) bridge the gap between the field and wave analysis,
on the one hand, and circuit analysis on the other. This makes transmission line
theory an integral part in understanding microwave and mm-Wave devices and circuits.
As it will be seen throughout this chapter, wave propagation through the T-lines
can be formulated by extending the circuit theory basics and making use of some
specific solutions of the Maxwell equations. In this chapter, we provide a profound
understanding of circuit equations governing T-lines using differential equations. The
readers are encouraged to refer to Ref. [1] for a more comprehensive account of the
microwave theory. T-lines play a very important role in modern wireless circuits and
systems which find applications in antenna interfacing to TRX, impedance matching
in mixers and amplifiers, resonator in oscillators and filters, etc.

7.1 An Introduction to Radio-Frequency Amplifiers in Receivers

Low-noise amplifiers (LNAs) are one of the most challenging constituents of a high-
frequency receiver. Consider Figure 7.1, in which, the high-frequency signal is received
by an LNA and passed on to the next building blocks. This suggests that the overall
noise and sensitivity behavior of the receiver tightly depends on the LNA. In RF com-
munication circuits, building blocks are designed to be matched to a 50 Ω impedance,
both at the input and the output.
Given the fact that the impedances of RF devices, antennas, and passive and
active components mostly vary between a value of few ohms to few hundreds, a
commensurate value of 50 Ω has been chosen as the reference impedance for RF
circuits. As such, matching RF devices to the value of 50 Ω would be feasible in
most of the cases. Matching to 50 Ω is therefore necessary to obtain the maximum
power transfer. We discuss later that this matching comes at certain circumstances
at the price area occupation in RF integrated circuits. Another problematic issue in
high-frequency amplifiers is oscillation. As the frequency increases, parasitic elements,
284 Chapter 7. Transmission Lines and Impedance Matching

/1$

'HPRGXODWRU

)UHTXHQF\
V\QWKHVL]HU

Figure 7.1: A generic RF front-end.

namely, capacitors and inductors, tend to have a larger effect, the likelihood of a
positive feedback also increases. For example, consider Figure 7.2, where the model
of a high-frequency amplifier is depicted. As it is seen in Figure 7.2, the matching
circuit elements could be set such that the impedance seen from the antenna and that
of the load are both equal to 50 Ω. It is possible that the circuit could oscillate because
of the existence of parasitic Cgd or Ls , both of which may cause unexpected feedback
at higher frequencies.

7.1.1 Transmission Line

It is not hard to imagine that wires (interconnects) against the ground could be modeled
as a sequential combination of inductive and capacitive components. On the other
hand, there should also be a physical means of sending a signal to a transistor, and then
extracting it out to the next stage. A lossless T-line, in principle, delivers the signal
to the load unattenuated, while introducing an associated propagation delay. Besides
the signal transmission, the main application of T-lines is in impedance matching.
However, T-lines introduce both uncharacterized distortion and delay. Figure 7.3
depicts the phase and amplitude response of a typical T-line.
As it is obvious from Figure 7.3, the gain of an ideal T-line is equal to unity and
it exhibits a linear phase behavior (constant delay behavior). The gain of a nonideal

/J &JG UG

ȍ & &JV YJV UR & ȍ

JPYJV
/ /
& & ȍ
U6

/6

,QSXW 7UDQVLVWRU 2XWSXW

PDWFKLQJ PRGHO PDWFKLQJ

Figure 7.2: The model of a high-frequency amplifier.

7.1 An Introduction to Radio-Frequency Amplifiers in Receivers 285

*DLQRID
7/LQH

I

,GHDO7/LQH
3KDVHRID
1RQLGHDO7/LQH
7/LQH

ž I

ž

Figure 7.3: The phase and gain response of a lossless T-line.

T-line falls with frequency, furthermore its phase changes in a nonlinear manner
with frequency, and therefore it has a variable delay with frequency which causes
phase distortion (or dispersion). Furthermore, a characteristic impedance is defined
for a T-line. As the operating frequency increases, the circuit dimensions become
comparable to the carrier wavelength, the wave behavior of the electromagnetic waves
should be taken into consideration rather than using the lumped element KVL and
KCL relations. As suggested by the maximum power transfer theorem, in the case of
matched terminations, the signal will be completely absorbed by the load. However, as
we will see shortly, if the circuit suffers from a nonzero reflection coefficient, a portion
of the signal, and hence the power, is reflected back.

Capacitor Inductor
50Ω

L L

50Ω 50Ω
L 50Ω L 10Ω

(a) (b)
Open
circuit Z02/ZL
L=λ/4 L=λ/4

50Ω 50Ω
L=λ/4 ZL
L=λ/4

(c) (d)

Figure 7.4: Impedance transformation property of the T-line, (a) The line
terminated by 50 Ω exhibits an impedance of 50 Ω throughout the line, (b) The
line terminated by an unmatched load can exhibit both an inductive or capacitive
impedance seen through it depending on the position, (c) Transformation of a
short circuit to an open circuit using a quarter wavelength T-line, and (d) Load
impedance inversion using a quarter wavelength T-line.
286 Chapter 7. Transmission Lines and Impedance Matching

I(z,t) I(z+∆ z,t)

R ∆Z L ∆Z

V(z,t) G ∆Z C ∆Z V(z+∆ z,t)

Figure 7.5: The lumped model of a differential transmission line for a differen-
tial length ∆Z.

Another important property of T-lines is impedance transformation. Figure 7.4

elaborates on this property. In case (a), the impedance is equal to 50 Ω regardless of
the position throughout the line. For case (b), however, the impedance seen through
the line can be either capacitive or inductive, depending on the position. Interestingly,
in case (c), the T-line can transform a short circuit to an open circuit, for the quarter
wavelength, and T-line in case (d) operates as an impedance transformer (impedance
inverter).
The principal difference between the standard circuit theory and microwave circuit
theory lies within the electrical size of the circuits and devices. Recall from circuit the-
ory that a circuit can be viewed as a lumped one if the physical length is smaller than
the wavelength of the operating signal. This allows us to conclude that the voltages
and currents do not alter through a conductive wire according to the position. However,
in microwave circuits, circuit size can be as large as the wavelength or even larger,
which calls for a new perspective into design and analysis of such circuits. To begin
with, consider the lumped model of a differential TEM T-line depicted in Figure 7.5.

7.2 Wave propagation Equations in Transmission Line

for R = 0 and G = 0
As illustrated in Figure 7.5, a T-line is generally made up of two conductors. In
electromagnetic wave theory, it is proved that this kind of structure can support
(transmit) a TEM wave. A TEM wave is the one in which both the electric field and
the magnetic field are perpendicular to the direction of the wave propagation. Most of
the transmission lines used in the modern electronic circuits are of TEM type. This
type of transmission line can be modeled with a distributed cells of series R and L
alongside parallel G and C. We consider the transmission line model as depicted in
Figure 7.5 consists of a series resistance per unit length R, a series inductance per unit
length L, a parallel conductance per unit length G, and a parallel capacitance per unit
length C. It can be observed that for a tiny fraction of the length, the circuit is lumped,
and hence, KVL and KCL are still valid. It follows that the voltage and the current can
be written as
∂ i(z,t)
v(z,t) = L∆z + v(z + ∆z,t) (7.1)
∂t
and
∂ v(z + ∆z,t)
i(z,t) = i(z + ∆z,t) +C∆z (7.2)
∂t
7.2 Wave propagation Equations in Transmission Line for R = 0 and G = 0 287

respectively. Equations 7.1 and 7.2 can be rewritten as

v(z + ∆z,t) − v(z,t) ∂ i(z,t)
= −L (7.3)
∆z ∂t
and
i(z + ∆z,t) − i(z,t) ∂ v(z + ∆z,t)
= −C (7.4)
∆z ∂t
respectively. The length of the line can approach to zero in order to comply with our
lumped treatment of the circuit. Therefore, Equations 7.3 and 7.4 can be written in
differential form as
∂v ∂i
= −L (7.5)
∂z ∂t
and
∂i ∂v
= −C (7.6)
∂z ∂t
respectively. These time-domain equations are famously known as the telegraphic
equations. To arrive at a unified solution, partial derivative with respect to position is
taken from Equation 7.5, which yields

∂ 2v

∂ ∂i
= −L (7.7)
∂ z2 ∂ z ∂t
Changing the order of differentiation in Equation 7.7 and using Equation 7.6, we obtain

∂ 2v ∂ 2v
= LC (7.8)
∂ z2 ∂t 2
which corresponds to

∂ 2v
2
∂ v
2
− LC =0 (7.9)
∂z ∂t 2
This is a simple one-dimensional wave equation for the voltage on the line. It is left to
the reader to find a similar equation for the current. Now, for the sake of simplicity,
we assume that the input RF voltage is sinusoidal, having a phasor representation of
v(z,t) = Re{V (z)ejωt }. It follows that

d 2V
− LC(−ω 2 )V = 0 (7.10)
dz2
which can be rewritten as
d 2V
= − ω 2 LC V

(7.11)
dz2
288 Chapter 7. Transmission Lines and Impedance Matching

Defining Z = jωL and Y = jωC, Equation 7.11 can be rewritten as

d 2V
= (ZY )V (7.12)
dz2
Let’s define γ 2 = ZY , where γ is the propagation constant, and then find the solution to
Equation 7.12 as
V (z) = Ae−γz + Be+γz (7.13)
The constants in Equation 7.13 can be found using the initial conditions. The first term
to the left represents the wave prorogating in the positive direction of the z-axis, and
the second term to the left represents the wave prorogating in the negative direction of
the z-axis. Therefore, a more meaningful representation of Equation 7.13 would look
like
V (z) = V0 + e−γz +V0 − Be+γz (7.14)
where, the propagation constant, γ is given by
p √
γ = jβ = ( jωL)( jωC) = jω LC (7.15)
One can observe from Equation 7.15 that γ is frequency dependent. Now, to obtain
the current wave, we substitute V (z) from Equation 7.13 in Equation 7.5, and hence
obtain
jβ + −jβ z 1 + −jβ z
I(z) = V0 e −V0 − e+jβ z = V0 e −V0− e+jβ z (7.16)
jωL Z0
where
r
ωL L
Z0 = = (7.17)
β C
Here, Z0 is the transmission line’s characteristic impedance. This impedance always
shows the quotient of incident voltage to incident current or the quotient of reflected
voltage to reflected current traveling along the transmission line. The voltage traveling
wave equation can be easily obtained by assuming V0 + = |V0 + | ∠φ and arriving at
v+ (z,t) = V0 + cos(ωt − β z + φ + )

(7.18)
The same equation as that derived in Equation 7.18 can also be obtained for the
reflected wave, by means of which the total voltage waveform is given by
v(z,t) = V0 + cos(ωt − β z + φ + ) + V0 − cos(ωt + β z + φ − )

(7.19)
Now, we introduce two new quantities. The distance between two successive planes in
z-direction having the same phase is defined as the wavelength, that is, β (z2 − z1 ) = 2π,
where z2 = z1 + λ and therefore
2π
λ= (7.20)
β
7.2 Wave propagation Equations in Transmission Line for R = 0 and G = 0 289

The wave’s phase velocity is also defined assuming ωt − β z = cte as velocity with
which a specific point on the wave front travels. That is
dz ω 2π f
υp = = = 2π = λ f (7.21)
dt β λ

In other words, the phase velocity can be written as

ω ω 1
υp = = √ =√ (7.22)
β ω LC LC
To grasp a better understanding of the meaning of the phase velocity, note that this
quantity describes the speed with which the plane of constant phase travel in the space.
This velocity in air-filled cables and transmission lines is the same as the velocity of
light, while for those cables filled with other dielectric materials, it is the speed of light
divided by the square root of the relative permittivity.

7.2.1 General Wave Propagation Relations in lossy Transmission Lines

For a lossy transmission line (R 6= 0 and G 6= 0) as depicted in Figure 7.6, a two-wire
representation for a T-line can be thought of two conductors separated by a dielectric
and excited by a source with a Thevenin voltage, VTH , and the Thevenin impedance,
ZTH . As stated earlier, it can be shown that for a tiny fraction of the wire, the circuit
can be assumed to be lumped, and therefore, KVL and KCL still hold. It therefore
follows that
∂ i(z,t)
v(z,t) = R∆z × i(z,t) + L∆z + v(z + ∆z,t) (7.23)
∂t
and
∂ v(z + ∆z,t)
i(z,t) = i(z + ∆z,t) + G∆z × v(z + ∆z,t) +C∆z (7.24)
∂t
Equations 7.23 and 7.24 can be rewritten as

v(z + ∆z,t) − v(z,t) ∂ i(z,t)

= −Ri(z,t) − L (7.25)
∆z ∂t
and
i(z + ∆z,t) − i(z,t) ∂ v(z + ∆z,t)
= −Gv(z + ∆z,t) −C (7.26)
∆z ∂t

I(z,t) I(z+∆ z,t)

R ∆Z L ∆Z
ZTH
+
VTH V(z,t) G ∆Z C ∆Z V(z+∆ z,t) ZL
-

Figure 7.6: A transmission line divided into consecutive differential lumped

sections.
290 Chapter 7. Transmission Lines and Impedance Matching

As the length of the sample line approaches zero, differential forms for Equations 7.25
and 7.26 are obtained as
∂v ∂i
= −Ri − L (7.27)
∂z ∂t
and
∂i ∂v
= − Gv −C (7.28)
∂z ∂t
Now taking a derivative of Equation 7.27, we obtain

∂ 2v

∂i ∂ ∂i
= −R − L (7.29)
∂ z2 ∂z ∂ z ∂t

By changing the order of derivation and using Equation 7.28, we arrive at

∂ 2v ∂ 2v

∂v ∂v
= −R −Gv −C − L −G −C (7.30)
∂ z2 ∂t ∂t ∂t 2

The overall differential equation for the voltage is given by

∂ 2v
2
∂v ∂ v
− (RG) v − (RC + LG) − LC =0 (7.31)
∂ z2 ∂t ∂t 2

In sinusoidal regime with phasor representation of v(z,t) = Re{V (z)ejωt }, we arrive at

d 2V
− (RG)V − (RC + LG) jωV − LC(−ω 2 )V = 0 (7.32)
dz2
Equation 7.32 can be rewritten as

d 2V
= (RG)V + jω(RC + LG)V − ω 2 LC V

2
(7.33)
dz
Defining Z = R + jωL and Y = G + jωC, Equation 7.32 can be written as

d 2V
= (ZY )V (7.34)
dz2

The propagation constant, γ, is defined as γ 2 = ZY , and then Equation 7.34 can be

recast as

V (z) = Ae−γz + Be+γz (7.35)

The constants in Equation 7.35 can be computed using the initial conditions. The first
term to the left represents the wave prorogating in the positive direction of the z-axis,
7.3 Characteristic Impedance of a Line 291

and the second term represents the wave prorogating in the negative direction of the
z-axis. Therefore, a more meaningful representation of Equation 7.35 would look like
V (z) = V0 + e−γz +V0 − e+γz (7.36)
It also follows that
p
γ = α + jβ = (R + jωL)(G + jωC) (7.37)
where the real and imaginary parts describe the attenuation and the phase constants,
respectively. Here the propagation constant has a nonlinear frequency dependency, and
therefore the transmission line is dispersive. The current waveform can be obtained by
substituting Equation 7.36 in the phasor form of Equation 7.27 and we obtain
γ
V0 + e−γz −V0 − e+γz

I(z) = (7.38)
R + jωL
As before, the wave traveling in the positive z-direction is
v+ (z,t) = V0 + e−αz cos(ωt − β z + φ + )

(7.39)
And hence the overall voltage waveform at the input is given by
v(z,t) = V0 + e−αz cos(ωt − β z + φ + ) + V0 − e+αz cos(ωt + β z + φ − ) (7.40)

The phase velocity can be defined as before for the lossy case, here we have
ω
υp = np o (7.41)
Im (R + jωL)(G + jωC)

7.3 Characteristic Impedance of a Line

The characteristic impedance of the line is defined as the ratio of the positive z-direction
traveling voltage to the positive z-direction traveling current as
V0 + (z)
Z0 = (7.42)
I0 + (z)
Writing Equation 7.27 in the phasor domain, we arrive at
dV
= −RI − jωLI = −ZI (7.43)
dz
Considering only the forward-propagating waves, V + and I + , and using Equation 7.43
we can write
−γV0 + e−γz = −ZI0 + e−γz (7.44)
where in using Equation 7.42, the characteristic impedance can be found to be
s
V0+
r
Z Z R + jωL
Z0 = + = = = (7.45)
I0 γ Y G + jωC
As it can be observed from Equation 7.45, the characteristic impedance is a function
of intrinsic properties of the line as well as the frequency. But once the line is lossless,
the characteristic impedance becomes independent of frequency.
292 Chapter 7. Transmission Lines and Impedance Matching

nH fF
Example 7.1 Consider Equation 7.45 for a line with L = 0.273 mm , C = 93.5 mm ,
mΩ µS
R = 170 mm , and G = 60 mm . Derive an expression for
the phase and amplitude
of
the line characteristic impedance from 0 to 1 GHz. λ` = 2n−2 4 (n ≥ 1) , and plot
the real and the imaginary parts as a function of frequency.

Solution:
It follows from Equation 7.45 that
s s
R + jωL 0.17 + jω(0.273)10−9
Z0 = = (7.46)
G + jωC 60 × 10−6 + jω(93.5)10−15

which is depicted in Figure 7.7.

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SDUWȍ

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Figure 7.7: Characteristic impedance of a line.

As it can be seen in the above figure, Z0 becomes almost pure real and inde-
pendent of frequency at the higher portion of the spectrum.

The current waveform as a function of the line characteristic impedance can also be
written as
1
V0 + e−γz −V0 − e+γz

I(z) = (7.47)
Z0

7.3.1 Lossless Transmission Line

The equations derived earlier can be well extended to any line in TEM mode, and as it
was shown, the propagation constant and line impedance in their most general forms
are complex quantities. In many practical cases, however, losses are small enough to
be neglected, that is the line resistance is sufficiently small compared to the line series
reactance, and the line conductance is sufficiently small compared to the line parallel
susceptance. Therefore, it follows from 7.37 that
p √
γ = α + jβ = (0 + jωL)(0 + jωC) = jω LC (7.48)
This means
√ that the attenuation constant is equal to zero and the phase constant
β = ω LC. Hence, the voltage and the current waveforms traveling through this line
7.4 Terminated Transmission Lines 293

will no longer experience any loss and will experience only a phase shift. The line
characteristic impedance becomes in this case as
s r
0 + jωL L
Z= = (7.49)
0 + jωC C

As it is observed from Equation 7.49, the line characteristic impedance becomes purely
real and it is also independent of frequency. The voltage and the current waveforms
can also be derived in the lossless case as
V (z) = V0 + e−jβ z +V0 − e+jβ z (7.50)

and
V0 + −jβ z V0 − +jβ z
I(z) = e − e (7.51)
Z0 Z0

The phase velocity is given by

ω ω 1
υp = = √ =√ (7.52)
β ω LC LC

As an example, for the values given in Example 7.1, the phase velocity amounts to
1.98 × 108 m/sec. If the medium in between the two conductors is homogeneous with
the permittivity ε and the permeability µ, it can be shown that for the transmission
line, one can write

LC = µε (7.53)

The wavelength can be readily derived from Equation 7.48 as

2π 2π
λ= = √ (7.54)
β ω LC

We also know that the speed of TEM electromagnetic propagation wave in a dielec-
tric/magnetic medium is

1 c
υg = √ =√ (7.55)
µε µr εr

where c is the speed of light in vacuum. Using Equation 7.53, we end up with υP = υg
which means the phase velocity in a TEM transmission line is the same as the speed of
propagation in a free space medium.

7.4 Terminated Transmission Lines

In this section, we discuss the behavior of an arbitrarily terminated line, as depicted
in Figure 7.8. For now, we assume that the origin of the z-axis is located at the load
294 Chapter 7. Transmission Lines and Impedance Matching

I(z)
+
V(z) Z0,Ɣ ZL
-
Z

l Z=0

Figure 7.8: A terminated transmission line.

end. The voltage at the source end of the line is of interest, which can be written from
Equation 7.36 as

V (−`) = V0+ e+γ` +V0− e−γ` (7.56)

where ` is the distance from the load and the first term in the right-hand side is the
traveling wave in the positive z-direction and the second term is the reflected wave
in the negative z-direction. The current waveform can also be derived in a similar
manner as

V0+ γ` V0− −γ`

I (−`) = e − e (7.57)
Z0 Z0

Now, Equation 7.56 can be rewritten as

V−

V (−`) = V0+ eγ` +V0− e−γ` = V0+ eγ` 1 + 0+ e−2γ` (7.58)
V0

where V0 + is the traveling wave vector toward the load at Z = 0 and V0 − is the reflected
wave from the load at Z = 0. The ratio of the reflected wave to the incident wave at the
load is defined as reflection coefficient and can be computed as

V0− e−γ`
ΓL (−`) = = ΓL (0)e−2γ` (7.59)
V0+ e+γ`

Using the above definition, the voltage and the current waveforms can be written using
the reflection coefficient as

V (−`) = V0+ eγ` (1 + ΓL e−2γ` ) (7.60)

and

V0+ γ`
I (−`) = e (1 − ΓL e−2γ` ) (7.61)
Z0
7.4 Terminated Transmission Lines 295

It is easy to compute the input impedance by finding the ratio of the voltage to the
current phasors as

1 + ΓL e−2γ`

V (−`)
Z (−`) = = Z0 (7.62)
I (−`) 1 − ΓL e−2γ`

which gives the input impedance of an arbitrarily terminated T-line. If one chooses
` = 0, the load impedance is given as

1 + ΓL
Z (0) = Z0 = ZL (7.63)
1 − ΓL

The reflection coefficient in terms of load impedance becomes

ZL − Z0
ΓL = (7.64)
ZL + Z0

As suggested by Equation 7.64, if the load impedance is equal to the characteristic

impedance, the reflection coefficient becomes zero, in which case the matching is
achieved. Now, by substituting Equation 7.64 into Equation 7.62, an explicit expression
for the input impedance can be obtained as

ZL −Z0
 
1+ ZL +Z0 e−2γ`
Z (−`) = Z0   (7.65)
ZL −Z0
1− ZL +Z0 e−2γ`

Now, if the explicit expression of the input impedance of a T-line is to be derived,

Equation 7.65 can be rewritten as

(ZL + Z0 ) + (ZL − Z0 ) e−2γ`

Z (−`) = Z0 (7.66)
(ZL + Z0 ) − (ZL − Z0 ) e−2γ`

Multiplying the numerator and the denominator by e+γ` , it follows that

(ZL + Z0 ) e+γ` + (ZL − Z0 ) e−γ`

Z (−`) = Z0 (7.67)
(ZL + Z0 ) e+γ` − (ZL − Z0 ) e−γ`

Factoring Z0 and ZL out, Equation 7.67 can be rewritten using hyperbolic functions as

ZL cosh (γ`) + Z0 sinh (γ`)
Z (−`) = Z0 (7.68)
Z0 cosh (γ`) + ZL sinh (γ`)

By dividing the numerator and the denominator by cosh (γ`), we have

ZL + Z0 tanh (γ`)
Z (−`) = Z0 (7.69)
Z0 + ZL tanh (γ`)
296 Chapter 7. Transmission Lines and Impedance Matching

Now, we derive the above expressions for a lossless T-line. The voltage and the current
waveforms are given by

V (−`) = V0+ ejβ ` 1 + ΓL e−2jβ ` (7.70)

and
V0+ jβ `
I (−`) = e 1 − ΓL e−2jβ ` (7.71)
Z0
Therefore, it follows that
!
1 + ΓL e−2jβ `

V (−`) ZL + jZ0 tan (β `)
Z (−`) = = Z0 = Z0 (7.72)
I (−`) 1 − ΓL e−2jβ ` Z0 + jZL tan (β `)

Since in the lossless T-line tanh (γ`)=tanh ( jβ `)= j tan (β `), by replacing tanh (γ`) in
Equation 7.69, we can obtain the same result as above. It follows from Equation 7.72,
the input impedance has a periodic property as a function of distance, and we have
2π nλ
β ` = nπ ⇒ ` = nπ ⇒ ` = (7.73)
λ 2
This means that the input impedance attains the same value for each λ2 length.
Equation 7.72 is used for a lossless transmission line while Equation 7.69 is used for a
lossy transmission line. The calculation of these complex equations can be simplified
through the use of the Smith chart which is provided in section 7.10.

Example 7.2 For the circuit in Figure 7.9, compute the input impedance and the
reflection coefficient at the input and at the load side.
(a) First, consider the following parameters for the line and find the results at 1 GHz.
(b) Consider the line is lossless and repeat part (a).
pF S
L = 1.125 µH Ω
m ,C = 450 m , R = 5 m , G = 0.01 m

Zin

Z0 =50Ω Z(l )=30-j20

l =0.5λ

Figure 7.9: The terminated T-line.

Solution:
(a) We have
p
γ = α + jβ = (R + jωL)(G + jωC) (7.74)
q
5+ j(2π ×109 )×1.125×10−6 0.01+ j(2π ×109 )×450×10−12

=
1
= 0.3 + j141.371
m
7.4 Terminated Transmission Lines 297

s
R + jωL
Z0 = ≈ 50 Ω (7.75)
G + jωC

Then, using Equation 7.68, the input impedance is given by

ZL + Z0 tanh (γ`) 30 − j20 + 50 tanh (γ`)
Z (−`) = Z0 = 50 (7.76)
Z0 + ZL tanh (γ`) 50 + (30 − j20) tanh (γ`)

λ 2π
Since ` = 2 and β = λ , then from Equation 7.76, the line length becomes
2π
λ β π
`= = = = 2.22 cm (7.77)
2 2 β

Therefore
 
30 − j20 + 50 tanh (α + jβ ) βπ
Z (−`) = 50   (7.78)
50 + (30 − j20) tanh (α + jβ ) βπ

From Equation 7.78, we have

Z (−`) = 30.2651 –j19.8399 Ω (7.79)

First, the reflection coefficient at the load side can be computed as

ZL − Z0 30 − j20 − 50
ΓL (0) = = = –0.1765 –j 0.2941 (7.80)
ZL + Z0 30 − j20 + 50

and for the source side, the reflection coefficient is given by

ΓL (−`) = ΓL (0)e−2γ` = –0.1741 –j 0.2902 (7.81)

As it is seen here the input reflection coefficient is slightly different from the load
reflection coefficient (because the line length is λ2 and the line is lossy).
(b) For the input impedance, we have from Equation 7.72
!
30 − j20 + j50 tan 2π

ZL + jZ0 tan (β `) λ 0.5λ
Z (−`) = Z0 = 50
50 + j(30 − j20) tan 2π

Z0 + jZL tan (β `) λ 0.5λ
= 30 − j20 (7.82)

The reflection coefficient can be found as

ΓL (−`) = ΓL (0)e−2β ` = –0.1765 – j0.2941 (7.83)

As it is seen here the reflection coefficient has exactly the same value as the input
(because the line length is λ2 and the line is considered as lossless).
298 Chapter 7. Transmission Lines and Impedance Matching

7.5 Special Cases of a Terminated Line

Some special cases of line loading are of specific interest and find their application in
filter design. These cases include terminations to the intrinsic characteristic impedance
of the T-line, short circuit, and open circuit.

7.5.1 Termination to the Line Characteristic Impedance

In this case, we assume that the load impedance is equal to Z0 , as depicted in
Figure 7.10. Therefore, for the input impedance, we have from Equation 7.69

Z0 + Z0 tanh (γ`)
Z (−`) = Z0 = Z0 (7.84)
Z0 + Z0 tanh (γ`)

for the reflection coefficient at the load and the source, we have

ZL − Z0 Z0 − Z0
ΓL = = =0 (7.85)
ZL + Z0 Z0 + Z0

Therefore, for this case, the input impedance is equal to the characteristic impedance
and the reflection coefficient will be equal to zero throughout the line, irrespective of
the location. No reflection will therefore occur on the line and perfect matching has
been achieved, and the voltage and the current waveforms can be derived as

V (−`) = V0+ e+jγ` (7.86)

and

V0+ +jγ`
I (−`) = e (7.87)
Z0

It implies that a voltage or a current wave can be moved from the point −` to point zero
with only a phase shift and then they will be absorbed by the load (with no reflection).
It should be noted that the normal PCB circuit wires cannot transmit the high-frequency
signals. Using transmission lines in PCBs, we can transfer very high frequency signals
to any devised distance.

I(-l )
+
Z0,Ɣ V(-l ) ZL
-

Figure 7.10: A terminated T-line to the intrinsic impedance.

7.5 Special Cases of a Terminated Line 299

7.5.2 Short-circuit load impedance

In this case, the load is terminated to a short circuit, i.e., ZL = 0, which is shown in
Figure 7.11.
It follows from Equation 7.69

0 + Z0 tanh (γ`)
Z (−`) = Z0 = Z0 tanh (γ`) (7.88)
Z0 + 0 × tanh (γ`)

which in case of a lossless line can be written as

Z (−`) = Z0 tanh ( jβ `) = jZ0 tan (β `) (7.89)

As it is obvious from Equation 7.89, the input impedance in this case is always an
imaginary quantity. This suggests that any arbitrary value of reactance can be obtained
with a T-line terminated to a short circuit. The value of the input impedance in this
case is depicted in Figure 7.12.
As it is obvious from Figure 7.12, the impedance assumes the values of zero and
infinity at even multiples of λ4 and at odd multiples of λ4 , respectively. This result shows

I(-l )
+
Z0,Ɣ V(-l )
-

Figure 7.11: A short-terminated T-line.

"
_=_ȍ

,QGXFWLYH
EHKDYLRU

" OJ

&DSDFLWLYH
EHKDYLRU

Figure 7.12: The input impedance of a short-terminated T-line.

300 Chapter 7. Transmission Lines and Impedance Matching

that moving away from a short-ended transmission line first for less than quarter wave
length distances, the input becomes inductive and for a length in excess of a quarter-
wave length, it becomes capacitive. In practice, we use short-ended transmission lines
shorter than a quarter of a wavelength to realize inductive impedances. The reflection
coefficient at the load can be computed from Equation 7.64 as
ZL − Z0 0 − Z0
ΓL = = = −1 (7.90)
ZL + Z0 Z0 + 0

7.5.3 Open-circuit load

In this case, the load impedance is assumed to be infinite, that is, ZL → ∞, which is
depicted in Figure 7.13. We first calculate the input impedance in this case as

ZL + Z0 tanh (γ`)
Z (−`) = Z0 = Z0 coth (γ`) (7.91)
Z0 + ZL tanh (γ`) ZL →∞
which for the lossless case reduces to

Z (−`) = Z0 coth ( jβ `) = − jZ0 cot (β `) (7.92)

As it is obvious from Equation 7.92, the input impedance in this case is always
imaginary, meaning that any value of a reactive impedance can be realized by this line.
The input impedance in this case is depicted in Figure 7.14.
As it is obvious from Figure 7.14, for odd multiples of λ4 and even multiples of λ4 ,
the input impedance is that of short circuit and open circuit, respectively. This result
shows that moving away from an open-ended transmission line first (for the lengths less
than a quarter wave length), the input becomes capacitive and for a length in excess of a
quarter wave length, it becomes inductive. In practice, we use open-ended transmission
lines shorter than a quarter of a wavelength to realize capacitive impedances. The
reflection coefficient can be computed from Equation 7.64 as

ZL − Z0
ΓL = =1 (7.93)
Z0 + ZL ZL →∞

I(-l )
+
Z0,Ɣ V(-l )
-

Figure 7.13: The input impedance of an open-terminated T-line.

7.6 Source and Load Mismatch in Lossless Lines 301

"
_=_ȍ

,QGXFWLYH
EHKDYLRU

" OJ

&DSDFLWLYH
EHKDYLRU

Figure 7.14: The input impedance of an open-terminated T-line.

7.6 Source and Load Mismatch in Lossless Lines

(A Reflection Coefficient Perspective)
We have assumed thus far that the input source has an impedance equal to the char-
acteristic impedance of the lines, resulting in no voltage or current reflection at the
source. This might not be true for practical purposes and in real cases, a small fraction
of incident wave is reflected off the line. An arbitrarily terminated line is depicted in
Figure 7.15. As waves are reflected from both ends, there are countless waves propagat-
ing along the line, nevertheless, in the steady state, there is only one wave propagating
toward the load and one wave toward the source. We shortly derive equations for the
current and voltage in this case. Figure 7.15 can be redrawn as shown in Figure 7.16 by
calculating the input impedance. From Figure 7.16, it follows using voltage division
that

Zin
V (−d) = VTH (7.94)
Zin + ZTH
and the input impedance can be calculated from Equation 7.72 as

ZL + jZ0 tan (β d)
Z (−d) = Z0 (7.95)
Z0 + jZL tan (β d)

I(-l )
ZTH
+ +
VTH Z0=β V(-l ) ZL
- -

Zin l

Figure 7.15: A T-line with its load and source impedances.

302 Chapter 7. Transmission Lines and Impedance Matching

ZTH
+ +
VTH V(-d) Zin
- -

Figure 7.16: Equivalent model of Figure 7.15 for input impedance calculation.

The voltage wave at Z = −` can be obtained from Equation 7.58 as

V (−`) = V0+ ejβ ` 1 + ΓL e−2jβ ` (7.96)

Equation 7.96 can be written for the input, and using Equation 7.94, we arrive at

Zin
V (−d) = V0+ ejβ d 1 + ΓL e−j2β d = VTH (7.97)
Zin + ZTH

The incident wave phasor can be obtained from Equation 7.96; it follows that

+ Zin −jβ d 1
V0 = VTH e (7.98)
Zin + ZTH 1 + ΓL e−j2β d

Now, by substituting Equation 7.98 in Equation 7.96, the voltage can be found at any
point along the T-line as
!
−j2β `

Zin −jβ (d−`) 1 + ΓL e
V (−`) = VTH e (7.99)
Zin + ZTH 1 + ΓL e−j2β d

It follows from Equation 7.99 that the impedance at distance d from the load as
!
V (−d) 1 + ΓL e−j2β d
Zin = Zin (−d) = = Z0 (7.100)
I (−d) 1 − ΓL e−j2β d

Then, an explicit expression of the ratio of the source impedance divided by the input
impedance can be found as
−j2β d

Zin (−d) Z0 1+Γ Le
1−ΓL e −j2β d
= (7.101)
Zin (−d) + ZTH 1+ΓL e−j2β d
Z0 1−Γ e−j2β d + ZTH
L

which reduces to

1 + ΓL e−j2β d

Zin (−d) Z0
= (7.102)
Zin (−d) + ZTH ZTH + Z0 1 − ΓL e−j2β d ZZTH −Z0
TH +Z0
7.6 Source and Load Mismatch in Lossless Lines 303

Considering the input reflection coefficient, we have

ZTH − Z0
ΓS = (7.103)
ZTH + Z0
If we substitute Equation 7.103 into Equation 7.102, we obtain
!
1 + ΓL e−j2β d

Zin (−d) Z0
= (7.104)
Zin (−d) + ZTH Z0 + ZTH 1 − ΓS ΓL e−j2β d

Hence, substituting Equation 7.104 into Equation 7.99, we arrive at

!
1 + ΓL e−j2β `

Z0 −jβ (d−`)
V (−`) = VTH e (7.105)
Z0 + ZTH 1 − ΓS ΓL e−j2β d

Finally, the voltage and current waveforms can be found at any point along the line
using Equation 7.105.

Example 7.3 Consider the circuit shown in Figure 7.17(a). Find the voltage
waveform at the input. (Hint: Derive the input such that it exhibits wave transmis-
sion back and forth toward the load and from the source. This behavior is depicted
in Figure 7.17(b).)

d
ZTH
+
VTH Z0,β ZL
-
(a)

d
ZTH
V
VΓLe-j2βd
VΓLe-j2βdΓS
+ VΓLe-j2βdΓSΓLe-j2βd
VTH ZL
VΓLe-j2βdΓSΓLe-j2βdΓS
-

(b)

Figure 7.17: (a) Demonstration of a T-line with its load and source
impedances, and (b) transmission of the wave back and forth on the line.
304 Chapter 7. Transmission Lines and Impedance Matching

Solution:
First, the voltage is divided between the source impedance and the input impedance.
Then, it moves along the line and a fraction of it is reflected, proportional to the
reflection coefficient, ΓL . This repeats while the wave reaches the sources and
is reflected back proportional to the source reflection coefficient, ΓS . In order to
quantify this behavior, we have

Z0
V (−d) = VTH 1 + ΓL e−j2β d + ΓL e−j2β d ΓS + · · ·
Z0 + ZTH
(7.106)
!
∞ i
Z0
= VTH 1 + (ΓS + 1) ∑ ΓL e−j2β d ΓS i−1
Z0 + ZTH i=1

Now, using the following expansion while |z| < 1,

∞
1
∑ zn = 1 + z + z2 + . . . = 1 − z , where z = ΓL ΓS e−j2β d (7.107)
n=0

We can rewrite Equation 7.106 as

!
Z0 ΓS + 1 ∞ i
V (−d) = VTH 1+ ∑ ΓL ΓS e−j2β d (7.108)
Z0 + ZTH ΓS i=1

which results in

Z0 ΓS + 1 1
V (−d) = VTH 1+ − 1 (7.109)
Z0 + ZTH ΓS 1 − ΓL ΓS e−j2β d

Now, we can use Equation 7.109 to derive an expression similar to that derived in
Equation 7.105 for d = `
!
1 + ΓL e−j2β d

Z0
V (−d) = VTH (7.110)
Z0 + ZTH 1 − ΓL Γs e−j2β d

As such, the general Equation 7.105 reduces to Equation 7.110 for ` = d. This
should make it clear that in fact the wave travels back and forth in multiple reflec-
tions to reach a steady-state condition.

7.7 Impedance Transformer Based on λ/4 line

(Impedance Inverter)
One of the interesting properties of T-lines occurs when its length is equal to ` =
λ λ
4 + n 2 (n ≥ 1). It follows from Equation 7.58 that
7.8 Voltage Standing Wave Ratio 305
!
ZL + jZ0 tan π
2 Z0 2
Z (−d) = Z0 π = (7.111)
Z0 + jZL tan 2
ZL

The important property revealed by Equation 7.111 is that it can transform the load
impedance to a value proportional to the inverse of load impedance (multiplied by
the square of characteristic impedance of the line). This property finds an important
application in impedance matching networks where one intends to change a real
impedance value to another real impedance value.

7.7.1 Synthesis of an Inductor and a Capacitor with a Transmission Line

One of the most important applications of T-lines is in matching networks. As it
was discussed earlier, the impedance seen through the line changes as a function of
the load and we observed that inductive and capacitive impedances can be achieved
when the line is terminated to an open or a short circuit. It therefore is tempting
to replace the bulky matching elements like capacitors and inductors with T-lines
terminated to a short or an open circuit, which are referred to as a short stub and an
open stub, respectively. Therefore, an open or short-terminated line can be used to
emulate a capacitor or an inductor, respectively, albeit for narrowband applications.
This application is conceptually demonstrated in Figure 7.18

7.8 Voltage Standing Wave Ratio

From Equation 7.70, we can calculate the voltage waveform along the line; specifically,
we can write
V (−`) = V0+ ejβ ` 1 + |ΓL | ejφL e−2jβ ` (7.112)

As it can be seen, the voltage along the line varies between a maximum and a minimum
value depending on the phase of the second term in the parentheses, i.e., φL − 2β `.
Along the transmission line at the point (points) where this phase is equal to zero, there
will be a maximum voltage and at the point (points) where this phase is equal to π,
there is a minimum voltage. The ratio of these two quantities is called voltage standing
wave ratio (VSWR).

C1 C1

L C2

Inductor Capacitor

Figure 7.18: Implementation of a narrowband inductor and a narrowband

capacitor using a short and an open-terminated line.
306 Chapter 7. Transmission Lines and Impedance Matching

ȍ ȍ

6KRUW 2SHQ
FLUFXLW FLUFXLW
D

ȍ ȍ

,PSOHPHQWDWLRQRIDVHULHVLQGXFWRU
E

ȍ

,PSOHPHQWDWLRQRIDSDUDOOHOFDSDFLWRU
F

Figure 7.19: (a) Implementation of a parallel inductor and a parallel capacitor

using short-circuit and open-circuit stubs, respectively, (b) Implementation
of a series inductor using a short-length high-impedance transmission line,
(c) Implementation of a parallel capacitor using a short-length low-impedance
stub, all in microstrip technology.

+
Vmax V (1 + |ΓL |) 1 + |ΓL |
V SW R = = 0+ = (7.113)
Vmin V0 (1 − |ΓL |) 1 − |ΓL |

Equation 7.113 provides a measure of input impedance matching as well. As an VSWR

equal to unity is only possible once ΓL = 0. In the case of a mismatch, VSWR assumes
a value greater than unity. A large value of VSWR is an indicator of a large value of
the reflection coefficient as well as a greater value of the reflected power which is equal
to |ΓL |2 Pinc where Pinc is the incident power.
Normally, the RF equipment designers give the input VSWR of their device
(instead of Γin ) as a measure of their device matching. The nearer its value is to
unity, the better the circuit is matched and the larger the value of VSWR indicates
poorer matching. Nowadays, with the emergence of advanced network analyzers the
input and output reflection coefficients of any device can be readily measured and
transformed into impedance or admittance values. The generalization of input and
output reflection coefficients concept can be interpreted as S-parameters that will be
studied in Chapter 8.

7.9 Impedance Matching: The L-Section Approach

The basic principle behind impedance matching was first introduced for connecting
a line with a certain characteristic impedance to a specific load. With matching,
reflections from the load on the line can be avoided, and therefore the traveling wave
is received at the other end with a sufficient power level. Impedance matching is of
utmost importance in wireless systems and circuits, by means of which the maximum
power transmission, the maximum SNR, and hence a higher data rate in the receivers,
the minimum required power in the transmitters, a higher lifetime for the power supply,
and a lower risk of undesired radiation can be achieved. Impedance matching also
7.9 Impedance Matching: The L-Section Approach 307

finds another application in amplifiers, where in order to achieve the maximum power
transmission in both input and the output, matching must be present between the source
and the input on the one hand, and the load and the output on the other. There are quite
a few points which merit specific attention in matching networks:
(1) Complexity: designing the most simple matching network possible is crucial. After
all, a smaller matching network is less expensive, more reliable and suffers from a
smaller attenuation with respect to its more complex counterparts;
(2) Bandwidth: every single matching network can only provide matching in a specific
bandwidth given by its specifications. This is, however, inadequate for many applica-
tions where a wideband matching is desired. There exists a myriad of techniques for
bandwidth extension, which as expected, come at the price of complexity;
(3) Implementation: the designer may prefer one matching structure to another based
on the type of the T-line, lumped elements, or the waveguide. For example, tuning
screws in waveguide arms provide better flexibility than the quarter wave length T-line,
and
(4) Tunability: In some applications, it is desirable to be able to fine-tune the matching
network so as to achieve the maximum power transmission to the load. Some architec-
tures are better fit for this property.
Consider the circuit depicted in Figure 7.20. We will call circuits of this kind which
have a frequency-selective behavior a resonant or a tank circuit thereafter. Before
dealing with the circuit details, let’s first discuss a parameter which provides a measure
of loss in energy storage element. Referred to as quality factor, Q, it is defined as
f0
Q= (7.114)
∆f
wherein f0 is the resonant frequency of the circuit and ∆ f is the corresponding 3 dB
bandwidth. Nevertheless, the presence of load and source impedances degrades the
overall quality factor of the circuit. We call the matching in this case a loaded one.
The effect of the source impedance on the frequency response of the resonant network
is depicted in Figure 7.21. As it is evident in Figure 7.21, when the input impedance
is equal to 50 Ω, the frequency response is wider, while for an input impedance of
1000 Ω, a much narrower response is observed. The inductance of the inductor is also
important in the overall quality factor of the circuit. As depicted in Figure 7.22, with a
higher inductance, a lower Q is obtained mainly due to ohmic losses. In this circuit,
RS
Q = Lω 0
= RSCω0 .
As stated in the beginning of this chapter, one of the properties of matching
network is maximum power transmission. As you can recall from the basic circuit
theory, in a DC circuit, maximum power transmission between the load and the source

RS

+ L
Vin RL C
Rloss

Figure 7.20: A loaded resonant circuit.

308 Chapter 7. Transmission Lines and Impedance Matching

0 RS
Vout
|Vout/Vin|(dB)
-10
-20
-30 Vin XL XC
-40
-50 Q=1.1, RS=50Ω
Q=22.4, RS=1000Ω
-60 1 L=50nH,C=25pF
10 102 103
Frequency (MHz)

Figure 7.21: The effect of source impedance on Q.

Q+ S) ȍ
_=MȦ_

=



Q+ S) ȍ
)UHTXHQF\0+]
=

Figure 7.22: The effect of inductance on Q.

0.26
0.24 1Ω Vout
0.22
P(Watt)

0.2
0.18
0.16
0.14 Vin RL
0.12
0.1
0.08
10-1 100 101
RL(Ω)

Figure 7.23: Output power characteristic for a DC circuit.

impedances occurs when the two have equal values. Depicted in Figure 7.23 is the
power that is delivered to a variable load for a 1 V source.
Now, let’s consider the more general case depicted in Figure 7.24, which includes
a source impedance having both resistive and inductive components, and a load
consisting of a capacitive and a resistive component. If the capacitor and the inductor
resonate at some frequency, the circuit then reduces to that shown in Figure 7.22,
and maximum power transmission is achieved by choosing equal load and source
impedances. That is the total load impedance should be the complex conjugate of the
7.9 Impedance Matching: The L-Section Approach 309

ZS
RS jXS ZL RS

-jXL
+ RL + RL
Vin Vin

Figure 7.24: The general case of maximum power transmission to the load.

source impedance (ZL = ZS∗ ). In order to achieve this condition, we now proceed to
introduce some popular matching structures, known as L-sections. Different variants
of an L-section are depicted in Figure 7.25.
We analyze, in the final section of this chapter, all the structures depicted in
Figure 7.25 using a powerful tool called Smith chart. Now, we consider the basic
impedance matching methods. See Figure 7.27.

RS L RS L

+ +
Vin C RL Vin C RL

Lowpass Lowpass

RS C RS C

+ +
Vin L RL Vin L RL

Highpass Highpass

Figure 7.25: Four possible variants of an L-section matching network.

ȍ Mȍ

Mȍ ȍ

= Mȍ

Figure 7.26: An example of an L-section matching network.

310 Chapter 7. Transmission Lines and Impedance Matching

-j300Ω
100Ω

Z1

Figure 7.27: The equivalent circuit of the network shown in Figure 7.26 at the
operating frequency.

Firstly assume that the source is terminated to an RL = 100 Ω load and we calculate
the power delivered to this load. Secondly assume that in Figure 7.26, the LC matching
network (L-section) is omitted and the source is terminated to an RL = 1000 Ω load
and we recalculate the power delivered to this load. The ratio of this latter power to the
former power is defined as the mismatch loss.
vmismatch 2
vmismatch 2 Rmatch

pmismatch Rmismatch
L = −10 log = −10 log = −10 log =
pmatch vmatch 2 vmatch Rmismatch
Rmatch
(7.115)
2
0.909vin 100
− 10 log = 4.8 dB
0.5vin 1000

As demonstrated by Equation 7.115, the loss is equal to 4.8 dB. Now, if we employ
the circuit shown in Figure 7.26, the impedance seen at the load, Z1 ,will amount to
100 − j300 Ω. Let’s calculate the equivalent impedance of the RC section as

jXC RL − j333(1000)
Z= = = 100 − j300 (7.116)
jXC + RL − j333 + 1000

This is equivalent to the circuit shown in Figure 7.27 at the operating frequency. Now,
if an inductor of 300 jΩ is added in series to this network, then the load impedance will
be purely resistive and equal to 100 Ω. This is conceptually depicted in Figure 7.28.
What we have learned from the concept of impedance matching thus far suggests that a
parallel element can lower the real part of the impedance level of the load, which for the

+j300Ω

-j300Ω
100Ω = 100Ω

Z2 Z2

Figure 7.28: Impedance matching by adding an inductor.

7.9 Impedance Matching: The L-Section Approach 311

case studied here, a 1000 Ω load was lowered to 100 Ω. The series element can resonate
with the other energy-storing element, resulting in a purely resistive impedance equal
to the source impedance. This, however, points to a possible limitation of series or
shunt resonant matching network, which is their narrowband response due to single
frequency matching or resonance.

7.9.1 A New Definition of the Quality Factor

As we discussed in the previous section, Q factor plays a crucial role in matching
networks of all kind. We consider the Q factor of a reactance (either inductive or
capacitive) either in series or in parallel definition, as follows
XS (ω0 ) RL
QS = , QP = (7.117)
RS XP (ω0 )
where Qs and Qp are the series and parallel quality factors, and Xs and Xp are the
series and the parallel reactances, respectively. Rs and Rp are the equivalent series and
parallel resistances of the considered reactance, respectively.
As shown in Figure 7.29, equating the series and the parallel impedances, we
arrive at
Rp ( jXp )
Rs + jXs = (7.118)
Rp + jXp
Equating the real and the imaginary parts of Equation 7.118 to each other, we have

Rp Xp 2
Rs = (7.119)
Rp 2 + Xp 2
and
Rp 2 Xp
Xs = (7.120)
Rp 2 + Xp 2
which represent the equivalent series and parallel impedances, respectively. Given the
fact that QP = QS , it follows from Equation 7.119 that
Rp
= 1 + Qp 2 = 1 + Qs 2 (7.121)
Rs

XS
Xp Rp
RS

Figure 7.29: The equivalent circuit of a reactance with a limited quality factor.
312 Chapter 7. Transmission Lines and Impedance Matching

Therefore, the quality factor is given by

r
Rp
Qs = Qp = −1 (7.122)
Rs

Now, for an L-section matching, using two different reactances, one can use the source
resistance, the load resistance, and Equation 7.122, as the starting point and then
one chooses two reactances of the opposite signs to realize the conjugate matching
condition. It is obvious that this matching procedure is applicable once Rp > Rs . This
principal matching procedure is demonstrated in Figure 7.30.

Qs=Xs/Rs
Qp=Rp/Xp
Rs
Xs

+ Xp Rp
Vin

Rp
Qs=Qp= -1
Rs

Figure 7.30: The definition of Q in a matching network.

Example 7.4 Consider the circuit shown in Figure 7.31. Design a matching
network at 100 MHz which matches a source impedance of 100 Ω to the load
impedance of 1000 Ω. Also, you may assume that the circuit is DC coupled.

RS L

+
Vin C RL

Figure 7.31: An L-section matching network.

Solution:
We first compute the quality factor from Equation 7.122 as
r r
Rp 1000
Qs = Qp = −1 = −1 = 3 (7.123)
Rs 100
7.9 Impedance Matching: The L-Section Approach 313

The series and parallel reactances are also given by

Xs = Qs Rs = 3 × 100 = 300 Ω (7.124)

and
−Rp −1000
Xp = = = −333.3 Ω (7.125)
Qp 3

respectively. The values of the inductor and the capacitor can both be easily
calculated as
Xs 300
L= = = 477 nH (7.126)
ω 2π(100 × 106 )

and
1 1
C=− = = 4.8 pF (7.127)
ωXp 2π(100 × 106 )(333.3)

respectively.

Now that we have learned the impedance matching concept, we turn to complex load
and source impedances. This can be the case while circuits are being interfaced to real-
world impedances like antennas, mixers, T-lines, transistors, and other components,
where their input impedance is both complex and frequency-dependent. A possible so-
lution can be absorption of impedances within the matching network. This can be done
by absorbing the stray capacitances into parallel matching capacitors, and by absorbing
the stray inductances into series matching inductors. We elaborate on this point in
Example 7.5 in which series resonance occurs at the desired frequency.

Example 7.5 Consider the circuit depicted in Figure 7.32. Using impedance
absorption technique, match the source and load impedances at 100 MHz.

100Ω 200nH

Z
match 2pF 1000Ω
100-j126

Figure 7.32: Impedance matching at the source and the load.

314 Chapter 7. Transmission Lines and Impedance Matching

Solution:
The first step is to consider only the real part of the source impedance which is
100 Ω at 100 MHz and the real part of the load impedance which is 1000 Ω at
100 MHz. Using the numerical results of Example 7.4, the matching network will
look like that depicted in Figure 7.33. The matching of the 1000 Ω to the 100 Ω
source would need a 477 nH series inductor and a parallel 4.8 pF shunt capacitor as
demonstrated in Example 7.4. By subtracting the existing 200 nH inductance from
the 477 nH needed one and subtracting the 2 pF capacitance from the 4.8 pF needed
one, we obtain the resultant values shown in the dashed recangle in Figure 7.33.

100Ω 200nH 277nH

2.8pF 2pF 1000Ω

100-j126

Figure 7.33: The proper matching network for complex source and complex
load matching.

Note that here we had positive values for the series inductance and the parallel
capacitance, given the fact that the total needed inductance and the total needed
capacitance in the matching network were larger than the stray inductance and the
stray capacitance, respectively.

In Example 7.6, we discuss impedance matching using resonating load.

Example 7.6 Design a matching network at 75 MHz for the circuit shown in
Figure 7.34. Employ DC blocking.

50Ω

Z
match 40pF 600Ω

Figure 7.34: Impedance matching using resonance.

Solution:
The desired matching network which employs DC blocking is illustrated in
Figure 7.35.
7.9 Impedance Matching: The L-Section Approach 315

50Ω C

L 40pF 600Ω

Figure 7.35: Impedance matching network using a resonating load.

We first place an inductor in parallel with the 40 pF stray capacitance so that

they resonate at 75 MHz. It then follows that

1 1
L= = = 112.6 nH (7.128)
ω 2C 6 2
2π(75 × 10 ) × 40 × 10−12

A part of the matching network is illustrated in Figure 7.36.

50Ω

Z
match 112.6nH 40pF 600Ω

Figure 7.36: A part of the matching network.

Now that the stray capacitance has been tuned out, we should match the 50 Ω
source to 600 Ω load resistor. Hence,
r r
Rp 60
Qs = Qp = −1 = − 1 = 3.32 (7.129)
Rs 5

It then follows from Equation 7.117 that

Xs = −Qs Rs = −3.32 × 50 = −166 Ω (7.130)

and
Rp 600
Xp = = = 181 Ω (7.131)
Qp 3.32

which corresponds to

Xp 181
L= = = 384 nH (7.132)
ω 2π(75 × 106 )
316 Chapter 7. Transmission Lines and Impedance Matching

and
1 1
C=− = = 12.7 pF (7.133)
ωXs 2π(75 × 106 )(166)

respectively, and the matching network is depicted in Figure 7.37.

50ȍ 12.78pF

384nH 112.6nH 40pF 600ȍ

Figure 7.37: The designed matching network.

Now, if we replace two parallel inductors with one, the final matching network
will be as depicted in Figure 7.38.

50Ω 12.78pF

87nH 40pF 600Ω

Figure 7.38: The final matching network in Example 7.11.

Another method which is used for impedance matching is known as the π and T
method, which is illustrated in Figure 7.39.
A π network can be formed by cascading two L-sections with a virtual resistor in
between, as shown in Figure 7.40.
The negative signs in the parallel reactances are just for representation purposes;
however, the important point is that they differ with their series counterparts in sign.
Therefore, if Xp1 is a capacitor, Xs,1 must be an inductor and vice versa. Similarly, if Xp2

RS RS
X1 X3 X2

X2 RL X1 X3 RL

Figure 7.39: π and T matching networks.

7.9 Impedance Matching: The L-Section Approach 317

Req
RS
Xs1 Xs2

-Xp1 -Xp2 RL

Figure 7.40: π matching network.

is a capacitor, then Xs2 must be an inductor and vice versa. Now, from Equation 7.122,
it follows that
s
RH
Q= −1 (7.134)
Req

where RH is the larger resistor on the source and the load side, and Req is the virtual
resistor between the two networks. Evidently, RH should be larger than Req .

Example 7.7 Consider the circuit shown in Figure 7.40. Design a π match-
ing network such that the input impedance of 100 Ω is matched to a 1000 Ω load
impedance. The loaded Q of each L-section is equal to 15.

Solution:
We first consider Q from Equation 7.134, and calculate the virtual resistor as

RH 1000
Req = = = 4.42 Ω (7.135)
Q2L + 1 226

We can then use Equation 7.117, the series and parallel reactances, as depicted in
Figure 7.41, can be calculated as

Req
Xs2

-Xp2 RL

Figure 7.41: The right-hand equivalent half-circuit of the π matching

network.

Xs2 = Qs2 Req = 15 × 4.42 = 66.3 Ω (7.136)

318 Chapter 7. Transmission Lines and Impedance Matching

Note that Qs2 = Qp2 in this section. Therefore

RL 1000
Xp2 = = = 66.7 Ω (7.137)
Qp2 15

Now, we analyze the left-hand L-section. The quality factor for this circuit, as
depicted in Figure 7.42, can be found as

Req
Xs1

RS -Xp1

Figure 7.42: The left-hand equivalent half-circuit of the π matching network.

s r
RS 100
Qs1 = Qp1 = −1 = − 1 = 4.6 (7.138)
Req 4.42

and using Equation 7.117, the parallel and series reactances can be calculated as

Xs1 = Qs1 Req = 4.6 × 4.42 = 20.51 Ω (7.139)

and
RS 100
Xp1 = = = 21.7 Ω (7.140)
Qp1 4.6

Now that we have the values of all the reactances, the overall matching network
can be chosen as in Figure 7.43 in a different version depending on the chosen sign
of the reactances.

Req
100Ω
Xs1 Xs2

-Xp1 -Xp2 1000Ω

Figure 7.43: π matching network.

7.9 Impedance Matching: The L-Section Approach 319

Figure 7.44 shows a DC-coupled (low-pass) version of the π matching network.

100Ω +j20.5Ω +j66.3Ω 100Ω +j86.8Ω

-j21.7Ω -j66.7Ω 1000Ω -j21.7Ω -j66.7Ω 1000Ω

Figure 7.44: Low-pass version of the π matching network.

The main point to remember here is that the reactances in each branch of
L-sections have a different sign. Therefore, the other structures can also be used for
matching, all of which are depicted in Figure 7.45. In total, four combinations of π
section matching network (depending on low-pass/DC coupled or high-pass/AC
coupled L-section being chosen) are possible to realize.

It could be verified through circuit simulations that the overall quality factor
and therefore the corresponding bandwidth of this matching circuit could be found
through the following relation

Qs1 + Qs2 Qp1 + Qp2

Qtotal = = (7.141)
2 2

-j20.5Ω -j66.3Ω -j86.8Ω

+j21.7Ω +j66.7Ω +j21.7Ω +j66.7Ω

-j20.5Ω +j66.3Ω +j45.8Ω

+j21.7Ω -j66.7Ω +j21.7Ω -j66.7Ω

+j20.5Ω -j66.3Ω -j45.8Ω

-j21.7Ω +j66.7Ω -j21.7Ω +j66.7Ω

Figure 7.45: Variants of the matching network with inductors and capacitors
in a π structure.

320 Chapter 7. Transmission Lines and Impedance Matching

RS
Xs1 Xs2

-Xp1 -Xp2 RL
Req

Figure 7.46: T matching network.

The reader may wonder that which one of the parameters should be chosen for the
matching network. In order to pick one of them, it should be noted that the following
parameters might be taken into account: DC coupling or AC coupling, the values of
stray capacitances or stray inductances to be tuned out (to be deduced from the match-
ing network), harmonic voltages or harmonic currents to be eliminated, the frequency
response of the matching network, and finally realizable values for the matching
elements.
We now proceed by discussing the T matching network. Matching with a T
network is very much similar to its π counterpart and it is done by two L-sections as
well. With the exception that both of the L-sections are matched to a larger value of
virtual resistance and the horizontal part of the L-section, that is, the series reactance
comes in series with the load or the source. As a result, the parallel arms of the two
L-sections will eventually appear in parallel. The T matching network is depicted in
Figure 7.46.
Let’s now return to our definition of Q as
r
Req
Q= −1 (7.142)
Rl
where Req is the virtual resistance to be matched to the load and the source, and Rl
is the minimum of the load and the source resistances. Example 7.8 clarifies this
point.

Example 7.8 Consider the circuit illustrated in Figure 7.46. Design four dif-
ferent matching networks which match a 10 Ω source impedance to a 50 Ω load
impedance. The loaded Q is chosen to be 10.

Solution:
The virtual resistance can be found from Equation 7.142 as

Req = Rl (Q2L + 1) = 10(101) = 1010 Ω (7.143)

and the values of the series and the parallel reactances, as depicted in Figure 7.47,
can be calculated using Equation 7.117 as
7.9 Impedance Matching: The L-Section Approach 321

RS
Xs1

-Xp1 Req

Figure 7.47: The left-hand equivalent half-circuit of the T matching

network.

Xs1 = Qs1 RS = 10 × 10 = 100 Ω (7.144)

Req 1010
Xp1 = = = 101 Ω (7.145)
Qp1 10

Now, it follows from Equation 7.142 that the quality factor of the right-hand
L-section, as depicted in Figure 7.48, is

RL
Xs2

Req -Xp2

Figure 7.48: The right-hand equivalent half-circuit of the T matching

network.

r r
Req 1010
Qs2 = Qp2 = −1 = − 1 = 4.4 (7.146)
RL 50

and using Equation 7.142, we have

Xs2 = Qs2 RL = 4.4 × 50 = 220 Ω (7.147)

and
Req 1010
Xp2 = = = 230 Ω (7.148)
Qp2 4.4

Finally, the four possible T matching networks are depicted in Figure 7.49. Note
that the final parallel reactance is the resultant parallel combination of the two
middle reactances of each L-section.
322 Chapter 7. Transmission Lines and Impedance Matching

It could be verified through circuit simulations that the overall quality factor
and therefore the corresponding bandwidth of this matching circuit could be found
through the following relation

Qs1 + Qs2 Qp1 + Qp2

Qtotal = = (7.149)
2 2

10Ω
Xs1 Xs2

-Xp1 -Xp2 50Ω

+j100Ω +j220Ω +j100Ω +j220Ω +j100Ω -j220Ω +j100Ω -j220Ω

-j101Ω -j230Ω -j70Ω -j101Ω +j230Ω -j180Ω

-j100Ω -j220Ω -j100Ω -j220Ω -j100Ω +j220Ω -j100Ω +j220Ω

+j101Ω +j230Ω +j70Ω +j101Ω -j230Ω +j180Ω

Figure 7.49: Variants of T matching network.

As in the previous example, here each one of the four variants could be chosen ac-
cording to the following criteria: DC coupling or AC coupling, the required frequency
response, low-pass or high-pass response, the requirement to deduce the stray capac-
itances or inductances from the matching network, harmonic voltages or harmonic
currents to be eliminated, and finally realizable values for the matching elements. Thus
far, we have learned to match any passive load to any passive source impedance using
L, π, or T networks. We should have realized in this section, that matching networks
are indispensable parts of any radio-frequency circuit. In the next section, we introduce
a powerful tool which could be used for matching networks calculations, that is the
Smith chart application.

7.10 Smith Chart Mapping

First developed in 1930 at Bell Labs by Philip Smith, the Smith chart was first thought
of as a simple tool which would circumvent lengthy impedance matching calculations
in RF circuits. Before dealing with the equations, we should note that Smith chart
is nothing but a mapping of impedances to the reflection coefficient plane. We now
proceed by carrying out the required derivations to reach to this chart. One may recall
from section 7.2 that the reflection coefficient can be written as
ZL
ZL − Z0 Z0 −1
ΓL = = ZL
(7.150)
ZL + Z0 Z0 +1
7.10 Smith Chart Mapping 323

Now, if we define ZL /Z0 as the normalized impedance and writing ΓL in terms of its
real and imaginary parts, it follows that

Zn − 1 R + jX − 1
Γr + jΓi = = (7.151)
Zn + 1 R + jX + 1

In order to find an explicit expression for the Smith chart contours, we rewrite
Equation 7.151 as

1 + ΓL
Zn = (7.152)
1 − ΓL
We proceed by replacing the real and the imaginary parts of the reflection coefficient
and the normalized impedance in Equation 7.152, hence,

1 + Γr + jΓi
R + jX = (7.153)
1 − Γr − jΓi

By multiplying the right-hand side of Equation 7.153 by the complex conjugate of the
denominator, we arrive at

1 + Γr + jΓi 1 − Γr + jΓi 1 − Γr 2 − Γi 2 + 2 jΓi

R + jX = × = (7.154)
1 − Γr − jΓi 1 − Γr + jΓi (1 − Γr )2 + Γi 2

Equating the real and the imaginary parts of Equation 7.154, we have

1 − Γr 2 − Γi 2
R= (7.155)
(1 − Γr )2 + Γi 2

and
2Γi
X= (7.156)
(1 − Γr )2 + Γi 2

Equations 7.155 and 7.156 play a crucial role in finding an expression for the Smith
chart contours. Rewriting Equations 7.155 and 7.156 in two complete square forms in
terms of Γr and Γi , we arrive at
2 2
R 1
Γr − + Γi 2 = (7.157)
1+R 1+R

and

1 2
2
1
(Γr − 1)2 + Γi − = (7.158)
X X

Equations 7.157 and 7.158 represent constant resistance and constant reactance con-
tours in the Γr -Γi plane. Each point in this plane corresponds to a unique reflection
324 Chapter 7. Transmission Lines and Impedance Matching

Γi Γi
Inductive reactance component
+j 1

0 0.2 0.5 1 2 5 Γr 0
Γr

-j 1
Capacitive reactance component

Constant Constant
resistance circles reactance circles
Figure 7.50: Constant-resistance and constant-reactance circles within |Γ| ≤ 1
plane.

coefficient and therefore a unique impedance in that plane. Equation 7.157 represents a
group of circles centered at (x, y) = (R/ (1 + R) , 0) and with a radius of r = 1/ (1 + R).
Equation 7.158 represents a group of circles centered at (x, y) = (1, 1/X) and with
a radius of r = 1/X. Drawing the two groups of circles for loads having a positive
real part (within a circle centered at the origin and with the unity radius) results in
the Smith chart. The intersection of the reactance and the resistance circles results in
a specific impedance in the Γr -Γi plane. Constant-resistance and constant-reactance
circles are shown in Figure 7.50.
Now, we mention a few points regarding the Smith chart. (1) The intersections of
constant-resistance circles with the Γr axis (x-axis) are purely real impedance (R + j0)
points. (2) The intersections of constant-reactance circles with the |Γ| = 1 circle are the
purely imaginary impedance (0 + jX) points. (3) The center of the chart corresponds
to R = 1 point. (4) The perimeter of the chart corresponds to R = 0 points. (5) The
extreme right-hand point on the x-axis that is Γ = 1 corresponds to an open circuit.
(6) The extreme left-hand point on the x-axis that is Γ = −1 corresponds to a short
circuit. (7) Load impedances having a negative real part would be projected out
of the chart, that is, out of the |Γ| = 1 circle. Evidently for these impedances the
corresponding reflection coefficient would have an amplitude greater than unity.

Example 7.9 Show Z1 = 50+ j50 and Z2 = 50− j50 on the Smith chart. Assume
the line impedance is equal to 50 Ω.

Solution:
We begin by calculating the normalized values of the impedances,

Z1
Z1n = = 1+ j (7.159)
50
7.10 Smith Chart Mapping 325

and
Z2
Z2n = = 1− j (7.160)
50
which can be found using the Smith chart by finding the intersections of R = 1 and
X = 1, and R = 1 and X = −1 circles, respectively. This procedure is shown in
Figure 7.51.

Γi
+j 1

1+j

0 0.2 0.5 1 2 5 Γr

1-j

-j 1

Figure 7.51: Representation of the two impedances in the Smith chart.

Recalling Equation 7.72, one can write the impedance value at a distance d from the
load as follows
!
1 + ΓL e−2jβ `

1 + Γ(−d)
Z(−d) = Z0 = Z0 (7.161)
1 − Γ(−d) 1 − ΓL e−2jβ `

As it is evident from Equation 7.161, if one is moving toward the generator, by rotating
an amount of 2β ` clockwise from the initial impedance point, he/she would arrive at
the new impedance point on the chart. Otherwise, if one is moving from the initial
point toward the load, by rotating an amount of 2β ` counterclockwise, he/she would
arrive at the new impedance point on the chart.
326 Chapter 7. Transmission Lines and Impedance Matching

Example 7.10 Consider the normalized impedance Z = 0.5 + j0.7 and assume
that a −1 j reactance is added in series to this impedance. Sketch the initial and the
resulting impedances on the Smith chart.

Solution:
The initial and the final points are shown on the Smith chart in Figure 7.52.

Z 0 = Z − j1 = 0.5 − j0.3 (7.162)

Now moving on the R = 0.5 circle from the initial X = j0.7 toward X = − j0.3,
we come from the initial point to the final point on the chart.

Γi
+j 1

0.5+j0.7

0 0.2 0.5 1 2 5 Γr
0.5-j0.3

-j 1

Figure 7.52: Representation of the effect of adding a series capacitive

reactance in the Smith chart.

We now turn our attention to Admittance Smith chart, that is, constant-conductance
and constant-susceptance circles. Recall that

1
Yn −1 1 −Yn
Γ= 1
= (7.163)
Yn +1 1 +Yn
If we imagine having a load whose normalized impedance is inverse of the given
normalized admittance (Zn = Y1n ), the Admittance Smith chart could be obtained by the
same procedure as the Impedance Smith charts just by replacing Γ by −Γ as shown in
Equation 7.164. In other words, if we rotate the impedance Smith chart by 180◦ , the
same chart would represent the Admittance Smith chart.
1
Yn −1 1 −Yn
ΓZ = 1
= = −Γ (7.164)
Yn +1 1 +Yn
7.10 Smith Chart Mapping 327

As such, the conductance and the susceptance circles can be derived from the resistance
and the reactance circles, respectively. This procedure is useful in the sense that once
we desire to add any reactance or resistance in series, we use the Impedance Smith
chart and once we desire to add any susceptance or conductance in parallel, we use the
Admittance Smith chart. A complete Smith chart is shown in Figure 7.53, in which the
blue and the red circles denote the impedance and admittance circles, respectively.
Care should be taken by the reader while using the Smith chart. Notice that wherever
on the chart the reactance is positive (upper half of the chart), then the susceptance is
negative and wherever on the chart the reactance is negative (lower half of the chart),
then the susceptance is positive. Furthermore, wherever on the chart the normalized
resistance is greater than unity, then the normalized conductance is less than unity
and wherever the normalized conductance is greater than unity, then the normalized
resistance is less than unity.
7.10.1 Some simple application rules while using the Smith chart
Rule 1: For matching, we generally use circular paths on the chart.
Rule 2: Rotating clockwise on a constant resistance circle is equivalent to adding a
series inductance.
Rule 3: Rotating counterclockwise on a constant resistance circle is equivalent to
adding a series capacitance.
Rule 4: Rotating clockwise on a constant conductance circle is equivalent to adding a
shunt capacitance.
Rule 5: Rotating counterclockwise on a constant conductance circle is equivalent to
adding a shunt inductance.
Rule 6: Rotating clockwise on a constant radius circle about the chart center is
equivalent to approaching the generator on the transmission line.
Rule 7: Rotating counterclockwise on a constant radius circle about the chart center is
equivalent to approaching the load on the transmission line.
Rule 8: Jumping from a constant resistance circle to another constant resistance
circle (on the real axis) is equivalent to putting a transformer on the transmission line,
meaning that increasing or decreasing the input resistance (depending on the sense of
the jump).
Rule 9: Jumping from a constant conductance circle to another constant conductance
circle (on the real axis) is equivalent to putting a transformer on the transmission line,
meaning that increasing or decreasing the input conductance (depending on the sense
of the jump).
Rule 10: Just rotating by 180◦ , one can read the admittance value on the same chart
(once he/she has recorded the impedance value on the impedance chart). Otherwise,
just rotating by 180◦ , one can read the impedance value on the same chart (once he/she
has recorded the admittance value on the admittance chart).
Rule 11: Using quarter wave transformers, one can travel clockwise on a half-circle
from the starting point at the load impedance to the desired input impedance at the end
point. As seen in Figure 7.54, this way one can transform a high impedance (point A)
to a low impedance (point B), or one can transform a low impedance (point C) to a
high impedance (point D).
The application of these rules is illustrated in Figure 7.54. We now revisit
example 7.11 and repeat it using the Smith chart.
328 Chapter 7. Transmission Lines and Impedance Matching

Γi
+j 1
-j 1

0.2 0.2
0.5 0.5
1 1
2 2
5 5

Γr

+j 1
-j 1

Figure 7.53: The complete Smith chart.

Example 7.11 Consider the circuit depicted in Figure 7.34. Use the Smith
chart to determine a matching network at 75 MHz which incorporates DC current
blocking.

Solution:
The load impedance consisting of a parallel resistor and a capacitor is depicted on
the admittance chart as YL = 1.7 + j18.9 mS or in normalized form ȲL = 0.085 +
j0.945 or its normalized impedance is depicted as Z̄L = 0.095 − j1.05 at point 1.
Now, we move on the constant normalized conductance circle of 0.085, on the
admittance chart such that we come across the R = 1 circle at point 2. We now
record the difference in normalized susceptances of point 2 and point 1 as

jB2 − jB1 = j0.945 − (− j0.265) = j1.21 (7.165)

The inductive susceptance to be added in parallel with the load would become
then

Bt = 1.21 × 20 mS = 24.2 mS (7.166)

7.10 Smith Chart Mapping 329

5XOH 5XOH 5XOH

5XOH 5XOH 5XOH 5XOH

% $
& '

5XOH 5XOH 5XOH 5XOH

Figure 7.54: The Smith chart rules and applications.

1 1
L= = = 87.7 nH (7.167)
0.0242ω 0.0242 × 2π 75 × 106

At point 2, we record the reactance X̄2 = j3.4 or X2 = 170 Ω. We should add a

capacitive reactance of −170 Ω to tune out this inductance as follows

1 1
C= = = 12.5 pF (7.168)
170ω 170 × 2π 75 × 106

With this series capacitance, we come to the center of the chart at point 3 as
depicted in Figure 7.55.
330 Chapter 7. Transmission Lines and Impedance Matching

Γi

2
Γr
3
1

1
Yn1=0.085+j0.945 Zn1=0.095-j1.05
Yn2=0.085-j0.265 Zn2=1+j3.4
Yn3=1 Zn3=1

Figure 7.55: Matching on the Smith chart.

Example 7.12 Find a matching network to match the load impedance illustrated
in Figure 7.56 to 50 Ω at 2.5 GHz. The reference impedance is 50 Ω.

0DWFKLQJ
=LQ =/ &S S) 5S ȍ
QHWZRUN

Figure 7.56: The load impedance of Example 7.12.

Solution:
We first compute the normalized admittance at 2.5 GHz

1/200 + j2π(2.5 × 109 )10 × 10−12

YL
Yn1 = = = 0.25 + j0.7854 (7.169)
Y0 0.02

This admittance is shown in Figure 7.57 on the Smith chart.

7.10 Smith Chart Mapping 331

Γi

Γr

1
0.25

Yn1=0.25+j0.785 Zn1=0.37-j1.16

Figure 7.57: Representation of the load admittance on the Smith chart.

As it was discussed earlier, matching can be achieved using an L-section, as

depicted in Figure 7.58.

/
=LQ & =/ &S S) 5S ȍ

0DWFKLQJ
QHWZRUN

Figure 7.58: Matching based on an L-section.

Figure 7.59 explains how the proper value of the inductor can be found using
the Smith chart.

Γi

Γr

Yn1=0.25+j0.785 Zn1=0.37-j1.16
Yn2=1-j1.31 Zn2=0.37+j0.48

Figure 7.59: Adding an inductor to the load.

332 Chapter 7. Transmission Lines and Impedance Matching

In Figure 7.59, we record the corresponding load impedance on the chart as

Zn1 = 0.37 + j1.16. Now we turn from point 1 on the constant resistance circle
(R = 0.37) clockwise until we intersect the constant conductance circle (G = 1)
at 1 − j1.31, point 2. Here we record the corresponding impedance value of
Zn2 = 0.37 + j0.48 on the chart. As such, the required series reactance to be added
to reach point 2 would be j0.48 − (− j1.16) = j1.64. Now to compute the required
parallel susceptance, we turn on the constant conductance circle (G = 1) clockwise
from point 2 to point 3, by adding a susceptance value of j1.31, where we reach
the center of the chart as shown in Figure 7.60.

Γi

3
Γr

Yn1=0.25+j0.785 Zn1=0.37-j1.16
Yn2=1-j1.31 Zn2=0.37+j0.48
Yn3=1 Zn3=1

Figure 7.60: Adding a capacitor to the load to reach the point 3 from
point 2.

Now, we compute the required values of the series inductance and the parallel
capacitance as follows

Lω X̄L Z0 (0.48 − (−1.16)) × 50

X̄L = ⇒L= = = 5.2 nH (7.170)
Z0 ω 2π × 2.5 × 109
and

Cω ȲCY0 1.31(0.02)
ȲC = ⇒C = = = 1.67 pF (7.171)
Y0 ω 2π × 2.5 × 109
The reader might notice that using the Smith chart he/she would need only simple
arithmetic calculations to design the matching circuit.
7.10 Smith Chart Mapping 333

Example 7.13 The structure depicted in Figure 7.61 can be shown to match 1 kΩ
to 50 Ω at 2 GHz. The relative permittivity is considered as unity. Verify this fact
using the Smith chart.

Ὓ Ȝ Ὓ Ȝ Ὓ Ȝ

S) = ȍ = ȍ = ȍ

ȍ

ȍ
Figure 7.61: The matching network in Example 7.13.

Solution:
We first record the load impedance on the Smith chart for the first section of the
transmission line:

Zn0 = 1000/500 = 2 (7.172)

From point 0 on the Smith chart, we turn clockwise, for 0.24λ (or 173◦ ) to reach
the point 1 and we record the input impedance as 0.501 − j0.047, at point 1. For
moving along the 300 Ω line, we normalized this impedance by the new reference
impedance of 300 Ω as

500
Zn2 = (0.501 − j0.047) × = 0.835 − j0.0783 (7.173)
300
We report this value on the chart as point 2. Now we turn clockwise about the
center of the chart by 0.24λ (or 173◦ ) to reach the point 3. We record the value of
the impedance at this point as 1.167 + j0.135. For moving along the 115 Ω line,
we normalized this impedance by the new reference impedance of 115 Ω as

300
Zn4 = (1.167 + j0.135) × = 3.047 + j0.351 (7.174)
115
We report this value on the chart as point 4. Now we turn clockwise about the
center of the chart by 0.35λ (or 252◦ ) to reach the point 5 on the chart. We record
the value of the impedance at this point as 0.445 + j0.569. We denormalize the
value of the impedance here to achieve

Z5 = (0.445 + j0.569) × 115 = 51.26 + j65.4 Ω (7.175)

334 Chapter 7. Transmission Lines and Impedance Matching

We normalize the above value of impedance by 50 Ω to achieve a new value of

normalized impedance at point 6:

(51.26 + j65.4)
Zn6 = = 1.024 + j1.308 (7.176)
50
This value is reported as point 6 on the chart. By adding a series capacitive reac-
tance of − j65.4 ( C11ω = 65.4), we approximately reach to the center of the chart at
point 7. The same procedure could be followed analytically as follows:

We first calculate the input impedance of the 500 Ω line as

2π
!
1000 + j500 tan

ZL + jZ0 tan (β `) λ 0.24λ
Z1 = Z0 = 500 2π

Z0 + jZL tan (β `) 500 + j1000 tan λ 0.24λ
= 250.74 –j23.57 (7.177)

and for the second section, we have

Z1 + jZ0 tan (β `)
Z3 = Z0
Z0 + jZ1 tan (β `)
2π
!
(250.74 –j23.57) + j300 tan λ 0.24λ
= 300 2π
(7.178)
300 + j (250.74 –j23.57) tan λ 0.24λ
= 350.32 + 40.427j

and finally, the input impedance of the 115 Ω section is equal to

Z3 + jZ0 tan (β `)
Z5 = Z0
Z0 + jZ3 tan (β `)
!
(350.32 + 40.427j) + j115 tan 2π
λ 0.35λ
= 115 (7.179)
115 + j (350.32 + 40.427j) tan 2π

λ 0.35λ
= 51.26 + j65.4

By adding the series 1.21 pF capacitor, the final input impedance becomes

Z7 = Z5 − j65.4 = 51.26 Ω (7.180)

which is a good match for a 50 Ω source.

7.10 Smith Chart Mapping 335

Γi

5 6

1 0 4
Γr
2 73

Zn0=2
Zn1=0.501-j0.047
Zn2=0.835-j0.078
Zn3=1.167+j0.135
Zn4=3.047+j0.351
Zn5=0.445+j0.569
Zn6=1.024+j1.308
Zn7=1.024≈1

Figure 7.62: The steps of matching in the circuit shown in Figure 7.61.

Example 7.14 Determine the matching of a 1 kΩ load to a 50 Ω source using

three section λ4 transformers, as an example similar to the previous one.
Solution:
To transform a 1000 Ω load to a 50 Ω input impedance, we can use three transmis-
sion lines with characteristic impedances Z0,1 and Z0,2 , and Z0,3 . If we want to
reduce the input impedance level by a fraction of β at each stage, we should have
1000 1000
1000 β β2
Z1 = Z2 = Z3 = = 50 Ω (7.181)
β β β

= = =

ȍ ȍ

= = =

Figure 7.63: Impedance matching using three sections of quarter wave

transformers.
336 Chapter 7. Transmission Lines and Impedance Matching

Therefore, we would have

r
3 1000
β= = 2.71 (7.182)
20
Consequently, we would have the following values for the characteristic impedances
and the input impedance of each section:
√
Z1 = 368.4 Z01 = 368.4 × 1000 = 607 (7.183)
√
Z2 = 135.7 Z02 = 135.7 × 368.4 = 223 (7.184)
√
Z3 = 50 Z03 = 50 × 135.72 = 82.4 (7.185)

Figure 7.64 shows the contour of this impedance matching on the Smith chart.

īL

= = = Ÿ
īU

Figure 7.64: The contours of impedance matching on the Smith chart using
three sections of quarter wave transformers.

There are two points to be mentioned in this example:

Point 1: Using a quarter wave transformer means travelling clockwise on a half-
circle, on the Smith chart, from the starting point impedance to the end-point
impedance.
7.10 Smith Chart Mapping 337

īL

% $
īU

Figure 7.65: Half-circle contour showing the quarter wave impedance trans-
formation on the Smith chart.

Point 2: Whenever the impedance

√
transformation contours are held within the
2
constant-Q locus, here Q ≤ 2 , the matching circuit would be wideband.

īL

&RQVWDQW4
ORFXV

4”
īU

√
2
Figure 7.66: The impedance transformation contours and Q = 2 locus on
the Smith chart.
338 Chapter 7. Transmission Lines and Impedance Matching

Example 7.15 The structure depicted in Figure 7.67 can be shown to match 1 kΩ
to 50 Ω.

50Ω C1
+ L 1000Ω
VS C2
- 50Ω

Figure 7.67: The lumped matching network at 1 GHz.

(a) Assuming we have matching at 1 GHz, calculate the values of C1 , C2 , and

L,using Figure 7.67. Choose the input quality factor of 10.
(b) If Q for the capacitors and inductors are equal to 80 and 60, respectively,
calculate the bandwidth.
Solution:
(a) Given an input quality factor of 10, let (C1 +C2 ) ω = 10 GS = 200 mf, so

C1 +C2 = 31.83 pF (7.186)

On the other hand

2
C1 50 1
= = (7.187)
C1 +C2 1000 20

Then
C2
= 3.47 (7.188)
C1

and

C1 = 7.12 pF,C2 = 24.7 pF (7.189)

We calculate the value of the required inductance as

C1 +C2
L= = 4.58 nH (7.190)
C1C2 ω 2
7.11 Conclusion 339

(b) Given the quality factors of the inductor and the capacitors, the parallel equiva-
lent resistance is equal to (verification of the following is left to the reader):

"
# " #
C1 2 C2 2

QC QC
RP = RL k (QL Lω) k 1+ k RS k 1+ = 331.9 Ω
C1 ω C2 C2 ω C1
(7.191)

The bandwidth can be then calculated as

ω0 ω0 Lω0 2
Q= ⇒ BW = = = 86.7 MHz (7.192)
2πBW 2πQ 2πRP

The following figure shows the frequency response and the bandwidth of this
matching circuit through ADS simulation.

4
Vout/VS(dB)

3
2
1 BW=86.7MHz
0
-1
1
0.95
0.96
0.97
0.98
0.99

1.01
1.02
1.03
1.04
1.05

Frequency (GHz)
Figure 7.68: The frequency response and the bandwidth of the matching
network (ADS simulation result).

7.11 Conclusion
Impedance matching is crucial in RF circuits, to transfer the maximum power from
the source to the load. The impedance matching can be achieved through the use of
reactive elements such as inductors, capacitors, or transformers. Transmission lines are
widely used in RF circuits as well. Using the transmission line equations or the Smith
chart, we can use them for impedance matching of the RF circuits as well. Note that
while using the Smith chart in the design of the matching networks, generally inductors
and capacitors are considered to be lossless to have a quick insight and a quick design
340 Chapter 7. Transmission Lines and Impedance Matching

procedure. Care should be taken while using the Smith chart not to approach the
open-circuit vicinity on the impedance chart and not to approach the short-circuit
vicinity on the admittance chart, in order to avoid significant errors in the matching
network designs or evaluations. Open-circuit stubs or short-circuit stubs can be used
as the reactive elements in the matching circuits. Quarter-wave transmission lines
can be used as impedance transformers in the matching circuits as well. Furthermore,
the combination of the lumped elements and transmission lines could be used in the
matching circuit networks in any case.

7.12 References and Further Reading

1. D. Pozar, Microwave Engineering, fourth edition, Hoboken, NJ: J. Wiley &
Sons, Inc., 2012.
2. S. Ramo, J.R. Whinnery, T. Van Duzer, Fields and Waves in Communication
Electronics, New York: J. Wiley & Sons, 1994.
3. R. Chi-Hsi Li, RF Circuit Design, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
4. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
5. F. Farzaneh, RF Communication Circuits (in Persian), Tehran: Sharif University
Press, 2005.
6. U.L. Rohde, A.M. Pavio, G.D. Vendelin, Microwave Circuit Design Using
Linear and Nonlinear Techniques, Hoboken, NJ: J. Wiley & Sons, Inc., 2005.
7. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
8. H.L. Krauss, C.W.Bostian, F.H. Raab, Solid State Radio Engineering, New
York, NY: J. Wiley & Sons, Inc., 1980.
7.13 Problems 341

7.13 Problems
Problem 7.1 Assume that a transmission line with a characteristic impedance of Z0
is terminated to 75 Ω. If SW R = 1.5, determine the characteristic impedance, Z0 .
Problem 7.2 Consider the circuit shown in Figure 7.69. Find the reflection coeffi-
cient, the input impedance Zin (λ /8), and SWR. Also, find the voltage and the current
phasors at the source and the load sides. What is the delivered power to the load?

100Ω Zin(λ/8)

+
10 0º Z0=50Ω ZL=100+j100Ω ZL
-
d=λ/8 d=0

Figure 7.69: A transmission line with the source and the load terminations.

Problem 7.3 Consider the amplifier shown in Fig. 7.70 with the input and output
matching networks. If the input impedance can be modeled as 15 KΩ k 15 pF and the
output equivalent circuit can be modeled as 410 Ω k 5 pF and the operation frequency
is 50 MHz, calculate the bandwidth at the input and at the output. Also calculate the
input matching circuit loss in dB at the center frequency. All capacitors have a quality
of factor of 100 at 50 MHz. Hint: The power delivered to the amplifier is the same
power delivered to the 15 kΩ.
C1 = 13 pF,C2 = 34 pF,C3 = C4 = 28 pF
L1 = 436 nH(Q = 11), L2 = 336 nH(Q = 32)

ȍ & & & &

Y6 / Nȍ S) Y JPY ȍ S) / ȍ

=LQ =RXW

Figure 7.70: The circuit model for the amplifier.

Problem 7.4 Consider the load impedance at the point Z = (30+ j40) Ω on the Smith
chart and also the two matching networks shown in Figure 7.71. Plot the matching
circle paths on the Smith chart, and estimate the input impedance, and then compare
it to your analytical computations. The operating frequency is 1 GHz. Is there any
deficiency in these matching networks?
342 Chapter 7. Transmission Lines and Impedance Matching

22.5nH 50Ω 62.5Ω 2.5pF

5pF Z 6nH Z

Zin Zin

Figure 7.71: The circuits for input impedance evaluation.

Problem 7.5 We desire to match a load impedance Z = (200 + j50) Ω to 50 Ω. In

either of the matching networks depicted in Figure 7.72, determine the proper values
of matching components at 900 MHz. Use C2 to tune out the load’s inductive reactance.
Note that for the circuit (b) there isn’t a unique solution (several values of L and C can
satisfy the matching condition).

C1 C2

C2
L Z L Z
C1

(a) (b)

Figure 7.72: Two possible matching circuits for the specified load.

Problem 7.6 In the circuit shown in Figure 7.73, we desire to perform the matching
to the complex source impedance. Calculate the length of the line, `1 , the λ /8 stub
characteristic impedance, Z0,2 , and the type of the stub (open-circuit stub or short
circuit stub) for this purpose. The operation frequency is 1 GHz, and the effective
permittivity of the line is 3.

ȍ Mȍ

= ȍ
6WXE
96 Ȝ =/ M
= Ὓ

0DWFKLQJ
SODQH

Figure 7.73: The λ /8 single stub matching for a complex source impedance.
7.13 Problems 343

Problem 7.7 A 50 Ω load is connected to a quarter-wavelength T-line, cascaded by

a 75 Ω T-line of unknown length. Determine the length of the second T-line and the
characteristic impedance of the first T-line such that the input impedance at 1 GHz is
equal to 112.5 Ω. Neglect T-line losses (Note that there are two possible solutions).
Problem 7.8 Sketch the frequency response of the circuit of the problem 7.7 for
300 MHz–3 GHz and determine whether the input impedance is capacitive or inductive
at each frequency. Determine the input impedance at f = 0.3, 0.5, 1, 1.5, 2.5, 3 GHz.
Problem 7.9 In the circuit of problem 7.7, assume that the input source has an
impedance of 112.5 Ω and a source voltage of 2 V and is operating at 3 GHz. Determine
output voltage on the 50 Ω load. Note that the transmission line length is one-fourth of
the wavelength at 1 GHz.
Problem 7.10 The output impedance of a ceramic filter is 50 Ω and the input
impedance of an LNA can be represented by 900 Ω k 0.5 pF at 900 MHz.
1. Design a matching network consisting of two capacitors and one inductor. The
acceptable range for the inductor is 1 − 8 nH and note that only capacitors larger
than 500 fF are allowed. You might choose an inductor of 6 nH with a typical
quality factor of 60 which is a relatively high achievable value in the range of
1 − 8 nH. Noting that the Q of the capacitors is typically larger than 200 and
quite larger than that of the inductor, find the loss of the matching network.
2. In practice, if implemented on a chip, the inductor will have a Q as small as 5.
Find the loss in this case as well.
3. What is the difference between the bandwidths of the circuit in part 1 and
part 2?

%LDV
FLUFXLWU\

&
/
&HUDPLF
ILOWHU &
ȍ__I)

Figure 7.74: The matching circuit for the ceramic filter.

Problem 7.11 The VSWR in a lossless T-line terminated by an unknown load is
3. The distance between the two successive voltage minima is 20 cm, with the first
minimum occurring at the distance of 5 cm from the load. The characteristic impedance
of the line is equal to 50 Ω.
1. Find the reflection coefficient and the load impedance, ZL .
2. What a pure resistive load could be put at the T-line termination through which
and using a minimum length T-line, one can reach to the same load impedance,
ZL ? (Specify the amount of rotation required on the Smith chart.)
Problem 7.12 Determine the distance d0 , and the short-circuit stub length ` such that
the input impedance in Figure 7.75 becomes 50 Ω? Both the T-line and the short-circuit
344 Chapter 7. Transmission Lines and Impedance Matching

stub have a characteristic impedance of 50 Ω. Express the lengths as fractions of the

wavelength.

d0

Z0=50Ω ZL=35-j47.5
l

Zin

Figure 7.75: The single stub matching circuit.

Problem 7.13 Determine the values of `A and `B in Figure 7.76 such that the input
is matched to 50 Ω. Consider all the T-lines are of 50 Ω characteristic impedance. Note
that X could be either a short circuit or an open circuit.

λ/8

Z0=50Ω
ZL=60+j80
lB
50Ω

X
lA

Figure 7.76: The double stub matching circuit.

Problem 7.14 Assuming a lossless 50 Ω line and the load impedance in the circuit
depicted in Figure 7.77, calculate the power delivered to the load. Hint: calculate first
the available power of the source and then the input reflection coefficient.

Z0

100Ω
+V 50Ω ZL=100+j100
5

d=λ/8

Figure 7.77: Determination of the delivered power to the load through a T-line.
7.13 Problems 345

Problem 7.15 A lossless line is terminated to a resistive 100 Ω load. If the reflected
voltage at the load side is V − (z = 0) = j Volts and the total current passing through
the load is equal to I = j (0.04) Amperes, determine the characteristic line impedance
Z0 (Fig. 7.78).

I(Z)

+
V(Z) Z0 100Ω
-

l
Z=- l Z=0

Figure 7.78: The characteristic impedance determination through the current

and the voltage phasors.

Problem 7.16 In a lossless 50 Ω T-line, the voltage phasor at a distance of λ /4

from the load is equal to (25 − j25) mV and the current at this point is equal to
(0.5 − j1.5) mA.
1. Determine the reflection coefficient at this point.
2. Calculate VSWR on this line.
3. What is the load impedance at the line termination?

Problem 7.17 In the lossless T-line depicted in Figure 7.79 which is terminated to
150 Ω, the voltage phasor at endpoint of the line is V (z = 0) = j3 V.
1. Determine the complex functions Γ (z) ,V + (z) ,V − (z) along the line.
2. Determine the complex functions Z (z) ,V (z) , I (z) along the line.
3. Determine the values of the functions found in parts (1) and (2) at z = −1 m.

I(z) β=π/2 (rad/m)

+
V(z) Z0=50Ω 150Ω
-
z=-1m z=0

Figure 7.79: The circuit for determination of the incident and the reflected
voltage phasors.

Problem 7.18 In the circuit depicted in Figure 7.80, compute Z(−`) as a function
of the T-line’s length and plot the results in two separate curves expressing the real and
the imaginary parts. Also, calculate the reflection coefficient at the points shown in the
figure (at the input, this value can be expressed in terms of `, where 0 < ` < λ2 ).
346 Chapter 7. Transmission Lines and Impedance Matching

l λ/4

Z(-l )
Z0=50Ω Z0=75Ω
25Ω

Γ Γ Γ

Figure 7.80: The circuit for reflection coefficient computation.

Problem 7.19 In the circuit depicted in Figure 7.81, we wish to perform the impedance
matching between a 100 Ω source and a 1000 Ω load using an ideal capacitor and an
ideal inductor at 1 GHz. Determine the required values of L, C, and the corresponding
Q of the circuit. Sketch the frequency response (| VVout |) of the circuit as well.
in

0DWFKLQJ
FLUFXLW
ȍ 9RXW
/
YLQ & Nȍ

Figure 7.81: The circuit for L-section impedance matching.

Problem 7.20 Calculate the values of inductors and capacitors to achieve impedance
matching between 100 Ω source and 1000 Ω load considering a load’s L-section Q
factor of 10 at 1 GHz.

0DWFKLQJFLUFXLW
ȍ / /
9RXW
& & ȍ
YLQ

5HT

Figure 7.82: The π matching network.

Problem 7.21 Consider a DC source is connected to a lossless air line of 75 Ω

characteristic impedance as in Figure 7.83. Draw the transient traveling waves along
the line as a function of time.

50ȍ t=0 Z0=75ȍ

" =3cm
VDC=1V +- 150ȍ

Figure 7.83: The circuit for transient voltage determination.

7.13 Problems 347

Problem 7.22 An air line is depicted in Figure 7.84 which is loaded by an RLC
circuit. Draw the input reflection coefficient about 5 GHz (e.g., from 4.95 GHz to
5.05 GHz) on the Smith chart. What would be the equivalent circuit of this network
then?

L
L=3.186nH
Z0=50Ÿ
r=1Ÿ r
" =15mm C=318fF
C

īin

Figure 7.84: The circuit for impedance inversion.

8. Scattering Parameters

8.1 Representation of Two-Port Networks

In order to characterize a linear two-port network, the measured parameters of the
transfer functions are required. Two-ports networks are characterized by such param-
eters as Z, Y, G, H, and T which provide a basic understanding of a network function.
These parameters are mostly used at lower frequencies; furthermore, they entail some
difficulties in their measurement at higher frequencies. The most significant drawback
of these parameters is that they need short- and open-terminations measurements which
are not easily realizable at microwave and millimeter-wave frequencies. That’s to say
a short length of any wire would be equivalent to a small inductor and any open circuit
at the end of a transmission line would represent a small capacitance. S-parameters
have already been introduced in microwave circuit measurement and design as well
as millimeter-wave application. Being based on the electromagnetic wave propagation
model, S-parameters provide a comprehensive account of the circuit properties. In
the next few sections, we first review common circuit parameters, and then introduce
S-parameters.

8.1.1 Common Circuit Parameters of Two-Port Networks

A generic two-port network is depicted in Figure 8.1. The matrix representation of this
two-port network parameters can be written as one of the following

v1 z11 z12 i1
= (8.1a)
v2 z21 z22 i2

i1 y y12 v1
= 11 (8.1b)
i2 y21 y22 v2

v1 h h12 i1
= 11 (8.1c)
i2 h21 h22 v2
350 Chapter 8. Scattering Parameters

L L

7ZRSRUW
9 9

QHWZRUN

Figure 8.1: A generic two-port network.

i1 g g12 v1
= 11 (8.1d)
v2 g21 g22 i2

v1 A B v2
= (8.1e)
i1 C D −i2

The five above parameters can be easily measured at low frequencies by open- or
short-circuiting the network. Example 8.1 provides a better insight into this issue.

Example 8.1 Depicted in Figure 8.2 is a resistive two-port network. Derive the
Z-parameters according to Equation 8.1a.

=$ =% =$ =%

L =& Y Y =& L

Figure 8.2: A resistive two-port and Z-parameters measurement.

Solution:
It follows from Equation 8.1a that
v1
z11 = i =0 = ZA + ZC (8.2a)
i1 2

v1
z12 = i =0 = ZC (8.2b)
i2 1

v2
z21 = i =0 = ZC (8.2c)
i1 2

v2
z22 = i =0 = ZB + ZC (8.2d)
i2 1

8.1 Representation of Two-Port Networks 351

9L 9L

9U 7ZRSRUW 9U

GHYLFH

Figure 8.3: Two port S-parameter matrix concept.

8.1.2 Scattering Parameters

Scattering parameters, or simply S-parameters, are defined according to the wave
behavior of the signal and unlike low-frequency parameters, do not require open-circuit
or short-circuit termination in their measurement. S-parameters can be obtained by
terminating the circuit with the reference impedance (e.g., 50 Ω). A generic microwave
two-port is shown in Figure 8.3. As depicted in Figure 8.3, the incident waves at ports 1
and 2 are denoted by Vi1 and Vi2 , respectively. The reflected waves at ports 1 and 2
are denoted by Vr1 and Vr2 , respectively. For a linear two-port, there is always a linear
relation between these four parameters as
Vr1 = ρ11Vi1 + τ12Vi2 (8.3a)
Vr2 = τ21Vi1 + ρ22Vi2 (8.3b)
Here, ρ11 is the reflection coefficient at port 1 once Vi2 = 0 (port 2 is terminated by a
matched load).
τ21 is the forward transmission coefficient once Vi2 = 0.
ρ22 is the reflection coefficient at port 2 once Vi1 = 0 (port 1 is terminated by a matched
load).
τ12 is the reverse transmission coefficient once Vi1 = 0.
Hence, the matrix representation of the network, relating the incident and the reflected
waves at the output and the input ports, can be denoted in a matrix form by

Vr1 ρ11 τ12 Vi1
= (8.4)
Vr2 τ21 ρ22 Vi2
The normalized incident and reflected waves can be defined in the following manner
Vi1 Vi2
a1 = √ , a2 = √ (8.5a)
Z0 Z0
Vr1 Vr2
b1 = √ , b2 = √ (8.5b)
Z0 Z0
where Z0 is the reference (the matched load) impedance. Consequently, a and b will
have a dimension of square root of Watts. Furthermore, the incident power and the
reflected power at each port will be proportional to
1 1
Pi = ai a∗i = |ai |2 (8.6a)
2 2
1 1
Pr = bi b∗i = |bi |2 (8.6b)
2 2
352 Chapter 8. Scattering Parameters

The absorbed power of

the two-port
would be
Pabs = Pi − Pr = Pi 1 − |Γin |2 (8.7)

where Γin is the input reflection coefficient of the two-port. The standard representation
of Equation
8.4is given by
b1 S11 S12 a1
= (8.8)
b2 S21 S22 a2
which is widely referred to as the S-parameters matrix. As with the other matrix
representations of circuits, each entry carries an interpretation of its own. S11 is the
input reflection coefficient once the output is terminated by the reference impedance,
S22 is the output reflection coefficient once the input is terminated by the reference
impedance, S21 is the forward transmission coefficient once the output is terminated
by the reference impedance, and S12 is the reverse transmission coefficient once the
input is terminated by the reference impedance. Each of the entries of the [S] matrix
can be derived individually
as
Vr1 b1
S11 = = (8.9a)
Vi1 Vi2 =0 a1 a2 =0

Vr1 b1
S12 = = (8.9b)
Vi2 Vi1 =0 a2 a1 =0

Vr2 b2
S21 = = (8.9c)
Vi1 Vi2 =0 a1 a2 =0

Vr2 b2
S22 = = (8.9d)
Vi2 Vi1 =0 a2 a1 =0
Equations 8.9a–8.9d also explicitly indicate how each one of the parameters can be
measured. To measure S11 , for instance, one needs to measure the ratio of the reflected
wave of port 1 to the incident wave of port 1 while the other ports are terminated by
the reference impedance. A 5-port network is depicted in Figure 8.4. The scattering
parameters for this network can be written as
b1 S11 S12 S13 S14 S15 a1
    
b2  S21 S22 S23 S24 S25  a2 
b3  = S31 S32 S33 S34 S35  a3  (8.10)
    
b  S
41 S42 S43 S44 S45
 a 
4 4
b5 S51 S52 S53 S54 S55 a5

Port 1

Port 2 Port 5

Device

Port 3 Port 4

Figure 8.4: Illustration of a 5-port network.

8.1 Representation of Two-Port Networks 353

Example 8.2 A two-port network is depicted in Figure 8.5. Determine the

S-parameters.

Vi1 8.56 8.56 Vi2

Z1 + Z2
Vr1 Vr2
141.8 Vo
Z3 -

Figure 8.5: A resistive two-port network.

Solution:
Using Equation 8.9a–8.9d, it follows that

Vr1 Zin − Z0
S11 = =ρ = (8.11)
Vi1 Vr2 =0 Zin + Z0

Terminating the output by the reference impedance (50 Ω), the input impedance is
given by

Zin = Z1 + [Z3 k (Z2 + Z0 )] (8.12)

= 8.56 + [141.8(8.56 + 50)/(141.8 + 8.56 + 50)] = 50 Ω

Hence,

50 − 50
S11 = =0 (8.13)
50 + 50
suggesting that we have matching at the input. Due to symmetry, S22 will also
assume a value of zero. Given the matching at the output (note that the reflected
wave at the output is zero), it follows that

(Z2 + Z0 ) k Z3 Z0 Z0
Vt2 = V2 = V1 = Vo
(Z2 + Z0 ) k Z3 + Z1 Z2 + Z0 Z2 + Z0

41.44 50
= V1 = 0.707 V1
41.44 + 8.56 50 + 8.56
(8.14)

Using the symmetry of the circuit, S12 = S21 = 0.707. Thus, the [S] matrix is
given by

0 0.707
[S] = (8.15)
0.707 0
354 Chapter 8. Scattering Parameters

It can be proved that, in general, Z-parameters can be converted to S-parameters,

using the following transforms

(Z11 − Z0 )(Z22 + Z0 ) − Z12 Z21

S11 = (8.16a)
∆
2Z0 Z12
S12 = (8.16b)
∆
2Z0 Z21
S21 = (8.16c)
∆
(Z11 + Z0 )(Z22 − Z0 ) − Z12 Z21
S22 = (8.16d)
∆
∆ = (Z11 + Z0 )(Z22 + Z0 ) − Z12 Z21

Example 8.3 Find the S-parameters for the circuit depicted in Figure 8.6 at
1 GHz.
Solution:
It follows from Figure 8.6 that

1
Zin = R|| + 50 = 75 − j25 (8.17)
Cs

hence,
Zin − Z0
S11 = = 0.277∠ − 33.7◦ (8.18)
Zin + Z0

Zin
50Ω 50Ω 50Ω

+
+
Vs1 3.2pF Vo2

(a)
Zout
50Ω 50Ω 50Ω

+
+
Vo1 3.2pF Vs2

(b)

Figure 8.6: A low-pass filter for S-parameter calculation.

8.1 Representation of Two-Port Networks 355

The output impedance can also be calculated as

1
Zout = 2R|| = 20 − j40 (8.19)
Cs

yielding

Zout − Z0
S22 = = 0.624∠ − 97◦ (8.20)
Zout + Z0

The forward gain and the reverse gain of the circuit can also be computed in a
similar manner as
1

VO2 2 Cs ||R
S21 = = 1 = 0.554∠ − 33.7◦ (8.21)
VS1 /2 Cs ||R + 2R

and

2 1 ||2R

VO1 R
S12 = = 1 Cs = 0.554∠ − 33.7◦ (8.22)
VS2 /2 Cs ||2R + R R + R

Example 8.4 Assume that in the oscillator depicted in Figure 8.7, an inductor
is tied to the base of the bipolar transistor, Q. The S-parameters of the two-port at
1 GHz have been measured as S11 = 1.8∠100◦ , S21 = 2.2∠−140◦ , S12 = 0.7∠140◦ ,
and S22 = 1.1∠ − 100◦ .
(a) Determine the maximum value for Rs so that the oscillation occurs.
(b) If L is changed in such a way that the input reflection coefficient becomes
Γin = −2, recalculate the maximum value of Rs .

ℓ=0.082λ
RS Z0=50Ω

L R=50Ω C=3.8pF
Γin ZL

Figure 8.7: An oscillator with source impedance for S-parameter calculation.

356 Chapter 8. Scattering Parameters

Solution:
(a) Using Equation 7.72, the load impedance can be calculated as
 
1
R|| jCω + jZ0 tan (β `)
ZL = Z0   = 16.11 –j0.0496 (8.23)
1
Z0 + j R|| jCω tan (β `)

The load reflection coefficient becomes

ZL − Z0
ΓL = = –0.513 –j0.0011 (8.24)
ZL + Z0

As we had from Equation 8.8

b1 = S11 a1 + S12 a2 (8.25)

or
a2
Γin = S11 + S12 (8.26)
a1

and as we had from Equation 8.8

b2 = S21 a1 + S22 a2 (8.27)

a2
Given b2 = ΓL , one can write

a2
= S21 a1 + S22 a2 (8.28)
ΓL

Therefore,

a2 S21
= 1
(8.29)
a1 ΓL − S22

a2
Replacing a1 in Equation 8.26, the input reflection coefficient can be computed as

S21 S12 ΓL
Γin = S11 + (8.30)
1 − S22 ΓL

or Γin = −0.946 + j1.38. This reflection coefficient corresponds to an impedance

value of

1 + Γin
Zin = Z0 = –15.83 +j24.26 (8.31)
1 − Γin

We can then deduce that Rs should be less than 15.83 Ω for the oscillation to occur.
8.2 Measuring S-Parameters Using a Network Analyzer 357

(b) The corresponding input impedance should first be calculated from the
given reflection coefficient as

Zeq 1+Γ 1−2 1

= = =− (8.32)
Z0 1−Γ 1+2 3

For the oscillation to start, Rs should be less than the absolute value of the negative
resistance, i.e.,

1
RS < Z0 = 16.67 Ω (8.33)
3

8.2 Measuring S-Parameters Using a Network Analyzer

(For Advanced Readers)
In this section, we turn our attention to the important and practical issue of measuring
S-parameters using a network analyzer. As you may already know, the numerous
sources of error, namely, measurement device error and nonidealities, which specif-
ically emerge at higher frequencies need some extent of calibration. We first focus
on how a network analyzer operates and later will introduce a calibration technique
based on electrical delay lines. Finally, a relatively more accurate technique will be
introduced in order to measure the two-port S-parameters.

8.2.1 Operation of a Network Analyzer

Consider Figure 8.8, where the conceptual block diagram of a network analyzer is
illustrated. First, assume we are to measure S-parameters from the port 1 (S11 and S21 ).
The device will then switch automatically so that the signal source is connected to port 1.
The three resistors in Figure 8.8 simply serve as a power splitter, after which the divided
signals are identical in phase and in amplitude. The amplitude and the phase of the
direct signal are recorded using a detector at the output A1 , providing the phase and
the amplitude of the signal source as the reference. The other part of the signal is fed
through the port 1 to the DUT. Part of this signal is reflected back by the DUT at the
port 1 and the other part of it passes through the DUT to the port 2. The reflected signal
is measured using a directional coupler and its amplitude and phase are recorded at the
output B1 . The signal passing through the DUT is measured at the ouput B2 .
The ratio of the reflected signal from the DUT to the incident reference signal at
the DUT gives in S11 and the ratio of the output signal at B2 of the DUT to the incident
signal gives in S21 . Now to measure S22 and S12 , the signal source is switched to the
port 2 and the port 1 is loaded by the reference impedance. As such, by the same
procedure, the output reflection coefficient (S22 ) and the reverse gain of the device
(S12 ) are measured.
The network analyzer system takes into account automatically the losses in the
path of the signal, the coupling coefficient of the directional couplers, and the phase
changes due to the transmission line lengths.
358 Chapter 8. Scattering Parameters

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Figure 8.8: Conceptual block diagram of a network analyzer.

Therefore, all the scattering parameters can be evaluated using a network analyzer.
The measurements, however, are subject to errors which may stem from numerous
sources, as discussed earlier. In the next section, we discuss techniques to mitigate
these errors.

8.2.2 Calibration Using Electrical Delay

One of the sources of error is the cables connecting the DUT and the network analyzer.
In order to obtain the S-parameters accurately, one should compensate for the effect of
delay and attenuation of these cables. To better understand this effect, assume that the
length of the cable used for the reference signal amplitude measurement (A1 ) might be
smaller than that of the transmission line used for transmitting the signal to the device.
This difference introduces a phase error in the measured S-parameters. Therefore, in
order to make a correct comparison, an additional delay equal to the delay which the
signal experiences from the source to the DUT should be added to the source signal
path. This will provide a correct and free of error measurement.

8.2.3 Quiescent Point bias Circuit

Another valuable feature of a network analyzer is that it enables us to provide the
quiescent bias point directly to the circuit. As depicted in Figure 8.8, this is achieved
using an inductor along with a decoupling capacitor which might be mounted inside a
network analyzer. Interestingly, as the bias is provided by the inductor or RF choke
(RFC), it does not affect the S-parameter readings at high frequencies (as the RFC is
open circuit at higher frequencies).
8.2 Measuring S-Parameters Using a Network Analyzer 359

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SODQH SODQH

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D

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Figure 8.9: Calibration circuits needed in the calibration process for a network
analyzer to measure the two-port S-parameters of the DUT.

8.2.4 One-Port and Two-Port Calibration for Short Circuit, Open Circuit, and
the Characteristic Impedance
Calibration is of great importance if a network analyzer is to accurately measure an
unknown impedance. This can be achieved by using components which simulate the
behavior of an open circuit, a short circuit, or reference impedance. After calibration,
only a slight difference can be observed between the real and the measured parameters.
If carried out for only one port, the above procedure can only provide the input or the
output matching accurately. To measure the device’s gain or the isolation, however, the
procedure should be performed for both ports. The calibration procedure is illustrated
in Figure 8.9.
Consider we intend to measure the S-parameters of a transistor as depicted in
Figure 8.9(a) where the transistor is accessed through the ports of the network analyzer
with two transmission lines with the lengths `1 and `2 , respectively.
As in Figure 8.9(b) a through-line with a length of `1 +`2 is realized, and it is referenced
as S21 = 1∠0, in order to measure the parameters S12 and S21 with a correct phase.
As in Figure 8.9(c), two open circuits are realized at the ports 1 and 2 of the network
analyzer through two transmission lines with the lengths `1 and `2 , respectively. As
such, here, at port 1, the reflection coefficient is referenced as S11 = 1∠0, and at port 2,
the reflection coefficient is referenced as S22 = 1∠0.
As in Figure 8.9(d), two short circuits are realized at ports 1 and 2 of the network
analyzer through two transmission lines with the lengths `1 and `2 , respectively. As
such, here, at port 1, the reflection coefficient is referenced as S11 = 1∠180◦ , and at
360 Chapter 8. Scattering Parameters

port 2, the reflection coefficient is referenced as S22 = 1∠180◦ .

As in Figure 8.9(e), two matched loads are realized at ports 1 and 2 of the network
analyzer through two transmission lines with the lengths `1 and `2 , respectively. As
such, here, at port 1, the reflection coefficient is referenced as S11 = 0, and at port 2,
the reflection coefficient is referenced as S22 = 0.
Note that in all the five prototype circuits, depicted in Figure 8.9, used for calibration,
the connectors and the printed circuits should be of the same type and the same fabrica-
tion. Through this calibration procedure, the length of the device is taken into account
and any error associated with connector mismatches is deduced.

Example 8.5 In S11 measurements, the network analyzer is programmed to use

the reference plane C1 , and the Smith chart given in Figure 8.10 (left) is resulted for
open-circuit measurement. When the circuit is connected to the network analyzer,
the plot given in Figure 8.10 (right) is obtained.
(a) If the S11 of the transistor itself is to be measured, explain the errors in this
measurement.
(b) What can be done to obtain the correct plot of S11 ?

Solution:
(a) The error is equal to the delay generated by a reference transmission line with
the length of λ /8, that is about 90◦ , in reflection (assuming a lossless T-line).
(b) For proper measurement, the delay resulting from the transmission line should
be deduced from the phase of S11 . In other words
0
S11 = S11 e−j2β l (8.34)

Ɛ Ȝ
= ȍ

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5HIHUHQFH 5HIHUHQFH
SODQH SODQH

6
6’

2SHQFLUFXLW
0HDVXUHPHQW
FDOLEUDWHGDW&
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Figure 8.10: S-parameter measurement.

8.2 Measuring S-Parameters Using a Network Analyzer 361

Device Under Test (DUT)

50Ω
P1 V1 P4
+
vS P2 0.1mS×V1 P3 50Ω
-

Figure 8.11: The proposed model for the Device Under Test.
0
where S11 is the measured reflection coefficient at C1 reference plane, and S11
is the measured reflection coefficient at C2 reference plane.

0
S11 = S11 ej2β l (8.35)

In other words, the measured plots of S11 at C1 plane should be rotated 90◦ counter
clockwise to obtain the value of S11 at C2 reference plane.

Example 8.6 The S-parameters (S11 and S22 ) for the circuit shown in Figure 8.11
in the frequency range of 500 kHz–3 GHz have been measured as

S11,A = −0.111 at 500 kHz (8.36)

S11,B = 0.441∠158◦ at 3 GHz (8.37)
S22,C = 0.818 at 500 kHz (8.38)
S22,D = 0.807∠−11.5◦ at 3 GHz (8.39)

Sketch a reasonable and proper equivalent circuit for this network. The boxes
contain passive devices.

Solution:
For an RF transistor, the input and the output impedances at 500 kHz are almost the
same as the DC impedances. Given the fact that S11 is real and is equal to −0.111,
then it could be deduced that a real impedance of the following value is seen at the
input at low frequencies:

1 + S11
Zin = Z0 = 40 Ω (8.40)
1 − S11

As the input impedance on the chart progressively becomes capacitive and finally be-
comes inductive, we suggest the input equivalent circuit as depicted in
Figure 8.13. This means rπ = 40 Ω.
362 Chapter 8. Scattering Parameters

īL

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īU
'

3RLQW$ 6#0+]

3RLQW% 6#*+] ž
3RLQW& 6#0+]
3RLQW' 6#*+] ž

Figure 8.12: Impedance matching on Smith chart.

The input impedance at 3 GHz becomes

1 + S11
Zin = Z0 ≈ 20 + j8.27 (8.41)
1 − S11

Given the equivalent circuit, one can write

rπ
rin = = 20 (8.42)
1 + (ωrπ Cπ )2

Then

Cπ ≈ 1.33 pF (8.43)

Now given the equivalent circuit, one can write

jrπ2 Cπ ω
Xin = jLb ω − ≈ j8.27 (8.44)
1 + (ωrπ Cπ )2

Then

Lb ≈ 1.5 nH (8.45)
8.2 Measuring S-Parameters Using a Network Analyzer 363

Lb Lc
+

Cπ rπ Vx gmVx ro Co

Figure 8.13: The proposed equivalent circuit for the measured S-parameters
of the transistor.

By the fact that S22 (the output impedance) is real at 500 kHz, again one could
say that the output impedance at DC is almost

1 + S22
Zout = Z0 = 500 Ω (8.46)
1 − S22

It is seen that S22 becomes gradually capacitive and its amplitude is slightly reduced,
so we suggest the output equivalent circuit as depicted in Figure 8.13. This means
ro = 500 Ω.
At 3 GHz, the output impedance becomes

1 + S22
Zout = Z0 ≈ 250 − j231.2 (8.47)
1 − S22

Given the equivalent circuit, one can write

ro
= 250 (8.48)
1 + (ωroCo )2

Then

Co ≈ 0.106 pF (8.49)

Now given the equivalent circuit, one can write

jro2Co ω
jLc ω − ≈ − j231.2 (8.50)
1 + (ωroCo )2

Then

Lc ≈ 1 nH (8.51)

364 Chapter 8. Scattering Parameters

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5)&
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Figure 8.14: The effect of transmission line on the S-parameters.

Example 8.7 Derive the S-parameters for the transistor shown in Figure 8.14.
The S-parameters measured at ports one and two are given at 1 GHz as S11 =
0.3∠ − 20◦ , S21 = 2∠20◦ , S12 = 0.02∠ − 20◦ , and S22 = 0.15∠ − 62◦ . The T-lines
are lossless.

Solution:
The new S11 is given by
0 4π λ
S11 = S11 ej2β l1 = S11 ej λ 10 = 0.3∠ (−20◦ + 72◦ ) = 0.3∠52◦ (8.52)

Similarly, S22 can be computed as

0 4π λ
S22 = S22 ej2β l2 = S22 ej λ 8 = 0.15∠ (−62◦ + 90◦ ) = 0.15∠28◦ (8.53)

It should be noted that forward gain and reverse isolation will also experience a
81◦ phase shift, yielding
0 2π λ
S12 = S12 ejβ (l1 +l2 ) = S12 ej λ ( 10 + 8 ) = 0.02∠ (−20◦ + 36◦ + 45◦ )
λ

= 0.02∠61◦ (8.54)
0 j 2π
λ ( 10 8 )
λ +λ
S21 = S21 e jβ (l1 +l2 )
= S21 e = 2∠ (20 + 36 + 45 ) = 2∠101◦
◦ ◦ ◦

(8.55)

Example 8.8 For the transistor model depicted in Figure 8.15, plot S11 in the fre-
quency range of 0 − 1 GHz on a polar coordinate, in 50 Ω reference impedance sys-
tem. Put a cross mark on the frequencies 50 MHz, 200 MHz, 500 MHz, 850 MHz,
1000 MHz.
8.2 Measuring S-Parameters Using a Network Analyzer 365

Z2
i1 Z1 2.4pF Z3
i2 i2-3Vx

+ Cx +
C1 C2
Port 1 400fF 75Ω Vx V2 -3Vx 100Ω 200fF Port 2 Z0
- -
Zin

Figure 8.15: Small-signal model of the transistor for S11 calculation.

Solution:
To compute S11 , we should first calculate the input impedance while the output is
loaded by Z0 . It can be found from Figure 8.15 that

Vx
i1 = + i2 (8.56)
Z1
or
Vx Vx −V2
i1 = + (8.57)
Z1 Z2

Having

V2 = (i2 − 3Vx ) ZL (8.58)

where ZL = Z3 k Z0 . Substituting the latter equation in the former, we obtain

1
!
1 1 Z −3
i1 = Vx + − 2 Z (8.59)
Z1 Z2 1 + Z 2
L

or
Vx 1
Zin = = 1
(8.60)
i1 1 Z2 −3
Z1 + Z12 − Z
1+ Z 2
L

S11 can be found as

1
1 − Z0
1 1 Z2 −3
Z1 + Z2 − Z
Zin − Z0 1+ Z 2
L
S11 = = 1
(8.61)
Zin + Z0 1 + Z0
1 1 Z2 −3
Z1 + Z2 − Z
1+ Z 2
L
366 Chapter 8. Scattering Parameters

īL

īU

3RLQW 6#0+] ž

3RLQW 6#0+] ž
3RLQW 6#0+] ž
3RLQW 6#0+] ž
3RLQW 6#0+] ž

Figure 8.16: The plot of S11 of the transistor model from 50 MHz to
1000 MHz.

where
1 1 1
Z1 = ||75 Ω, Z2 = , Z3 = ||100 Ω (8.62)
jω (400 fF) jω (2.4 pF) jω (200 fF)

The S11 plot is given as below

Example 8.9 For a transistor, the output circuit model is shown in Figure 8.17.
Compute S22 in the frequency span of 100 MHz − 1.5 GHz.

Solution:
S22 is given by

1
− Z0 1 − Z0 jco ω + r1o
jco ω+ r1o
S22 = 1
= (8.63)
+ Z0 1 + Z0 jco ω + r1o
jco ω+ r1o
8.2 Measuring S-Parameters Using a Network Analyzer 367

ro co
200Ω 500fF
Zout

Figure 8.17: Equivalent circuit for S22 modeling.

-4.00 0

(S22)(Deg)
|S22|(dB)

-4.25 -10

-4.50 -20

-4.75 -30

-5.00 -40
0.1 0.25 0.5 0.75 1 1.25 1.5
Frequency (GHz)

Figure 8.18: The amplitude and phase of S22 of the transistor.

S22 phase and amplitude behavior is depicted in Figure 8.18 from the above
computation.

Example 8.10 Two lossless transmission lines have been used to connect two
ports of a transistor on a PCB to two SMA connectors for S-parameter measure-
ments (consider the transmission lines as airlines). If the reference plane in test 1
has been calibrated for S11 and S22 , and assuming Zout = 25 − j50 and Zin = 10 at
500 MHz, determine the real input and output impedance of the transistor on the
Smith chart. (You may use the Smith software to do this.)

Solution:
We first derive the S-parameters considering the reference plane for test 1 as

Zin − Z0 10 − 50 2
S11 = = = − = 0.67∠180◦ (8.64)
Zin + Z0 10 + 50 3
Zout − Z0 25 − j50 − 50 1 − j8
S22 = = = = 0.62∠−82.9◦
Zout + Z0 25 − j50 + 50 13

The wavelength can be calculated as λ = c/ f = 60 cm, and hence the length of

the line is equal to λ /15. These two parameters at the test reference plane 2 will
become
0
S11 = S11 ej2β l = 0.67∠228◦ (8.65)
368 Chapter 8. Scattering Parameters

FP FP
60$ 60$
ȍ ȍ

7HVW 7HVW 7HVW

UHIHUHQFH UHIHUHQFH UHIHUHQFH
SODQH SODQH SODQH

Figure 8.19: The circuit used in Example 8.10.

īL

īU

3RLQW 6#0+] ž

3RLQW 6’#0+] ž

Figure 8.20: The input reflection coefficient, depicted on the Smith chart
0
[(1): S11 , (2): S11 ].

and
0
S22 = S22 ej2β l = 0.62∠−34.9◦ (8.66)

In another way, these parameters can be calculated as

0 0
! !
2π
Zin + jZ0 tan (β `) Zin + j50 tan 15
Zin = Z0 0 = 50 0 2π
= 10 (8.67)
Z0 + jZin tan (β `) 50 + jZin tan 15

0 0
By solving for Zin , we arrive at Zin = 11.89 − j21.19 and the reflection coefficient
becomes
0
0 Zin − Z0
S11 = 0 = 0.67∠228◦ (8.68)
Zin + Z0
8.3 Conversion of Network Matrices 369

īL

īU

3RLQW 6#0+] ž

3RLQW 6’#0+] ž

Figure 8.21: The output reflection coefficient, depicted on the Smith chart
0
[(1): S22 , (2): S22 ].

The same steps should be taken for the output impedance. Hence,
0 0
! !
Zout + jZ0 tan (β `) Zout + j50 tan 2π
15
Zout = Z0 0 = 50 0 = 25− j50 (8.69)
Z0 + jZout tan (β `) 50 + jZout tan 2π
15

0
and solving for the output impedance, it yields Zout = 83.77 − j96.6 and again the
output reflection coefficient can be computed as
0
0 Z − Z0
S22 = out
0 = 0.62∠−34.9◦ (8.70)
Zout + Z0

8.3 Conversion of Network Matrices

It is noteworthy that a linear two port can be characterized by either of the impedance
matrix, admittance matrix, or scattering parameters. Modern day network analyzers
while measuring the scattering parameters can compute online the [Z] and the [Y]
matrices as well. In Table 8.1, the conversion of all the three network matrices is
represented, so that a user can compute either of the two matrices once he/she has the
measurement results of one of the matrices.
370 Chapter 8. Scattering Parameters

Table 8.1: Conversion between two-port network matrices.

S Z Y
(Z11 −Z0 )(Z22 +Z0 )−Z12 Z21 (Y0 −Y11 )(Y0 +Y22 )+Y12Y21
S11 S11 ∆Z ∆Y
2Z12 Z0 −2Y12Y0
S12 S12 ∆Z ∆Y
2Z21 Z0 −2Y21Y0
S21 S21 ∆Z ∆Y
(Z11 +Z0 )(Z22 −Z0 )−Z12 Z21 (Y0 +Y11 )(Y0 −Y22 )+Y12Y21
S22 S22 ∆Z ∆Y

Z11 Z0 (1+S11 )(1−S22 )+S12 S21

(1−S11 )(1−S22 )−S12 S21 Z11 Y22
|Y |
2S12 −Y12
Z12 Z0 (1−S11 )(1−S 22 )−S12 S21
Z12 |Y |
2S21 −Y21
Z21 Z0 (1−S11 )(1−S 22 )−S12 S21
Z21 |Y |

Z22 Z0 (1−S11 )(1+S22 )+S12 S21

(1−S11 )(1−S22 )−S12 S21 Z22 Y11
|Y |

Y11 Y0 (1−S11 )(1+S22 )+S12 S21

(1+S11 )(1+S22 )−S12 S21
Z22
|Z| Y11
−2S12 −Z12
Y12 Y0 (1+S11 )(1+S22 )−S12 S21 |Z| Y12
−2S21 −Z21
Y21 Y0 (1+S11 )(1+S22 )−S12 S21 |Z| Y21

Y22 Y0 (1+S11 )(1−S22 )+S12 S21

(1+S11 )(1+S22 )−S12 S21
Z11
|Z| Y22
∆Z = (Z11 + Z0 ) (Z22 + Z0 ) − Z12 Z21 ; ∆Y = (Y11 +Y0 ) (Y22 +Y0 ) − Y12Y21 ; |Z| = Z11 Z22 − Z12 Z21 ; |Y | =
Y11Y22 −Y12Y21 ; Y0 = Z1
0

8.4 Conclusion
Scattering parameters are mainly used for high-frequency measurement of active and
passive devices. These parameters are measured using the network analyzer. Network
analyzers can distinguish between the incident and the reflected waves at the two
ports of the Device Under the Test (DUT). The scattering parameters are determined
with respect to a reference impedance. This reference impedance in most of the
measurement equipment is chosen to be 50 Ω. The input and the output reflection
coefficients of a device, i.e., S11 and S22 can normally be shown on the Smith chart,
while the forward gain S21 and the reverse gain S12 of a two-port are depicted on polar
or Cartesian coordinates. It is convenient to transform the scattering parameters into
impedance/admittance matrices and vice versa. An RF transistor S-parameters can be
measured, using a network analyzer, through a calibration procedure where the effects
of the interconnects can be canceled out.
8.5 References and Further Reading 371

8.5 References and Further Reading

1. D. Pozar, Microwave Engineering, fourth edition, Hoboken, NJ: J. Wiley &
Sons, Inc., 2012.
2. S. Ramo, J.R. Whinnery, T. Van Duzer, Fields and Waves in Communication
Electronics, New York: J. Wiley & Sons, 1994.
3. G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design., NJ:
Prentice-Hall, 1994.
4. U.L. Rohde, A.M. Pavio, G.D. Vendelin, Microwave Circuit Design Using
Linear and Nonlinear Techniques, Hoboken, NJ: J. Wiley & Sons, Inc., 2005.
372 Chapter 8. Scattering Parameters

8.6 Problems
Problem 8.1 Determine the S-parameters for the two-port network depicted in
Figure 8.22.

100Ω

50Ω 50Ω

λ/8 λ/8

Port 1 Port 2

Figure 8.22: The resistive/transmission line circuit for S-parameters

determination.

Problem 8.2 The input of a transistor is modeled as in Figure 8.23. Sketch S11 in a
50 Ω system on the Smith chart from 0 to 1 GHz.

L=34.5nH

rπ=1kΩ Cπ=0.7pF gmv1 rO CO

Figure 8.23: The circuit model for a transistor to compute S11 .

Problem 8.3 The input of a bipolar transistor at 1 GHz ◦

is modeled by an RLC
circuit as depicted in Figure 8.24. Here, S11 = 0.63∠ − 54 . A π network is used for
impedance matching to 50 Ω, where L1 = 7 nH.
9&&
7UDQVLVWRU
5)& LQSXWPRGHO
6
/E 6
ȍ &

=/ &) ȍ
/
Y6 &
Q+
9E

Figure 8.24: The input circuit for a BJT amplifier.

1. Find the proper values of CF and Lb in the model to give in the stated value of
S11 .
2. Determine C1 and C2 for the required matching.
3. If the input inductor loss is modeled by a series resistance of 5 Ω, and assum-
ing QC1 = QC2 = 100, estimate the bandwidth of the matching network and
calculate the matching circuit loss in this case, in dB.
8.6 Problems 373

Problem 8.4 Determine the S-parameters in a 50 Ω reference system, in the two

attenuator networks (a) and (b) shown in Figure 8.25.

50Ω 50Ω 70Ω 30Ω

Port1 100Ω Port2 Port1 100Ω Port2

(a) ( b)

Figure 8.25: Two T-section attenuator circuits.

Problem 8.5 The input of a transistor is modeled as either of the networks depicted
in Figure 8.26, plot S11 in a 75 Ω reference system on the Smith chart for each of the
three cases shown in the figure for the frequency range of 0 − 1 GHz (with steps of
100 MHz). Compare these three cases.

2.1nH

25Ω 10pF 25Ω 10pF 25Ω

S11 S11 S11

(a) (b) (c)

Figure 8.26: The transistors’ input equivalent circuits.

Problem 8.6 Considering the bipolar transistor model given in Figure 8.27, determine
the corresponding expressions for the S-parameters, in terms of the circuit parameters,
with a reference impedance of Z0 . First assume Cµ k rµ is negligible, and then repeat
the problem while taking into consideration their effect.

rμ

rbb’ cμ
B C
+
rπ cπ Vb’e gmVb’e ro
-

Figure 8.27: The equivalent circuit of the transistor to determine the

S-parameters.
374 Chapter 8. Scattering Parameters

Problem 8.7 Compute the S-parameters of the network depicted in Figure 8.28 at
2 GHz.

θ=90º 50Ω θ=90º

1.59pF 1.59pF

50Ω 50Ω

Figure 8.28: The RC section for S-parameters’ determination.

Problem 8.8 Find an expression for the two-port S-parameters for a reference
impedance of Z0 as shown in Figure 8.29. For which values of L and C, S11 and
S22 will tend to zero?

Z0 L Z0

Port1 C C Port2

Figure 8.29: The delay cell for S-parameters’ determination.

Problem 8.9 A transistor’s S-parameters have been measured through 2 mm length

line pads at 4 GHz. The substrate effective relative permittivity as in Figure 8.30 has a
value of 2. What are the S-parameters of the pure transistor?

3XUH
PP WUDQVLVWRU PP
6 ž

6 ž

6 ž
6 ž

Figure 8.30: The transistor S-parameters for de-embedding.

Problem 8.10 Determine the S-parameter of the cascaded chain of amplifiers as in

Figure 8.31.
8.6 Problems 375

Z0
Z0

Γi1 0 Γi2 0 Γi3 0

S1= S2= S3=
G1 Γo1 G2 Γo2 G3 Γo3

Figure 8.31: The cascaded chain of three unilateral amplifiers.

Problem 8.11 A pair of similar amplifiers are cascaded by two three dB 90◦ couplers
with the specified S-parameters as in Figure 8.32. Determine the overall S-parameters
between port 1 and port 2. What is the advantage of this architecture?

AMP

1' 2' 1" 2"

1
IN
Z0

3dB 3dB
coupler AMP coupler

4' 3' 4" 3" 2

OUT
Z0

0 2 2 0 0 2 2 0
j j
2 2 2 2
2 0 0 2 SA,11 SA,12 2 0 0 2
j j
2 2 2 2
S C= S A= S C=
2 2 2 2
j 0 0 SA,21 SA,22 j 0 0
2 2 2 2

0 2 2 0 0 2 2 0
j j
2 2 2 2

Figure 8.32: A pair of balanced amplifiers cascaded by two 90◦ , 3 dB couplers.

9. Amplifier Design Using S-parameters

9.1 Amplifier Design Using Scattering Parameters

In this chapter, we mainly focus on the analysis and basic design of microwave
transistor-based amplifiers using S-parameters usually available from the datasheet.
The most important design factors in microwave amplifiers include stability, power
gain, bandwidth, noise figure, dc biasing, and power consumption. The first amplifier
design step is choosing a proper transistor. Subsequently, using the measured S-
parameters, matching, gain, and stability factor can be evaluated accordingly. An
unconditionally stable transistor would not oscillate with a passive load and a passive
source. However, for potentially unstable transistors, specific measures should be
taken into account while terminating them to passive loads/sources using the required
stability contours on the Smith chart.

9.2 Specification of Amplifiers

A generic transistor amplifier can be completely characterized using these parameters:
(1) stability (absence of unwanted oscillations), (2) maximum power gain, (3) input and
output impedances, (4) the transducer gain, (5) optimum load and source impedances,
and (6) simultaneous conjugate matching.
It can be easily concluded that all the above parameters are subject to variations with
frequency or bias level, complicating the design of wide-band microwave amplifiers.
Finding a stable transistor in its proposed quiescent point can be considered as the
first step in the design procedure. The desired performance can be estimated using
S-parameters. Consider Figure 9.1, where the general case of a microwave amplifier is
depicted with its input and output matching circuits.
Contrary to the ordinary analog electronic circuits where the parameters such as
the voltage gain and the current gain are mostly evaluated and employed, in RF
communication circuits, the power gain is of most importance. The reason is that
378 Chapter 9. Amplifier Design Using S-parameters

=LQīLQ =RXWīRXW
ħ6

,QSXW 2XWSXW
(V PDWFKLQJ PDWFKLQJ
ħ/

$PSOLILHU
=VīV =/ī/

Figure 9.1: Illustration of the general case of a microwave amplifier with input
and output matching circuits.

in communication systems, the RF power is the most scarce quantity, and it should
compete with noise, so approximately in all RF stages, the power gain is the quantity
to be optimized. Let us now introduce the most important property of a microwave
amplifier, that is, its power gain. Three separate definitions are considered for the
power gain as follows.
(1) Transducer Power Gain is the power delivered to the load, ZL , divided by the
available power of the source, PAVS , i.e.,

PL GL |VL |2 |VL |2
GT = = 1 2
= 4G G
S L (9.1)
PAVS
4GS |IS | |IS |2

Here, GS is the source conductance, GL is the load conductance, VL is the load

voltage, and IS is the source’s short circuit currents. Here, if the source and the load
reflection coefficients are complex conjugate of the reflection coefficients of the input
and the output of the transistor, that is,

ΓL = Γout ∗ (9.2)

then the absorbed power of the load becomes equal to the available power of the output

PL = PAVO (9.3)

and if

Γin = Γs ∗ (9.4)

then the available power of the source will be absorbed by the input, that is,

PAVS = Pin (9.5)

In this case, the transducer gain will attain its maximum value. This is the simultaneous
conjugate match condition.
9.2 Specification of Amplifiers 379

In terms of device’s S-parameters and the source and the load reflection coefficients,
the transducer power gain can be expressed as

|S21 |2 1 − |ΓS |2 1 − |ΓL |2
GT = (9.6)
|1 − ΓS Γin |2 |1 − S22 ΓL |2

This is the most realistic definition of the power gain.

(2) Available Power Gain (APG) is the ratio of the output available power to the
power available from the source, and can be expressed as
1 2
PAVO 4GO |IO | GS |IO |2
GA = = 2
= (9.7)
PAVS 1 GO |IS |2
4GS |IS |

Here, GS is the source conductance, GO is the output conductance, IS is the source’s

short-circuit current, and IO is the output’s short-circuit current. If Γin = Γs ∗ , that is,
PAVS = Pin , then the APG will attain its maximum value.
In terms of device’s S-parameters and the source reflection coefficient, the APG can be
expressed as

|S21 |2 1 − |ΓS |2
GA = (9.8)
|1 − S11 ΓS |2 1 − |Γout |2

One can generally expect that

GT ≤ GA (9.9)

(3) Operational Power Gain is the ratio of the power absorbed by the load from the
network to the power delivered to the network from the source, which can be written
as

PL GL |VL |2 GL
GP = = = |AV |2 (9.10)
Pin Gin |Vin |2 Gin

Here, Gin is the input conductance, GL is the load conductance, VL is the load voltage,
Vin is the input voltage, and AV is the voltage gain. If ΓL = Γout ∗ , that is, PL = PAVO ,
then power gain will attain its maximum value. One can generally expect that

GT ≤ GP (9.11)

In case of simultaneous conjugate match, all these three quantities will converge to the
value, that is,

GPmax = GAmax = GTmax (9.12)

We shortly develop expressions for each one the above triple definitions in terms of
S-parameters.
380 Chapter 9. Amplifier Design Using S-parameters

9.3 Performance Parameters of an Amplifier

We have recognized thus far that the transducer power gain is dependent on the input
reflection coefficient, output reflection coefficient, and S-parameters, the power gain
(operational power gain) is dependent on output reflection coefficient and S-parameters,
and finally, the APG is dependent on the input reflection coefficient and S-parameters.
Another point of importance is the matching network in amplifiers which match the
input and the output impedances to a certain value, say 50 Ω.

9.3.1 Stability
Passive loads, in general, have a reflection coefficient with an absolute value less than
unity, whereas for active two-ports (such as biased transistors), S-parameters could be
such that the input and/or the output reflection coefficients can have an absolute value
larger than unity. In this case, the circuit can become potentially unstable. In other
words, this means the input resistance or the output resistance is negative, which can
lead to instability. That is |Γin | > 1, or |Γout | > 1. In case of a unilateral network, for
example, S12 = 0, the unstable case reduces to |S11 | > 1 and |S22 | > 1, each revealing
the presence of a negative input or output resistances.
Regarding the stability, one could say a two-port is unconditionally stable if the
input reflection coefficient’s absolute value is smaller than unity for all passive loads,
and the output reflection coefficient’s absolute value is smaller than unity for all passive
sources. Or in other words, if the real part of both the input and the output impedances
for all passive load impedances and for all passive source impedances are positive. We
should bear in mind that all the expressions used here are in the frequency domain,
and hence, they are valid only within a certain bandwidth. If a two-port network is
not unconditionally stable, there exists a combination of load and source impedances
that leads to a negative real part for the input or a negative real part for the output
impedances. In terms of the reflection coefficients the stability means, the input
reflection coefficient and the output reflection coefficient for passive loads/sources
should satisfy the following condition, i.e., for |Γs |<1 and |ΓL |<1, can be described as

S21 ΓL S12
|Γin | = S11 + ≤1 for all |ΓL | ≤ 1 (9.13)
1 − S22 ΓL

and

S21 Γs S12
|Γout | = S22 + ≤1 for all |ΓS | ≤ 1 (9.14)
1 − S11 Γs

Relations 9.13 and 9.14 suggest that if the load or the source terminations are
passive, the input and the output reflection coefficients should remain passive, that is,
with an absolute value less than unity. To check the stability condition, relations 9.13
and 9.14 can be solved by putting each of the left-hand sides of the inequalities equal to
unity. A two-port network is conditionally stable if there exists passive loads for which
the absolute value of the input reflection coefficient is greater than unity (|Γin | > 1),
and there exists passive sources for which the absolute value of the output reflection
9.3 Performance Parameters of an Amplifier 381

coefficient is greater than unity (|Γout | > 1). As such the concept of stability using
input and output reflection coefficients, the problem of stability can be easily handled,
taking into consideration the locus for |Γin | = 1, once the load impedance varies, and
the locus for |Γout | = 1 once the source impedance varies, on the Smith chart. It can be
shown that both loci are described by circles given by the following relations (These
circles correspond to relations 9.13 and 9.14, respectively, once the equality holds).
The locus in the source plane can be described by

|Γs −Cs |2 = rs 2 (9.15)

Equation 9.15 describes a circle on the Smith chart whose center is Cs and whose
radius is rs .
where

S S
12 21
rs = (9.16)

|S11 |2 − |∆|2

(S11 − ∆S22 ∗ )∗
Cs = (9.17)
|S11 |2 − |∆|2
and the locus in the load plane can be described by

|ΓL −CL |2 = rL 2 (9.18)

Equation 9.18 describes a circle on the Smith chart whose center is CL and whose
radius is rL , where

S S
12 21
rL = (9.19)

|S22 |2 − |∆|2

(S22 − ∆S11 ∗ )∗
CL = (9.20)
|S22 |2 − |∆|2
In Equations 9.16 and 9.20, ∆ is the S-matrix determinant.
∆ = S11 S22 − S12 S21 (9.21)
With S-parameters known at a particular frequency, using Equations 9.16 and 9.17, the
circle corresponding to |Γout | = 1 can be found on the source impedance plane (Smith
chart) and the circle corresponding to |Γin | = 1 can be found on the load impedance
plane (Smith chart). These two circles are called the source stability circle and the load
stability circle, respectively. This means that these circles are the boundary between
the stable and the unstable region.
Therefore, either the inside or the outside of the stability circles corresponds to
the stable region, in other words the region where |Γout | < 1 or |Γin | < 1, respectively.
If the output is loaded by ΓL = 0, then the input reflection coefficient would become
Γin = S11 . The following cases could occur:
382 Chapter 9. Amplifier Design Using S-parameters

|Γin|=1

|Γin|=1 |Γin|=1
|Γin|<1
|Γin|<1
|Γin|<1 rL
rL rL CL
CL CL
|Γin|<1

|S11|>1 |S11|<1 |S11|<1

(a) ( b) (c)

|Γin|=1

|Γin|=1
|Γin|<1
|Γin|<1 rL
CL rL CL

|S11|<1 |S11|<1
(d) (e)

Figure 9.2: Input stability circles on the load plane Smith chart for five cases (the
shaded areas correspond to the stable region), (a) for |S11 | > 1 and conditional
stability, (b) for |S11 | < 1, the stability circle intersecting the chart while not
comprising the chart center, and consequently, conditional stability, (c) for
|S11 | < 1, the stability circle intersecting the chart while comprising the chart
center, and consequently, conditional stability, (d) for |S11 | < 1, the stability
circle does not intersect the chart, and consequently, unconditional stability, and
(e) for |S11 | < 1, the stability circle comprises the whole chart, and consequently,
unconditional stability.

1. If |S11 | > 1, then obviously there is a load (ΓL = 0) for which the two-port
becomes unstable, and therefore, the two-port can be conditionally stable
(Figure 9.2(a)).
2. If |S11 | < 1, and if the stability circle intersects the Smith chart, and the center
of the chart (ΓL = 0) is outside the stability circle, the points inside the chart
and outside the stability circle correspond to the stable region. Anyway, the
two-port is conditionally stable in this case (Figure 9.2(b)).
3. If |S11 | < 1, and if the stability circle intersects the Smith chart, and the center
of the chart (ΓL = 0) is inside the stability circle, the points inside the chart and
inside the stability circle correspond to the stable region. Anyway, the two-port
is conditionally stable in this case (Figure 9.2(c)).
4. If |S11 | < 1, and if the stability circle does not intersect the Smith chart, and
the center of the chart (ΓL = 0) is outside the stability circle, the points inside
9.3 Performance Parameters of an Amplifier 383

the chart and outside the stability circle correspond to the stable region. Conse-
quently, the two-port is unconditionally stable (Figure 9.2(d)).
5. If |S11 | < 1, and if the stability circle does not intersect the Smith chart but
the whole chart is inside the stability circle (evidently the center of the chart
is inside the stability circle as well), the points inside the chart and inside the
stability circle correspond to the stable region. Consequently, the two-port is
unconditionally stable (Figure 9.2(e)).

The same argument can be used for the source plane and S22 , as depicted in Figure 9.3.
This leads to an important conclusion: if |S11 | < 1 and |S22 | < 1, the network is
unconditionally stable if and only if the stability circles at the load plane and at
the source plane do not intersect the Smith chart. These points are demonstrated in
Figures 9.2 and 9.3.

|Γout|=1
|Γout|=1
|Γout|=1
rS

|Γout|<1
|Γout|<1
CS rS
CS
|Γout|<1 rS
CS

|S22|>1 |S22|<1 |S22|<1

(a) ( b) (c)

|Γout|=1 |Γout|=1

|Γout|<1 rS

|Γout|<1 rS
CS CS

|S22|<1 |S22|<1
(d) (e)

Figure 9.3: Output stability circles on the source plane Smith chart for five
cases (the shaded areas correspond to the stable region), (a) for |S22 | > 1 and
conditional stability, (b) for |S22 | < 1, the stability circle intersecting the chart
while not comprising the chart center, and consequently, conditional stability,
(c) for |S22 | < 1, the stability circle intersecting the chart while comprising
the chart center, and consequently, conditional stability, (d) for |S22 | < 1, the
stability circle does not intersect the chart and consequently, unconditional
stability, and (e) for |S22 | < 1, the stability circle comprises the whole chart,
and consequently, unconditional stability.
384 Chapter 9. Amplifier Design Using S-parameters

As observed in Figure 9.2(b), when |S11 | < 1, the shaded area includes the origin,
while in Figure 9.2(a), when |S11 | > 1, only a small area within the Smith chart is
covered by the stability circle. The same point is illustrated for the output reflection
coefficient in Figure 9.3. In Figure 9.3(b), when |S22 | < 1, the shaded area includes
the origin, while in Figure 9.3(a), when |S22 | > 1, only a small area within the Smith
chart is covered by the stability circle.
Now, the necessary and the sufficient conditions for unconditional stability of a
two-port are that the stability circles do not intersect the Smith chart at the source and
at the load planes. That is

||CL | − rL | > 1 and |S11 | < 1 (9.22)

||Cs | − rs | > 1 and |S22 | < 1 (9.23)

Given |S11 | < 1 and |S22 | < 1, the above conditions can be translated into the following
pair of conditions:

1 − |S11 |2 − |S22 |2 + |∆|2

k= >1 (9.24)
2 |S12 S21 |

and

|∆| = |S11 S22 − S12 S21 | < 1 (9.25)

In Equation 9.24, k is called Rollett’s stability factor. Equations 9.24 and 9.25 are the
necessary and the sufficient conditions for stability of the two-port, given |S11 | < 1 and
|S22 | < 1. Or, in other words, the conditions are k > 1 and |∆| < 1.

9.3.2 Maximum APG

It can be shown that in order to obtain the maximum power gain, simultaneous conju-
gate matching must be realized at the input and the output. This conjugate matching is
only possible for the unconditionally stable two-port. Then the maximum available
gain can be found as

S21 p
MAG = 10 log × k − k2 − 1 (9.26)
S12

provided S12 6= 0 and k > 1. Note that for the case where S12 = 0 one can use the
unilateral transducer power gain as in Equation 9.29. Now, consider when we have no
constraint on the two-port and the two-port is unconditionally stable, for simultaneous
conjugate match, we should have

S12 S21 ΓL
Γin = S11 + = Γs ∗ (9.27)
1 − S22 ΓL
9.3 Performance Parameters of an Amplifier 385

and
S12 S21 Γs
Γout = S22 + = ΓL ∗ (9.28)
1 − S11 Γs
The simultaneous resolution of Equations 9.27 and 9.28 which results in maximum
APG or the maximum transducer gain is called the simultaneous complex conjugate
match (we discuss the solution of these equations in the following). Therefore, for
design purposes, we first choose a specific transistor with required power-frequency
capability. Then, using the load and the source, proper matching networks can be
designed. We should also note that there exists a relationship between the input and the
output reflection coefficients through S12 , further complicating impedance matching.
For the sake of simplicity, we first consider the case where S12 = 0, which is the
property of a unilateral transistor.

Conjugate Matching for a Unilateral Amplifier

As stated earlier, in this case, we have S12 = 0. As a result, we have Γin = S11 and
Γout = S22 . Considering the complex conjugate matching condition, which simply
reduces to Γs = S11 ∗ and ΓL = S22 ∗ , and ultimately, using the transducer power gain
expression, we arrive at
1 1
GT = 2
|S21 |2 = Gs,max |S21 |2 GL,max (9.29)
1 − |S11 | 1 − |S22 |2
This transducer gain could be translated to three parts. The first part expresses the
source matching gain (Gs,max ), the second part, the unmatched transducer gain (|S21 |2 ),
and the third part, the load matching gain (GL,max ).

Conjugate Matching for a Bilateral Amplifier

Here we consider the two-port is no more unilateral, that is, S12 6= 0. The complex
conjugate matching condition can be deduced from the solution of the following pair
of equations for the two unknowns ΓL and Γs :
S21 ΓL S12
Γs ∗ = S11 + (9.30)
1 − S22 ΓL
and
S21 Γs S12
ΓL ∗ = S22 + (9.31)
1 − S11 Γs
If Equations 9.30 and 9.31 are solved for the input and output reflection coefficients
simultaneously, two complex second-order equations would result whose solutions are
given in Equations 9.33 and 9.38:
C1 Γ2s,O − B1 Γs,O +C1∗ = 0 (9.32)
Therefore
q
B1 ± B1 2 − 4|C1 |2
Γs,O = (9.33)
2C1
386 Chapter 9. Amplifier Design Using S-parameters

where we have

B1 = 1 + |S11 |2 − |S22 |2 − |∆|2 (9.34)

and

C1 = S11 − ∆S22 ∗ (9.35)

There exists a solution if and only if B1 2 − 4|C1 |2 ≥ 0 which means k > 1. In order to
determine the sign before the square root term in Equation 9.34, the solution which
has an absolute value less than unity would be acceptable. In other words, we look for
the sign of B1 , if it is positive, then the square root sign is negative and vice versa. The
source impedance can be found from

1 + Γs
Zs = Z0 (9.36)
1 − Γs

Equivalently for the output reflection coefficient, we have

C2 Γ2L,O − B2 ΓL,O +C2∗ = 0 (9.37)

Therefore
q
B2 ± B2 2 − 4|C2 |2
ΓL,O = (9.38)
2C2

where

B2 = 1 + |S22 |2 − |S11 |2 − |∆|2 (9.39)

and

C2 = S22 − ∆S11 ∗ (9.40)

There exists a solution if and only if B2 2 − 4|C2 |2 ≥ 0 which means k > 1. In order to
determine the sign before the square root term in Equation 9.38, the solution which
has an absolute value less than unity would be acceptable. In other words, we look for
the sign of B2 , if it is positive, then the square root sign is negative and vice versa. The
load impedance can be found from

1 + ΓL
ZL = Z0 (9.41)
1 − ΓL

It should be noted that, if one of the source or load reflection coefficients are found, the
other one can be found from either through Equations 9.31 or 9.30.
9.3 Performance Parameters of an Amplifier 387

Example 9.1 The S-parameters at the given bias are measured for a bipolar
transistor at 200 MHz and at VCE = 10V, IC = 10 mA as S11 = 0.4∠162◦ , S12 =
0.04∠60◦ , S21 = 5.2∠63◦ , S22 = 0.35∠ − 39◦ . Assume that the amplifier is termi-
nated to a 50 Ω impedance at both input and the output. Perform complex conjugate
matching such that the maximum transducer power gain occurs.

Solution:
First, we examine the stability conditions using the provided S-parameters
from Equations 9.24 and 9.25 as

∆ = S11 S22 − S12 S21 = 0.4∠162◦ (0.35∠ − 39◦ ) − 0.04∠60◦ (5.2∠63◦ )

(9.42)
= 0.068∠ − 57◦

Now, we compute k as

1 − |S11 |2 − |S22 |2 + |∆|2 1 − 0.42 − 0.352 + 0.0682

k= = = 1.74 > 1
2 |S12 S21 | 2 (0.04) (5.2)
(9.43)

As we have k > 1, |∆| < 1, |S11 | < 1, and |S22 | < 1, the two-port network is
unconditionally stable. The MAG can be calculated from section 9.3.2 as

B1 = 1 + |S11 |2 − |S22 |2 − |∆|2 = 1 + 0.42 − 0.352 − 0.0682 = 1.03 > 0

(9.44)

It follows that

S21 p
MAG = 10 log + 10 log k − k2 − 1 (9.45)
S12
5.2 p
= 10 log + 10 log 1.74 − 1.742 − 1 = 16.1 dB

0.04
For example, if the desired maximum gain was larger than 16.1 dB, this transistor
could not be used. We can find the load reflection coefficient assuming the complex
conjugate; we have

C2 = S22 −∆S11 ∗ = (0.35∠ − 39◦ )−(0.068∠ − 57◦ ) (0.4∠ − 162◦ ) = 0.377∠−39◦

(9.46)

and

B2 = 1 + |S22 |2 − |S11 |2 − |∆|2 = 1 + 0.352 − 0.42 − 0.0682 = 0.958 (9.47)

388 Chapter 9. Amplifier Design Using S-parameters

which results in
q q
B2 ± B2 2 − 4 |C2 |2 0.958 − 0.9582 − 4(0.377)2
ΓL,O = = = 0.487∠+39◦
2C2 2 (0.377∠−39◦ )
(9.48)

Therefore, we have ΓL,O = 0.487∠39◦ , which is equivalent to ZL = 79.5 + j64.

The source reflection coefficient can be found to be

S21 ΓL S12 ∗

Γs,O = S11 +
1 − S22 ΓL
5.2∠63◦ (0.487∠39◦ ) 0.04∠60◦ ∗

◦
= 0.4∠162 + (9.49)
1 − 0.35∠ − 39◦ (0.487∠39◦ )
= 0.522∠ − 162◦

This reflection coefficient is equivalent to Zs = 16 − j7.

Now, we show the reflection coefficients on the Smith chart.
We can now match the 50 Ω impedance to the desired Γs,O and ΓL,O , using the
circuit topology shown in Figure 9.7. We begin at the origin and add a parallel
capacitor to move clockwise along the constant conductance contour. Then, a series
inductor is added so that we move clockwise, on the constant resistance contour, to
reach the desired source reflection coefficient, Γs,O . These steps are demonstrated
in Figure 9.5.

Γi

ΓL,O
Γr
Γs,O

ΓL,O=0.487 +39º
Γs,O=0.522 -162º

Figure 9.4: Input and output reflection coefficients on the Smith chart.
9.3 Performance Parameters of an Amplifier 389

Γi

A
Γr
C

B
YnA=1
YnB=1+j1.45
YnC=2.62+j1.45 ZC=Zs=16-j7
ZnA=1
ZnB=0.32-j0.468
ZnC=0.32-j0.14

Figure 9.5: Steps for input matching on the Smith chart.

The values of the capacitor and the inductor can be found to be

|Im{YB } − Im{YA }| 1.45 × 20 × 10−3

C= = = 23pF (9.50)
ω 2π 200 × 106

and
|Im{ZC } − Im{ZB }| 0.328 × 50
L= = = 13nH (9.51)
ω 2π 200 × 106

respectively.

The same procedure can be carried out in order to find the output matching
network. We first choose a series capacitor and move counterclockwise, on the
constant resistance contour, from the origin to point B in Figure 9.6, then by choos-
ing a parallel inductor, we move counterclockwise, on the constant conductance
contour, to reach ΓL,O point. These steps are depicted in Figure 9.6.
The inductor and capacitor values can be similarly found as

1 1
L= = = 50.3nH
ω |Im{YC } − Im{YB }| 2π 200 × 106 0.79 × 20 × 10−3

(9.52)
390 Chapter 9. Amplifier Design Using S-parameters

Γi

C
A Γr

B
YnA=1
YnB=0.38+j0.485
YnC=0.38-j0.305 ZC=ZL=79.5+j64
ZnA=1
ZnB=1-j1.27
ZnC=1.59+j1.28

Figure 9.6: Steps for output matching on the Smith chart.

Vcc
50.3nH
12.5pF

50Ω 13nH Vout

+ 50Ω
23pF

Figure 9.7: The overall matching network.

and
1 1
C= = = 12.5pF (9.53)
ω |Im{ZB } − Im{ZA }| 2π 200 × 106 1.23 × 50

The overall matching networks in the transistor circuit are depicted in

Figure 9.7.

We now proceed to study the design of two-port amplifiers for a specific gain.
9.4 Power Gain Contours 391

9.4 Power Gain Contours

When the value of |S12 | is not negligible (the device is not unilateral), chances are that
the device becomes potentially unstable and the solution for simultaneous conjugate
matching does not exist. A routine and conventional method is to design the circuit for
a specific operational power gain (OPG), in this case, one normally uses the constant
power gain contours. Remind that the OPG is independent of the source impedance.
Therefore, constant OPG contours can be drawn for both unconditional and conditional
stability on the load plane.

9.4.1 OPG Contours for Bilateral Unconditionally Stable Amplifiers

Our purpose in this section is to design a two-port amplifier with a specific gain. Now,
we follow the design procedure by just considering a single-stage amplifier. The
straightforward way to specify the amplifier power gain is to use constant gain contours
on the Smith chart. We observe that there exists certain loci of constant gain loads on
the load plane. It can be shown that

|S21 |2 1 − |ΓL |2
Gp = = |S21 |2 gp (9.54)
S11 −∆ΓL 2

2
1 − 1−S22 ΓL |1 − S22 ΓL |

where
Gp 1 − |ΓL |2
gp = 2
= (9.55)
|S21 | 1 − |S11 |2 + |ΓL |2 |S22 |2 − ∆2 − 2 Re (ΓLC2 )

where C2 is given by Equation 9.40. In the above equations, Gp and gp are a function
of S-parameters and the load reflection coefficient. It can be shown that those values
of load reflection coefficient which yield a constant gp lie on a circle, which we refer
to as constant OPG contour from now on. The equation of this contour on the load
reflection coefficient plane is given by (9.56):

ΓL −Cp = rp (9.56)

where Cp is the center and rp is the radius of the circle which are given by

gC∗
Cp = p 2 (9.57)
1 + gp |S22 |2 − |∆|2

and
q
1 − 2k |S12 S21 | gp + |S12 S21 |2 gp 2
rp = (9.58)
2 2
1 + gp |S22 | − |∆|

Equation 9.57
suggests that the distance from the origin to the center of the circle is
equal to Cp and its angle can be found by the angle of C2 ∗ . The maximum OPG occurs
392 Chapter 9. Amplifier Design Using S-parameters

where rp is equal to zero. Now, if we equate rp to zero, it follows from Equation 9.58
that
g2 p,max |S12 S21 |2 − 2k |S12 S21 | gp,max + 1 = 0 (9.59)
where gp,max is the maximum value of gp . Solving for gp for the unconditionally stable
case, we obtain
1 p
gp,max = k − k2 − 1 (9.60)
|S12 S21 |
This is indeed the case where the conjugate matched condition occurs at the output.
Now, substituting Equation 9.60 into Equation 9.55, we have
|S21 | p
Gp,max = k − k2 − 1 (9.61)
|S12 |
Provided |S12 6= 0| and k > 1. The minimum value for gp is equal to zero, which
means Gp = 0 as well. We can observe from Equation 9.55 that Gp = 0, if only if
the magnitude of the load reflection coefficient is equal to unity (ΓL = 1). In other
words, OPG is equal to zero if all the power is reflected by the load. For a given power
gain, the load reflection coefficient can be deduced from constant OPG contours. The
maximum gain occurs when the load reflection coefficient lies at the distance |ΓL,O |
and where gp,max = Gp,max /|S21 |2 . The maximum output power occurs when we have
complex conjugate matching at the input, i.e., Γs =Γin ∗ . We can say equivalently that if
Γs = Γin ∗ , the input power is equal to the maximum available input power. Therefore,
in this case, the maximum transducer gain is equal to the maximum OPG. The constant
power contour can be drawn as follows: (1) For a given power gain, we draw the
desired circle from Equation 9.56; (2) We choose a desired load reflection coefficient
on the contour; (3) For the given load reflection coefficient, the maximum output power
is obtained when we have complex conjugate matching at the input, i.e., Γs = Γin ∗ .
The resulting source reflection coefficient gives an OPG equal to the transducer power
gain.
Example 9.2 The S-parameters at the given bias are measured for a bipo-
lar transistor at 250 MHz and at VCE = 5V, IC = 5 mA as S11 = 0.277∠ − 59◦ ,
S12 = 0.078∠93◦ , S21 = 1.92∠64◦ , S22 = 0.848∠ − 31◦ . Assume that the input
and the output terminations are Zs = 35 − j60 and ZL = 50 − j50, respectively.
Design a two-port amplifier such that the gain of 9 dB is achieved at 250 MHz.

Solution: The stability factor is:

1 − |S11 |2 − |S22 |2 + |∆|2

k= = 1.033 (9.62)
2 |S12 S21 |

where

∆ = S11 S22 − S12 S21 = (0.277∠ − 59◦ ) (0.848∠ − 31◦ )

− (0.078∠93◦ ) (1.92∠64◦ ) = 0.324∠ − 64.8◦ (9.63)
9.4 Power Gain Contours 393

Γi

rP
CP
C
Γr

A
B
YnA=0.5+j0.5
YnB=0.1+j0.3
YnC=0.1-j0.125 ZC=195+j244
ZnA=1-j1 Cp=0.712 +33.9º
ZnB=1-j3 rp=0.285
ZnC=3.9+j4.88

Figure 9.8: The load matching using a series capacitor and a parallel inductor
to achieve 9 dB gain.
The amplifier is unconditionally stable with k = 1.033 and ∆ < 1. It can be
shown that the maximum gain is equal to 12.9 dB. We have

C2 = S22 − ∆S11 ∗ = (0.848∠ − 31◦ ) − (0.324∠ − 64.8◦ ) (0.277∠59◦ )

= 0.768∠ − 33.9◦ (9.64)

and Gp 100.9 7.94

gp = 2
= 2
= = 2.15 (9.65)
|S21 | (1.92) (1.92)2

Now, we can write

gC∗ 2.15 (0.768∠33.9◦ )

Cp = p 2 = 2 2
= 0.712∠33.9◦
2
1 + gp |S22 | − |∆|2 1 + 2.15 0.848 − 0.324

(9.66)

and
q
1 − 2k |S12 S21 | gp + |S12 S21 |2 gp 2
rp = = 0.285 (9.67)
2 2
1 + gp |S22 | − |∆|

The constant gain contour is shown in Figure 9.8. In order to arrive at a point on
the contour from the starting point, A (ZnA = 1 − j1), we move counterclockwise
on a constant resistance circle (R = 50 Ω) with a series capacitor to point B and
394 Chapter 9. Amplifier Design Using S-parameters

then we move counterclockwise on the constant conductance circle, using a parallel

inductor, so as to intersect the constant power gain circle at point C.
The values of the series capacitor and the parallel inductor can be found as

1 1
C= = = 6.4pF (9.68)
ω |Im{ZB } − Im{ZA }| 2π 250 × 106 2 × 50

and
1 1
L= = = 75nH (9.69)
ω |Im{YC } − Im{YB }| 2π 250 × 106 0.425 × 0.02

For complex conjugate matching at the input, the chosen load reflection coefficient
0
is ΓL = 0.82∠14.2◦ . The input reflection coefficient then would be
0
!∗
0 S21 ΓL S12
Γs = S11 + 0
1 − S22 ΓL
(1.92∠64◦ ) (0.82∠14.2◦ ) (0.078∠93◦ ) ∗

= 0.277∠ − 59◦ + (9.70)
1 − (0.848∠ − 31◦ ) (0.82∠14.2◦ )
= 0.105∠160◦

The input matching is shown in Figure 9.9.

Γi

C
D
Γr

A
YnA=0.36+j0.62
YnB=0.36+j1.24 B
YnC=1.22-j2.01 ZD=41+j3
YnD=1.22-j0.09
ZnA=0.7-j1.2
ZnB=0.22-j0.74
ZnC=0.22+j0.36
ZnC=0.82+j0.06

Figure 9.9: Source matching.

9.4 Power Gain Contours 395

Vcc

75nH
6.4pF

35nH Vout
ZS
ZL
+
ES 7.9pF 24.4pF ΓL′ ΓL

Γs Γs′

Figure 9.10: The input and output matching networks for complex source
and load impedances.

We turn clockwise from point A, the normalized input impedance (ZnA =

0.7 − j1.2), with a parallel capacitor on the constant conductance circle to point B.
Then, using a series inductor, we turn clockwise on the constant resistance circle to
arrive at point C, and finally by adding a parallel capacitor, we turn clockwise on
the constant conductance circle to arrive at the desired source reflection coefficient.
The values of the parallel capacitors and the series inductor are given by

|Im{YB } − Im{YA }| 0.62 × 0.02

C= = = 7.9pF (9.71)
ω 2π 250 × 106

and
|Im{ZC } − Im{ZB }| 1.1 × 50
L= = = 35nH (9.72)
ω 2π 250 × 106

and
|Im{YD } − Im{YC }| 1.92 × 0.02
C= = = 24.4pF (9.73)
ω 2π 250 × 106

The overall matching network is depicted in Figure 9.10.

While in Example 9.2 the load and the source impedances were not equal to 50 Ω,
normally this is not the case and every stage is normally matched to the reference
impedance, e.g., 50 Ω. In the next example, we take into consideration both the stability
and the power gain contours.

Example 9.3 S-parameters at 200 MHz and bias information for transistor 2N5179
are given as VCE = 6V , IC = 5 mA, S11 = 0.4∠280◦ , S12 = 0.048∠65◦ , S21 =
5.4∠103◦ , S22 = 0.78∠345◦ . Also assume 50 Ω terminations. Design the two-port
amplifier such that 12 dB power gain is achieved at 200 MHz.
396 Chapter 9. Amplifier Design Using S-parameters

Solution: We first calculate ∆ as

∆ = (0.4∠280◦ ) (0.78∠345◦ ) − (0.048∠65◦ ) (5.4∠103◦ ) = 0.429∠ − 58.18◦

(9.74)

The Rollet stability factor becomes

1 − 0.42 − 0.782 + 0.4292

k= = 0.802 (9.75)
2 (0.048) (5.4)

Therefore, the two-port is conditionally stable (k < 1). Recalling Equation 9.35,
we now derive the input and the output stability circles as

C1 = S11 − ∆S22 ∗ = 0.4∠280◦ − (0.429∠ − 58.18◦ ) (0.78∠ − 345◦ )

= 0.241∠ − 136.6◦ (9.76)

and from Equation 9.40

C2 = S22 −∆S11 ∗ = 0.78∠345◦ −(0.429∠ − 58.18◦ ) (0.4∠ − 280◦ ) = 0.65∠−24◦

(9.77)

The center and the radius of the locus of the unity output reflection coefficient
(input stability circle) can be found from Equation 9.17:

C1 ∗ 0.241∠136.6◦
Cs = 2 2
= = 10∠−43.4◦ (9.78)
|S11 | − |∆| 0.42 − 0.4292

and recalling Equation 9.16

S S (0.048∠65◦ ) (5.4∠103◦ )
12 21
rs = = = 10.78 (9.79)

|S11 |2 − |∆|2 0.42 − 0.4292

The center and the radius of the locus of the unity input reflection coefficient (output
stability circle) can be found from Equation 9.20:

C2 ∗ 0.65∠24◦
CL = 2 2
= = 1.53∠24◦ (9.80)
|S22 | − |∆| 0.782 − 0.4292

and recalling Equation 9.19

S S (0.048∠65◦ ) (5.4∠103◦ )
12 21
rL = = = 0.610 (9.81)

|S11 |2 − |∆|2 0.782 − 0.4292
9.4 Power Gain Contours 397

We then proceed to find the center and the radius corresponding to the desired gain
in the example. It follows from Equation 9.55:
Gp 101.2 15.85
gp = 2
= = = 0.543 (9.82)
|S21 | 5.42 5.42

and then, recalling Equation 9.57, we have

gC∗ 0.543 (0.65∠24◦ )
Cp = p 2 = = 0.287∠24◦ (9.83)
1 + gp |S22 |2 − |∆|2 1 + 0.543 0.782 − 0.4292

and from Equation 9.58

q
1 − 2k |S12 S21 | gp + |S12 S21 |2 gp 2
rp = = 0.724 (9.84)
2 2
1 + gp |S22 | − |∆|

The areas of interest are shown in the Smith chart in Figure 9.11. We should choose
a point on the constant gain contour such that it lies outside the output stability
circle. Let’s choose ΓL = (0.724 − 0.287) ∠(24 + 180)◦ = 0.437∠204◦ to be sure
of the output stability. Now we choose a proper value for Γs such that the transducer
gain becomes equal to the operating power gain (the input is matched to the source),
so it can be calculated as follows

S12 S21 ΓL ∗

Γs = S11 + = 0.409∠68◦ (9.85)
1 − S22 ΓL

|īin|=1
īi īi Constant
Input gain
unstable circle
region Output
|īout|=1
unstable
region

rL
īs CL

CP
īr
rP
īr
īL

īs=0.409 +68º īL=0.437 +204º

(a) (b)

Figure 9.11: (a) The input stability circle and the corresponding source
reflection coefficient. (b) The output stability circle and the chosen load
reflection coefficient.
398 Chapter 9. Amplifier Design Using S-parameters

As it can be seen in Figure 9.11, in the computed Γs is outside the unstable

source region. So now a standard technique can be used to realize the specified val-
ues of Γs and ΓL out of a 50 Ω source and a 50 Ω load using an L-section matching
network. So an amplifier with a 12 dB gain is designed with a conditionally stable
device.

9.4.2 APG Contours for Bilateral Conditionally Stable Amplifiers

In a similar way, the constant APG contours can be obtained on the source plane:

|S21 |2 1 − |Γs |2
GA =
S22 −∆Γs = |S21 |2 ga (9.86)
2
1 − 1−S11 Γs |1 − S11 Γs |

where the normalized APG is

GA 1 − |Γs |2
ga = = (9.87)
|S21 |2

1 − |S22 |2 + |Γs |2 |S11 |2 − ∆2 − 2real{ΓsC1 }

and

C1 = S11 − ∆S22 ∗ (9.88)

In a similar way to those expressions already derived earlier for OPG, the center and
the radius of constant APG circles which are drawn on the input reflection coefficient
plane can be, respectively, found as

gC∗
Ca = a 1 (9.89)
1 + ga |S11 |2 − |∆|2

and
q
1 − 2k |S12 S21 | ga + |S12 S21 |2 ga 2
rp = (9.90)
2 2
1 + ga |S11 | − |∆|

At the end, the circles can be plotted using Ca and rp on the input reflection coefficient
plane with every point on the circle yielding the desired gain. The maximum gain is
achieved when the load and the output reflection coefficient are conjugate matched, in
which case the transducer power gain (TPG) and APG become equal. Interestingly,
as constant noise contours are also drawn on the input reflection coefficient plane, a
compromise can be made between the available gain and the minimum noise figure on
this plane. As a result for the amplifiers where the operating power gain is critical, we
use the procedure described in Example 9.3, and for the amplifiers where the APG and
the noise figure are of more importance, we use the procedure described in the next
section.
9.5 Noise Behavior of a Two-Port Network 399

9.5 Noise Behavior of a Two-Port Network

The noise figure (NF) for a two-port network can be defined by the quantity through
which it decreases the output SNR with respect to the input SNR. In many receiver
applications, minimum noise is the most important design parameter. As minimum
noise and maximum power gain do not coincide, a compromise is made by plotting
both the constant noise and the constant APG contours, and choosing the proper source
reflection coefficient. This trade-off can be well extended to noise, stability, matching,
and power gain. If the objective is to design a wideband amplifier, then the most
important condition to satisfy would be achieving a flat power gain response with
minimal distortion, all of which is achieved by using a compensated matching network,
may be using a negative feedback and a balanced architecture for the amplifier. It is
important to note that using small-signal S-parameters is valid as long as the transistor
operates in the linear regime, its output power remaining below saturation in linear
region. It should be noted that the more we move into the nonlinear regime, the more
the input/output impedances or the reflection coefficients become dependent on the
operating power level.

9.5.1 Noise in a Two-Port

In RF amplifiers, even in the absence of the signal and the interference at the input, a
small voltage can be recorded at the output. This negligibly small value is referred to as
the amplifier output noise voltage. We recognize that the total output noise power is the
combination of the intrinsic noise of the amplifier, resulting from the transistor itself
or other noisy components, and the input noise amplified by the amplifier. Depicted in
Figure 9.12 is the noise model of an RF or a microwave two-port amplifier.
The input noise can be modeled by an equivalent noise voltage source (Vn ) related
to the source resistance, a series noise voltage source (en ), and a parallel noise current
source (in ), the two latter pertaining to the two-port referred to its input. The source
resistance generates a thermal or Johnson noise. In fact, the noise is generated by the
random movements of electrons due to thermal excitations. This noise can be found
for a specific bandwidth as

V 2 n,rms = 4kT BRS (9.91)

where k is the Boltzmann constant of a value of 1.374 × 10−23 ◦Jk , T is the absolute
temperature of the resistor in Kelvins, and B is the operating bandwidth. As suggested
by Equation 9.91, the noise power is a direct function of its bandwidth and the
bandwidth is normally limited value in an RF system. Thermal noise is widely known

XS XS en

*
+
-

RS Noisy RS Noiseless
two-port ZL in two-port ZL
+ network + network
Vn
* -
Vn
* -
2 2
Vn =4KTBRS Vn =4KTBRS

Figure 9.12: The noise model of a two-port amplifier.

400 Chapter 9. Amplifier Design Using S-parameters

as a white noise, as it contains all frequency components and has a flat spectral behavior
over the frequency range. The available noise power of a resistor can be derived as
V 2 n,rms
PN = = KT B (9.92)
4RS
Note that noise voltage has a random value, its instantaneous value is not known, but
its rms value can be estimated. The wider the bandwidth, the narrower and larger the
instantaneous voltage spikes.

Example 9.4 Find the available noise power which a resistor generates at the
standard temperature, i.e., T0 = 290◦ k in a bandwidth of 1 Hz. Then, calculate the
noise voltage and power for a 2 MΩ resistor in a bandwidth of 5 kHz and at the
standard temperature.
Solution: We have from Equation 9.92,
PN = KT B = 1.374 × 10−23 (290) (1) = 3.985 × 10−21W

(9.93)

which if written in dBm, we have

PN
PN (dBm) = 10 log −3 = 10 log 3.985 × 10−18 = −174 dBm (9.94)
10
Now, in order to obtain the noise voltage for a 5 kHz bandwidth, we write
q
vn,rms = 4 1.374 × 10−23 (290) (5000) 2 × 106 = 12.6 µV

(9.95)

and finally, the noise power can be calculated from Equation 9.93 as
2
PN 12.6 × 10−6
PN (dBm) = 10 log −3 = 10 log × 103
10 4 2 × 106

= 10 log 19.9 × 10−15 = −137 dBm (9.96)

Noise figure is a quantitative measure of noise behavior in an RF or a microwave

amplifier. The noise figure is defined as the ratio of total available noise power at
the output of the amplifier to the available output noise power resulting from the
same noiseless two-port connected to a resistive source termination, say R, at standard
temperature, at the input. This definition can be written as
PNO
F= (9.97)
PNi GA
In Equation 9.97, PNo is the total noise power at the output of the amplifier, PNi = KT0 B
is the available noise power resulting from the termination resistor, R, at standard
temperature, T0 = 290◦ k, B is the bandwidth, and GA is the APG, which is given by
PSO
GA = (9.98)
PSi
9.5 Noise Behavior of a Two-Port Network 401

In Equation 9.98, PSO is the output signal power and PSi is the input signal power.
Therefore, Equation 9.97, can be rewritten as
PSi /PNi SNRi
F= = (9.99)
PSO /PNO SNRO

In other words, the noise figure can be defined as the ratio of the SNR at the input
to the SNR at the output. Given the fact that the noise figure is always greater than
unity, the output SNR is always smaller than the input SNR, so it is evident that in an
amplifier one cannot improve the SNR, as such an RF engineer would rather strive not
to degrade it. The curious student might ask why do we ever amplify the signal in a
receiver where at every stage the SNR would be degraded within the amplifier chain?
The reason is that to be able to further process the signal, it is necessary that the signal
should attain a certain required level (a few dBm’s, for example) for detection. In an
amplifier, in order to find the minimum noise figure, the choice of a proper source
reflection coefficient is important. In Figure 9.13, a model is provided for calculation
of noise figure in cascaded amplifiers. As depicted in Figure 9.13, PNi is the input
noise power, GA1 and GA2 are the APGs of the first and the second stage, and PN1 and
PN2 represent the available noise powers at the output of each amplifier which result
from its own intrinsic noise. Hence, the total noise at the output can be written as

PNO = GA2 GA1 PNi + PN1 + PN2 (9.100)

Using the definition provided earlier, noise figure can be calculated as

PNO PN1 PN2
F= = 1+ + (9.101)
PNi GA1 GA2 PNi GA1 PNi GA1 GA2

Equation 9.101 can also be rewritten as

F2 − 1
F = F1 + (9.102)
GA1
Since we have
PN1
F1 = 1 + (9.103)
PNi GA1

First Second
amplifier amplifier
R PNi=KTBR GA1PNi+PN1 PNo ZL
GA1 GA2
PN1 PN2

Figure 9.13: Model for noise figure calculation in a cascade of two stages.
402 Chapter 9. Amplifier Design Using S-parameters

and
PN2
F2 = 1 + (9.104)
PNi GA2

F1 and F2 are the noise figures corresponding to each one of the stages. Equation 9.102
suggests that the noise of the second stage is diminished by a factor of GA1 . We
then realize that the noise of the second stage cannot affect the overall noise figure
significantly. This leads to an important observation from the design point of view: the
noise of the first stage is the most important part of the overall noise figure, given the
fact that the power gain of the preceding amplifiers masks the noise of the following
stages, and therefore it is appropriate to diminish the noise figure of the first stage at
the price of losing a little bit of the power gain. In fact, we can target for the minimum
noise figure for a lesser power gain at the first stage. A trade-off always exists between
NF and the APG in any design. The design can be made such that the minimum NF
is obtained. Consider two amplifiers with NF’s and gains of F1 , F2 , GA1 , and GA2 ,
respectively. If the first amplifier precedes the second amplifier, the overall NF denoted
by F12 can be written as

F2 − 1
F12 = F1 + (9.105)
GA1
and if the second amplifier comes first, F21 is given by

F1 − 1
F21 = F2 + (9.106)
GA2
To have a lower NF in the first case, i.e., F12 < F21 , we should have
F2 − 1 F1 − 1
F1 + < F2 + (9.107)
GA1 GA2
which can be rewritten as
F1 − 1 F2 − 1
1
< (9.108)
1 − GA1 1 − G1A2

Equation 9.108 can be simplified as

M1 < M2 (9.109)

where the quantity M is defined as the noise measure of the amplifier:

F −1
M= (9.110)
1 − G1A

M is an alternative quantity to represent the noise performance of an amplifier, in-

cluding noise figure and the power gain. Equation 9.109 suggests that, if the noise
measure of the first stage, M1 , is smaller than that of the second stage, M2 , the overall
9.6 Constant Noise Figure Contours 403

noise figure in this structure will be smaller. Hence, we predict that, in order to have
a minimal NF in a cascade of stages, the amplifier with the lower noise measure, M,
should precede the one with larger noise measure. It can be shown that NF for a
cascade of many stages is given by

F2 − 1 F3 − 1 F4 − 1
F = F1 + + + +··· (9.111)
GA1 GA1 GA2 GA1 GA2 GA3

which is called the “Friis’ relation” for the noise figure. This equation for the special
case of F1 = F2 = · · · Fn and GA1 = GA2 = · · · = GAn and, assuming an infinite chain
of identical amplifiers, reduces to

F1 − 1
F = 1+ = 1 + M1 (9.112)
1 − G1A1

This means the noise figure of an infinite chain of identical amplifiers tends to a limited
value (the noise measure plus unity).

9.6 Constant Noise Figure Contours

It can be shown that the NF of a two-port amplifier can be expressed by

Rn 2
F = Fmin + Ys −Yopt (9.113)
Gs

where Rn is the equivalent noise resistance of the two-port, or in a normalized notation

rn = Rn /Z0 , YS = Gs + jBs is the source admittance of the two-port, and Yopt = Gopt +
jBopt denotes the optimum source admittance which results in the minimum noise
figure, Fmin . The source admittance and the optimum noise admittance can be readily
expressed in terms of their corresponding reflection coefficient as

1 − Γs
YS = Y0 (9.114)
1 + Γs

and
1 − Γopt
Yopt = Y0 (9.115)
1 + Γopt

Substituting Equations 9.114 and 9.115 into Equation 9.113, we obtain

2
4rn Γs − Γopt
F = Fmin + 2 (9.116)
1 − |Γs |2 1 + Γopt

This relation is a function of Fmin , rn , and Γopt . These three parameters, two real and
one complex (or equivalently four real parameters), are widely known as the noise
parameters and are provided either in the datasheet by the vendor or can be found
404 Chapter 9. Amplifier Design Using S-parameters

by measurement. The input reflection coefficient can be altered and the noise figure
can be measured accordingly. Multiple measurements with different source reflection
coefficients (measured using a network analyzer), and the noise figure measured by a
noise figure meter will allow the engineer to extract the four required noise parameters.
Here Fmin is a function of the bias current or the bias voltage of the device and the
operating frequency. Therefore, only a single Γopt corresponds to every value of Fmin .
Equation 9.116 can be rewritten such that for a specific input reflection coefficient, ΓS ,
the resulting NF is, say F = Fi . Hence

Γs − Γopt 2

Fi − Fmin 2
2
= 1 + Γopt (9.117)
1 − |Γs | 4rn

As suggested by Equation 9.117, for a given noise figure, Fi , the right-hand side of the
equation is a constant. Therefore, if we define a factor, Ni as
Fi − Fmin 2
Ni = 1 + Γopt (9.118)
4rn
and, it follows that

Γs − Γopt 2

= Ni (9.119)
1 − |Γs |2

Equation 9.119 can be rewritten as

2 Γopt 2 Ni
|Γs |2 − Re Γs Γopt ∗ +

= (9.120)
1 + Ni 1 + Ni 1 + Ni
This represents a contour on the input reflection coefficient plane. Equation 9.120 can
also be rewritten alternatively as

2 N 2 + N 1 − Γ 2
Γ i i opt
Γs − opt =

(9.121)
1 + Ni (1 + N )2 i

This describes a circle on the input reflection coefficient plane with the center, CF,i ,
and the radius, rF,i , as follows

Γopt
CFi = (9.122)
1 + Ni
and
r
1 2
rFi = Ni 2 + Ni 1 − Γopt (9.123)
1 + Ni
Using Equation 9.118, Ni can be obtained for a given value of Fi . Ultimately, having
both the centers and the radii of constant noise figure contours, they can all be plotted
9.6 Constant Noise Figure Contours 405

Γi

3dB
Γopt A
3.5dB
4dB
5dB
6dB
Γr

Γopt=0.58 +138º
ΓA=0.38 +119º

Figure 9.14: Constant NF contours on the plane of input reflection coefficient.

on the input reflection coefficient plane. Equations 9.118 through 9.123 suggest that,
when Fi = Fmin , Ni is equal to zero, and the center corresponds to Γopt and the radius
would be zero (Fmin contour lies at the center point, Γopt , with a radius of zero). We
realize from Equation 9.120 that the centers of all other constant noise figure contours
lie on a line connecting the center of the chart to the Γopt point; in other words, they
lie on a line passing through the center with ∠Γopt . A typical group of constant noise
figure contours are depicted in Figure 9.14. As it is obvious from Figure 9.14, the
minimum noise figure, Fmin , corresponds to Γs = Γopt = 0.58∠138◦ and it is equal
to 3 dB. Any other neighboring point will have a higher noise figure. At point A, for
instance, with Γs = 0.38∠119◦ , we have NF = 4 dB.
In practical designs, there is always an unwanted discrepancy between the targeted
NF value and the NF derived from the measurement which stems from the matching
network imperfection and also inaccuracies in the transistors noise parameters’ mea-
surement. Typically speaking, this may amount to a few 0.1 dB’s to 1 dB change in
NF.
In a practical low-noise amplifier design, there exists a trade-off between the APG,
the noise figure, and VSWR, or equivalently, matching. The trade-off between the
noise and the power gain is illustrated in Figure 9.15, which the transistor of choice is
unilateral and a group of constant NF and constant gain contours are plotted. As it is
obvious from Figure 9.15, the maximum power gain and the minimum NF points do
not coincide in general. The normalized power gain in Figure 9.15 is Gs = 3 dB, which
occurs with Γs = 0.7∠110◦ and results in Fi = 4 dB. The minimum NF, Fmin = 0.8 dB
is achieved with Γs = 0.6∠40◦ , and corresponds to normalized Gs = −1 dB.
Using the above constant gain and the constant noise figure contours, one can
easily make a trade-off between the gain and the noise figure. As to say for a given
noise figure, the point at which a constant gain circle (with maximum possible gain) is
406 Chapter 9. Amplifier Design Using S-parameters

īL $ĺ0LQQRLVHILJXUH)PLQ
&RQVWDQW
JDLQ %ĺ0D[SRZHUJDLQ
FRQWRXUV

G%
% &RQVWDQW
1)
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FRQWRXUV
$
G%
G%
G%
G% G%

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G%
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G%
G%

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Figure 9.15: Constant NF and the normalized available power gain contours on
the input reflection coefficient plane at 6 GHz.

tangent to it gives the best compromise, otherwise for a given power gain the point at
which a constant noise figure circle (with minimum possible noise figure) is tangent
to it gives the best compromise. For example, if we choose to have a NF of 1 dB, we
would then choose point C where the 0 dB power gain circle is tangent to it and the
corresponding ΓS is 0.45∠47◦ .

9.7 Design of a Single-Stage Low-Noise Amplifier

If our objective is to design a minimum NF stage, the source impedance and the bias
points must be chosen such that the minimum NF is achieved for the device. This can
be done either by performing a set of measurements on the device or using the noise
datasheet provided by the device vendor. The input matching network can then be
easily designed. For design considerations, the condition k > 1 should be satisfied, so
that the transistor is stable. Once the optimum input reflection coefficient is realized
for the minimum noise, the load reflection coefficient should be chosen such that the
load is matched to output. That is

S21 S12 Γs ∗

ΓL = S22 + (9.124)
1 − S11 Γs

Example 9.5 clarifies the design procedure.

9.7 Design of a Single-Stage Low-Noise Amplifier 407

Example 9.5 The optimum noise bias point for a given bipolar transistor is VCE =
10 V and IC = 5 mA. The optimum noise input reflection coefficient at 200 MHz is
Γs = 0.7∠140. S-parameters at 200 MHz (in a 50 Ω measurement system) are given
as S11 = 0.4∠168◦ , S12 = 0.04∠60◦ , S21 = 5.2∠63◦ , S22 = 0.35∠ − 39◦ . Design
an LNA at 200 MHz with the source and load impedances of 75 Ω and 100 Ω. Then,
determine what the transducer power gain is expected of this design.

Solution:
We first evaluate the Rollet stability factor as

1 − |S11 |2 − |S22 |2 + |∆|2 1 − 0.42 − 0.352 + 0.0682

k= = = 1.74 (9.125)
2 |S12 S21 | 2 (0.04) (5.2)

Considering k > 1 and |∆| < 1 the transistor is unconditionally stable. As such, the
amplifier is stable. We then design the input matching network for a 75 Ω source
impedance. We depict the optimum noise source impedance on the Smith chart
at point C, Γs = 0.7∠140 corresponding to ZnC = 0.2 + j0.35. Using Figure 9.16,
starting from point A (ZnA = 1.5 + j0), we turn clockwise on the constant conduc-
tance contour (G = 0.667) to intersect the constant resistance contour (R = 0.2) at
point B. So for the parallel capacitor, we would have

|Im{YB } − Im{YA }| 1.7 × 0.02

C= = = 27pF (9.126)
ω 2π 200 × 106

Γi

Γs, opt
C
A
Zsource=75Ω
Γr

YnA=0.667+j0
B
YnB=0.667+j1.7
YnC=1.23-j2.153 ΓC=ΓS=0.7 +140º
ZnA=1.5+j0
ZnB=0.2-j0.51
ZnC=0.2+j0.35

Figure 9.16: Input matching on the Smith chart.

408 Chapter 9. Amplifier Design Using S-parameters

Γi

B
Γmatching

A
Zload=100Ω
Γr

YnA=0.5+j0
YnB=0.5-j0.48
ZnA=2+j0 ΓB=ΓL=0.43 +61º
ZnB=1.04+j1

Figure 9.17: Output matching on the Smith chart.

Starting from point B (ZnB = 0.2 − j0.51), we turn clockwise on the constant
resistance contour (R = 0.2) to arrive at point C. So for the series inductor, we
would have
|Im{ZC } − Im{ZB }| 50 × 0.86
L= = = 34nH (9.127)
ω 2π 200 × 106

For the output matching network, we have from Equation 9.124

(5.2∠63◦ ) (0.7∠140◦ ) (0.04∠60◦ ) ∗

ΓL = 0.35∠ − 39◦ + = 0.43∠61◦ (9.128)
1 − (0.4∠168◦ ) (0.7∠140◦ )

In Figure 9.17, we depict ΓL = 0.43∠61◦ at point B on the Smith chart which

corresponds to YnB = 0.5 − j0.48. We depict the required load impedance at
point A corresponding to YnA = 0.5 + j0. As such, with adding a single parallel
inductance, we can turn counter clockwise, on the constant conductance circle
(G = 0.5) from point A to point B. We would have then

1 1
L= = = 83 nH (9.129)
ω |Im{YC } − Im{YB }| 2π 200 × 106 0.48 × 0.02

The 330 pF capacitors at the input and the output are for DC decoupling purpose
and their AC impedances are negligible.
9.8 Design of Two-Stage Amplifiers 409

9

S) ȍ

NŸ Q+

ȍ S) Q+ S)

ȕGF
ȍ
S)

Figure 9.18: The overall matching network.

The overall matching network is depicted in Figure 9.18.

For the transducer gain (once we put the expression for Γin from Equation 8.30
in Equation 9.6) we have

|S21 |2 1 − |ΓL |2 1 − |Γs |2
GT = = 23 (9.130)
|(1 − S11 Γs ) (1 − S22 ΓL ) − S21 ΓL S12 Γs |2

Or

10 log 23 = 13.6 dB (9.131)

Now that we have learned how to design a single-stage amplifier, we move on to design
a two-stage low noise amplifier and understand the design procedure.

9.8 Design of Two-Stage Amplifiers

Consider the NF of a cascade of multiple stages of amplifiers, which is referred to as
the Friis’ NF equation, as
F2 − 1 F3 − 1 F4 − 1
F = F1 + + + +··· (9.132)
GA1 GA1 GA2 GA1 GA2 GA3
In order to minimize the overall NF, the NF of the first stage must be minimized and
its gain maximized. The input reflection coefficient must be chosen such that it results
in the minimum overall NF. As we discussed earlier, the maximum gain point and the
minimum noise figure point are normally distinct on the source plane Smith chart. It
is possible to draw a line connecting the two point on the chart, and then choose the
reflection coefficient which results in the lowest noise along this line.
410 Chapter 9. Amplifier Design Using S-parameters

Example 9.6 If the amplifier whose specifications are given in Figure 9.15 has a
value of |S21 | = 8 and it is cascaded by another amplifier whose NF is F2 = 5 dB,
find the overall NF once the amplifier’s source reflection coefficient is either at
point A or at point B.

Solution:

We record NF and the power gain from Figure 9.15 as F = 0.8 dB and G =
−1 dB at point A and F = 4 dB and G = 3 dB at point B. The denormalized power
gains at points A and B become
GA = −1 + 10 log 8 = 8 dB (9.133a)

GB = 3 + 10 log 8 = 12 dB (9.133b)

We have from Equation 9.132

F2 −1 100.5 −1
A : FT =F1+ =100.08+ =1.545 or 10 log 1.545=1.89 dB (9.134)
G1 100.8
and
F2 −1 100.5 −1
B : FT =F1 + =100.4 + =2.65 or 10 log 2.65=4.23 dB (9.135)
G1 101.2

This design procedure for a specific power gain and the minimum possible NF consists
of three steps: (1) The contours corresponding to the desired APG should be drawn;
(2) The NF contour which is tangent to the required power gain contour should be
drawn next; and (3) The optimum reflection coefficient lies on the specified loci where
the two circles are tangent.
Example 9.7 The optimum bias points along with S-parameters and noise pa-
rameters for◦
a transistor are ◦provided at 4 GHz:
◦
VCE = 10V , IC =◦ 4 mA, S11 =
0.552∠169 , S12 =◦0.049∠23 , S21 = 1.681∠26 , S22 = 0.839∠−67 , Fmin = 2.5 dB,
Γopt = 0.475∠166 , rn = 3.5 Ω. Design the amplifier such that the overall noise
figure of this stage followed by another stage with NF = 7 dB is minimized.

Solution:
We first evaluate the stability of the transistor.

|∆| = S11 S22 − S12 S21 = 0.419 < 1 (9.136)

2 2 2
1 − |S11 | − |S22 | + |∆|
k= = 1.012 > 1 (9.137)
2 |S12 S21 |

As a result, the amplifier is unconditionally stable. The constant APG and the
constant NF contours are plotted in Figure 9.19 in the plane of the source reflection
9.8 Design of Two-Stage Amplifiers 411

coefficient. Now, we choose a set of points with the specified noise figure and
the maximum possible APG as follows, and we compute the overall noise figure
consequently (from Equation 9.132).

A1 : F1 = 2.5 dB, G1 = 11dB ⇒ FT = 2.095(3.21 dB) (9.138)

Γi 2.5dB→Min noise figure (Fmin)

Constant 14.7dB→Max power gain
NF
contours

2.5dB
A1
A2
Γr
A3
A4
14.7dB

Constant
gain
contours ΓA2=ΓS=0.5 -175º

Figure 9.19: Constant power gain and constant NF contours for the given
transistor on the Smith chart.

A2 : F1 = 2.6 dB, G1 = 12.2 dB ⇒ FT = 2.06(3.14 dB) ; ΓS = 0.524∠+186◦

(9.139)
A3 : F1 = 2.7 dB, G1 = 12.7 dB ⇒ FT = 2.077(3.17 dB) (9.140)
A4 : F1 = 2.8 dB, G1 = 13 dB ⇒ FT = 2.16(3.35 dB) (9.141)

As such, the input reflection coefficient (at point A2 ) is chosen as

Γs = 0.524∠+186◦ (9.142)

For the output matching, the load reflection coefficient can be calculated as

S21 S12 Γs ∗

ΓL = S22 + = 0.871∠+70◦ (9.143)
1 − S11 Γs

412 Chapter 9. Amplifier Design Using S-parameters

It is noteworthy that all the procedure which has been described in terms of S-
parameters formulation can be repeated in terms of other circuit parameters such as
Y-parameters. The following example illustrates this approach.

Example 9.8 Admittance parameters for a field effect transistor at 1 GHz are
given as Y11 = 8.79 mjf,Y12 = −2.5 mjf,Y21 = 1 mf − 2.5 mjf,Y22 = 0.33 mf +
3.77 mjf.
(a) Determine the circuit model values as depicted in Figure 9.20.
(b) Does this transistor lead to a stable amplifier design? Determine the value of
the required parallel resistor at the output to provide unconditionally stability if a
parallel 1 kΩ is added at the input.
(c) Assuming the output is short circuited, for matching the input to 50 Ω, a π
section is used, as shown in Figure 9.21. Determine the values of the capacitors
and the inductor with an input quality factor of 10.
(d) Calculate the matching bandwidth.

&JG

9JV &JV JGV &GV

JP9JV

Figure 9.20: Equivalent circuit model of the transistor in Example 9.8.

50Ω C2

+
Vs C1 L 1kΩ Cgs Cgd

Figure 9.21: The π matching network employed in Example 9.8.

Solution:
(a) The equivalent model of the transistor can be shown as in Figure 9.20. The
values can be found using the provided Y-parameters as
Y12 = − jωCgd ⇒ Cgd = 398 fF (9.144)

Y11 = jω Cgs +Cgd ⇒ Cgs = 1 pF (9.145)
Y21 = gm − jωCgd ⇒ gm = 1 mf (9.146)

Y22 = gds + jω Cgd +Cds ⇒ gds = 330 µf,Cds = 202 fF (9.147)

(b) The Rollet’s stability factor in terms of Y-parameters can be expressed as [5]
2g11 g22
k= (9.148)
|Y12Y21 | + Re{Y12Y21 }
9.8 Design of Two-Stage Amplifiers 413

Given the fact that g11 = 0 then k = 0 which suggests instability. Adding a 1 kΩ
resistor at the input, the Rollet’s stability factor can be rewritten as [5]

2 (g11 + GS ) g22 0.66

k= = = 1.375 (9.149)
|Y12Y21 | + Re{Y12Y21 } 6.73 − 6.25

This indicates that the circuit is unconditionally stable in this case, and no parallel
resistor is needed at the output.
(c) The value of the components can be found as

n2
Q= Ceq ω = 10 (9.150)
GS

n2
Let, GS = 1k, then Ceq = 1.59 pF, where
r
C1 +C2 1000
n= = = 4.47 (9.151)
C2 50

and
C1C2
Ceq = (9.152)
C1 +C2

Therefore, from the above

C1 = 7.08 pF, C2 = 2.05 pF (9.153)

For matching, we should have

1
= Ceq ω + b11 = 10 m + 8.79 m = 18.79 mf (9.154)
Lω
L = 8.47 nH (9.155)

(d) For estimating the matching network bandwidth, we calculate the total equiva-
lent resistance in parallel with the inductor

Rtotal = 1 k k 1 k = 500 Ω (9.156)

Rtotal
Qtotal = = 9.4 (9.157)
Lω
f0
BW = = 106 MHz (9.158)
Q

414 Chapter 9. Amplifier Design Using S-parameters

Example 9.9 Assume that the bandwidth of a receiver is equal to 30 kHz, and the
maximum allowable noise figure at the input is 7 dB. If the required SNRmin = 6 dB,
compute the sensitivity of the receiver.

Solution:
We have

Psen = (KT0 BF) (SNR)min (9.159)

Note 10 log KT0 = −174 dBm/Hz.

The sensitivity in decibles becomes:

Psen = −174 dBm + 10 log 30 × 103 + 7 dB + 6 dB = −116.2 dBm (9.160)

9.9 Conclusion
In this chapter, we discussed the design of RF/microwave amplifiers. We investigated
the stability condition at the input and the output in terms of S-parameters. We learned
about the radii and the centers of the stability circles at the source and at the load
reflection coefficient planes. After resolving the stability problem, we presented three
distinct definitions for the power gain of a two-port amplifier which were the operating
power gain, the APG, and the transducer power gain. Then, we introduced the constant
operating power gain contours on the load plane and the constant APG contours on
the source plane over the Smith chart. Subsequently, we provided the definition of the
noise figure and introduced constant NF contours on the source plane. Finally, a 3-step
design procedure was provided by means of which the trade-off between noise figure
and the power gain can be achieved, leading to the low-noise design with proper power
gain.

9.10 References and Further Reading

1. D. Pozar, Microwave Engineering, fourth edition, Hoboken, NJ: J. Wiley &
Sons, Inc., 2012.
2. G. Gonzalez, Microwave Transistor Amplifiers: Analysis and Design., NJ:
Prentice-Hall, 1994.
3. U.L. Rohde, A.M. Pavio, G.D. Vendelin, Microwave Circuit Design Using
Linear and Nonlinear Techniques, Hoboken, NJ: J. Wiley & Sons, Inc., 2005.
4. R. Chi-Hsi Li, RF Circuit Design, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
5. R.S. Carson, High Frequency Amplifiers, New York, NY: J. Wiley & Sons, Inc.,
1982.
6. J. Everard, Fundamentals of RF Circuit Design with Low Noise Oscillators,
United Kingdom: J. Wiley & Sons, Inc., 2000.
7. P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog
Integrated Circuits, fifth edition, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
9.10 References and Further Reading 415

8. T.H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, second

edition, Cambridge: Cambridge University Press, 2003.
9. M.C. Albuquerque, F. Farzaneh, J. Obregon, “Définition théorique des paramètres
en fort niveau d’un multipôle actif non linéaire,” Annales des Télécommunica-
tions, Vol. 40, Issue 3, pp. 106–110, March 1985.
10. J. Obregon, F. Farzaneh, “Definition of Nonlinear Reflection Coefficient of a
Microwave Device Using Describing Function Formalism,” IEEE Transactions
on Microwave Theory and Techniques, Vol. 32, Issue 4, pp. 452–455, May
1984.
416 Chapter 9. Amplifier Design Using S-parameters

9.11 Problems
Problem 9.1 Prove that in the case where the source and the load impedances are
equal to the characteristic impedance, the transducer power gain (GT ) can be written
as GT = |S21 |2 . Then calculate the operating power gain (GP ) and the APG (GA ) in
terms of the S-parameters of the transistor.
Problem 9.2 Consider the circuit shown in Figure 9.22. Compute GT , GA , and GP ,
with the following parameters:
Γs = 0.49∠ − 150◦ , ΓL = 0.56∠90◦
S11 = 0.54∠165◦ , S12 = 0.09∠20◦ , S21 = 2∠30◦ , S22 = 0.5∠ − 80◦

Output
50Ω Input
matching 50Ω
+ matching
network
Vs network

ΓS ΓL

Figure 9.22: The amplifier circuit for determining various power gains.

Problem 9.3 The S-parameters for three transistors are given. Comment on their
stability by drawing the stability circles at the source and the load planes.
◦ 0 ◦ 00 ◦
S11 = 0.674∠ − 152 S11 = 0.385∠ − 55 S11 = 0.7∠ − 50
◦ 0 ◦ 00 ◦
S12 = 0.075∠6.2 S12 = 0.045∠90 S12 = 0.27∠75
◦ 0 ◦ 00 ◦
S21 = 1.74∠36.4 S21 = 2.7∠78 S21 = 5∠120
◦ 0 ◦ 00 ◦
S22 = 0.6∠ − 92.6 S22 = 0.89∠ − 26.5 S22 = 0.6∠80

Problem 9.4 Show that as S12 approaches zero, the centers and the radii of the input
and output stability circles can be estimated as CS ≈ S111 , rS ≈ 0,CL ≈ S122 , rL ≈ 0.
Given |S11 | < 1 and |S22 | < 1, what would you deduce from this?
Problem 9.5 Two different amplifiers with the specified S-parameters are cascaded
as shown in Figure 9.23. Compute the overall S-parameters of these cascaded amplifiers
in terms of their corresponding S-parameters (Hint: use the concept of loaded two-port
S-parameters).

D D
E 6$ 6$ 6% 6% E
3RUW 3RUW
6$ 6$ 6% 6%

Figure 9.23: Cascaded amplifiers to determine the overall S-parameters.

Problem 9.6 Consider the circuits illustrated in Figure 9.24. Determine how resistive
loading affects the overall S-parameters and the stability of the two-port network. The
transistor’s S-parameters are:
S11 = 0.69∠ − 78◦ , S12 = 0.033∠41.4◦ , S21 = 5.67∠123◦ , S22 = 0.84∠ − 25◦
9.11 Problems 417

Hint: (1) Use the results of problem 9.5, (2) For the series resistance two-port S-
parameters, one can easily show that S21 = 1 − S11 , and for the parallel resistance
two-port S21 = 1 + S11 .

29Ω
9Ω

500Ω
71.5Ω
(a) (b) (c) (d)

Figure 9.24: A transistor cascaded by either of series or parallel resistances.

Problem 9.7 Prove that maximum transducer power gain, GT , occurs in a unilateral
amplifier once we have Γs = S11 ∗ , ΓL = S22 ∗ .
Problem 9.8 S-parameters for a transistor in a 50 Ω-system are given as:
S11 = 2.3∠ − 135◦ , S12 = 0, S21 = 4∠60◦ , S22 = 0.8∠ − 60◦
Comment on the stability of this transistor. Draw the circle corresponding to GA = 4 dB.
Then, design the matching network such that with GA = 4 dB, |Γout | is minimum.
Problem 9.9 Design a transistor amplifier in a 50 Ω-system with maximum GT . The
S-parameters are given as:
S11 = 0.277∠ − 59◦ , S12 = 0.078∠93◦ , S21 = 1.92∠64◦ , S22 = 0.848∠ − 31◦ .
Problem 9.10 Considering the following S-parameters, first plot the stability circles.
Secondly, determine GP where Γs = 0.2∠145◦ , ΓL = 0. Finally, determine the maxi-
mum value of GP .
S11 = 0.5∠45◦ , S12 = 0.4∠145◦ , S21 = 4∠120◦ , S22 = 0.4∠ − 40◦ .
Problem 9.11 Consider an amplifier with a silicon transistor as depicted in
Figure 9.25. First determine the required resistances RC and RB for the quiescent
point of VCE = 10V, IC = 5 mA. Secondly, compute the input and output impedances
and consequently the source and the load reflection coefficients. The operating fre-
quency is 300 MHz.

12V
RC 1nF

70nH
RB
1nF 30pF
β=100 70pF
50Ω
50Ω
+ 40nH
Vs

ΓS ΓL

Figure 9.25: A transistor amplifier with corresponding load and source

impedances and the bias circuitry.
418 Chapter 9. Amplifier Design Using S-parameters

Problem 9.12 The S-parameters and the noise parameters of a transistor are given at
1 GHz as:
S11 = 0.6∠170◦ , S12 = 0.05∠16◦ , S21 = 2∠30◦ , S22 = 0.5∠ − 95◦
Fmin = 2.5 dB, Γopt = 0.5∠145◦ , Rn = 5 Ω
Verify the stability and determine the maximum GA . Then, plot the constant power
gain contour having a gain 3 dB lower than GA,max . Furthermore, plot the constant NF
contours for NF = 3 dB and NF = 4 dB. Finally, derive the NF of the amplifier at the
maximum power gain point (in the source impedance plane).
Problem 9.13 Consider Figure 9.26. We wish to design a 2 GHz amplifier having
NF = 2 dB with maximum possible GT . First determine the required ΓS and corre-
sponding GA . Then compute the required Γout . What would be the value of GT then?
The S-parameters are given at 2 GHz as:
S11 = 0.646∠172◦ , S12 = 0.051∠13.5◦ , S21 = 3.042∠47.9◦ , S22 = 0.642∠ − 64◦

Constant
Γi
NF
contours

4dB
3.5dB
3dB
2.5dB
2dB

1.7dB

Γr

16dB
15dB
14dB
12dB
10dB
Constant
available gain
contours

Frequency=2GHz, 10V, 5mA

Figure 9.26: The Smith chart to design an amplifier with specific NF and GA .

Problem 9.14 Consider the cascade of amplifiers/mixer depicted in Figure 9.27.

Calculate the overall NF and the APG, GA , of the chain.
9.11 Problems 419

) G% ) G% ) G% ) G% ) G%

*$ G% *$ G% /RVV0 G% *$ G% *$ G%
0L[HU
,1 287
$PS $PS $PS $PS

Figure 9.27: The cascade amplifiers/mixer for determination of the overall

noise figure.

Problem 9.15 For the circuit depicted in Figure 9.28, calculate the input and the
output power in dBm as well as the output voltage in dBVolts.

ZIN=50Ω ZOUT=50Ω

50Ω
Es,rms= + GP1=13dB GP2=13dB GP3=10dB GP4=9dB 50Ω
79.5mV

Figure 9.28: A cascade of amplifiers for the output power calculations.

Problem 9.16 For the MOS amplifier operating at 2 GHz whose S-parameters are
S11 = 0.3∠160◦ , S12 = 0.03∠62◦ , S21 = 6.1∠65◦ , S22 = 0.4∠ − 38◦ , and depicted in
Figure 9.29
1. Neglecting S12 determine the input and the output matching loads and calculate
Gp . Assuming ideal inductors and capacitors, determine their required values.
2. If L3 is replaced by a short-circuited 50 Ω stub, calculate the electrical length of
the line as a fraction of the wavelength.

VG VDD

RFC L3
C4
50Ω C∞ L2

+ 50Ω
vS C1

Figure 9.29: The transistor MOS amplifier for input and output matching.
420 Chapter 9. Amplifier Design Using S-parameters

Problem 9.17 Consider a transistor with the following parameters at 2 GHz:

S11 = 0.55∠170◦ , S12 = 0.01∠23◦ , S21 = 1.68∠26◦ , S22 = 0.84∠ − 67◦
Fmin = 2 dB, Γopt = 0.48∠165◦ , Rn = 6.25 Ω

1. Comment on the stability and determine the maximum GT .

2. Design the amplifier for the minimum NF and the maximum possible power
gain. Find the proper values of ΓS and ΓL , determine the maximum possible
power gain. Design the input and the output matching networks using a pair of
lumped elements (capacitors and inductors).
3. In a second attempt design the amplifier for the maximum GT , determine the
required ΓS and ΓL in this case. Determine the corresponding NF in this case.
4. If the amplifier is followed by a mixer with NF = 7 dB, calculate the overall
NF in either of the cases in parts 2 and 3. In which case the receiver would be
more sensitive?
Problem 9.18 Consider Figure 9.30. Our objective is to design a two-stage amplifier.
The second stage being an amplifier with G2 = 14 dB and NF = 5 dB at 1.6 GHz,
preceded by a SiGe internally matched LNA, BGU7007 manufactured by NXP (see the
datasheet at www.nxp.com). Determine the required bias voltage and the bias current
of the LNA for an overall gain GT ≥ 30 dB and the total noise figure NFT ≤ 1.2 dB.

50Ω 50Ω 50Ω 50Ω

G1 G2

BGU7007 NF2=5dB
G2=14dB

Figure 9.30: The two-stage amplifier to be designed using a BGU7007 inter-

nally matched LNA.

Problem 9.19 Assume a transistor with the following S-parameters at 1 GHz:

S11 = 0.6∠ − 180◦ , S12 = 0.01∠ − 80◦ , S21 = 2.5∠30◦ , S22 = 0.6∠ − 83◦
Design an amplifier using this transistor with the power gain, GP of 9.5 dB (plot the
constant power gain contour in the load plane and choose the minimum |ΓL | point).
Now determine the appropriate ΓS such that the input is matched to it. Design the
matching network using T-lines (on a substrate of εeff = 3.3) and open/short stubs.
Problem 9.20 The S-parameters and the noise parameters of a transistor operating
at 4 GHz with VCE = 10V, IC = 4mA, are given as:
S11 = 0.552∠169◦ , S12 = 0.049∠23◦ , S21 = 1.681∠26◦ , S22 = 0.839∠ − 67◦
Fmin = 2.5 dB, Γopt = 0.475∠166◦ , Rn = 3.5 Ω
1. Using the constant noise and the constant gain contours given in Figure 9.31,
provided that the following stage has a NF of 7 dB. Choose the source reflection
coefficient (impedance) such that the overall NF becomes at most 3.2 dB.
2. If the minimum required gain is equal to 10.7 dB, regardless of the second stage,
9.11 Problems 421

choose a point on the contours depicted in Figure 9.31 to have the minimum
noise figure in this case. Determine the required load reflection coefficient to
match the output, and then design the matching network in a 50 Ω system at
both the input and the output using air-filled T-lines (εr = 1) and open/short
stub.

Γi
Constant
NF
contours

N1
N2
N3
N4

N5
Γr

G1
G2
G3
G4
G5
G6
G7
G8
G9
Constant
gain
contours
Gmax=14.7dB; G1=14.5dB; G2=13.7dB; G3=12.7dB; G4=11.7dB;
G5=10.7dB; G6=9.7dB; G7=8.7dB; G8=7.7dB; G9=6.7dB;

N1=3dB; N2=2.9dB; N3=2.8dB; N4=2.7dB; N5=2.6dB;

Figure 9.31: The constant noise and the constant available gain circles at the
source plane of the transistor at 4 GHz.

Problem 9.21 Calculate the maximum GT , if stable, for the Motorola silicon bipolar
transistor with part number MRF962 at 700 MHz at different biases of VCE = 5V, IC =
10mA, 25mA, 50mA where the S-parameters data are as follows:

Table 9.1: Part of MRF962 datasheet.

VCE IC f S11 S21 S12 S22

(Volts) (mA) (MHz) |S11 | ∠φ |S21 | ∠φ |S12 | ∠φ |S22 | ∠φ
5 10 700 0.78 −176 3.16 77 0.071 26 0.23 −117
5 25 700 0.80 178 3.82 78 0.055 40 0.31 −158
5 50 700 0.81 176 4.09 78 0.048 50 0.38 −169
5 25 1500 0.81 164 1.82 59 0.086 42 0.34 −167

Problem 9.22 Evaluate stability at 1.5GHz and for VCE = 5V, IC = 25mA, and design
the matching network for maximum transducer gain at this frequency. Use Table. 9.1.
422 Chapter 9. Amplifier Design Using S-parameters

Problem 9.23 In the given amplifier depicted in Figure 9.32, match the input and
the output at the frequency of 318.3 MHz. First determine the input and the output
admittances of the transistor at the operating frequency, and then find the required
reactive components to match the input to 50 Ω and the output to 20 Ω.

L1 Lg rg rd Ld L2

50Ω
C1 Cgs gmv rds Cds C2 20Ω

rds=400Ω
Cgs=15pF
Cds=5PF
rg=12Ω gm=50mS
Ld=2.0nH
Lg=2.5nH
rd=5Ω

Figure 9.32: The equivalent circuit of a FET transistor and the associated
matching circuits.

Problem 9.24 The Y-parameters of the cascode MOSFET stage at 159 MHz are
depicted in Figure 9.33. Determine the reactive matching components for the maximum
transducer power gain and compute the mentioned power gain.

L3
L1

RS
L2 RL
+ C1
Vs

yi=2.6+j12 ms
yr=0 RS=RL=75Ω
yf=-56+j14 ms
yo=1.1+j2.1ms

Figure 9.33: A cascode MOS stage amplifier.

Problem 9.25 The Y-parameters of a RF transistor are as depicted in Figure 9.34.

Moreover, one of the constant noise circles is given on the source admittance plane.
First determine the optimum noise admittance (Hint: transform the relation 9.161 into
a constant noise figure circle equation and from there determine GO and BO ). Then,
determine the required output admittance for the conjugate match condition. Finally,
design the required LC circuits to match the input and the output to the 50 Ω reference
impedance.

Rn h i
F = Fm + (Bs − Bo )2 + (GS − Go )2 (9.161)
GS
9.11 Problems 423

Bs(ms)

-6 2.5+j5 0
F=3dB Y T= mS
-5
52-j21 1+j2.5
-4
-3
-2
-1 Gs(ms)

1 2 3 4 5 6 7
L1 L2
YT
RS
C1 C2 RL

Figure 9.34: The low-noise amplifier with the corresponding input and output
matching circuits.

Problem 9.26 In a low-noise amplifier, a noise figure of F = 3 (or 5 dB) has been
measured for three consecutive source admittances, YS1 , YS2 , and YS3 as depicted in
Figure 9.35. Draw the corresponding constant noise figure circle and from there
determine the corresponding optimum noise admittance. Use Equation 9.161.

Bs(ms)

-60
YS1=37.3-j20 mS
-50
YS2=2.7-j20 mS
-40
YS3=20-j2.7 mS
-30
-20
-10 GS

10 20 30 40 50 60 70

Figure 9.35: The measured source admittances for a noise figure F = 3 (source
admittance plane).
ID

VGS

10. Power Amplifier

RF power amplifiers (PAs) consume the highest amount of power among all the
transmitter blocks. While advancements in technology have resulted in aggregating
all transmitter blocks into one single integrated circuit, the PA block is still integrated
separately in many applications. In a transmitter chain, the data signal modulates
properly the carrier signal and is then upconverted from the IF to the RF frequency.
Afterward, a PA provides the necessary RF power level to transmit the signal according
to the standard of interest, and the signal is radiated into the air by the antenna. By
virtue of the power amplification, the PA mostly operates in a nonlinear or large-
signal regime which mandates careful considerations regarding both its design and
its simulation. One of the most important trade-offs in a PA is that of efficiency and
linearity, as shown in Figure 10.1. In customary PAs, more linearity is expected to
result in less efficiency and vice versa, while better linearity and good efficiency are
both required to obtain a high data rate and low power consumption, respectively.
PA nonlinearity stems from the large-signal behavior of the active devices. An
important issue that must be taken into consideration is the presence of the signal har-
monics as well as IM products which have a potentially adverse effect on the adjacent
channels. For this reason, the standards stipulate a measure called adjacent channel
power ratio (ACPR) to regulate this issue. Furthermore, efficiency considerations im-
pose lower limits on the supply voltage and active device architecture. In other words,
the voltage source must be capable of providing sufficiently high currents and the active
device should have a high voltage swing without entering the breakdown region. For
driving purpose, a predriver stage is often used before the PA to provide the required
signal level at the PA input. Noting the fact that the antenna impedance is in the order
of 50 Ω and the breakdown voltage limit in active devices, an impedance matching
circuit is utilized to match the required load impedance to the antenna impedance
level. Considering the limited supply voltage for higher powers, we would need higher
current swings which means lower impedance levels at the PA output. Impedance
matching circuits generally introduce a finite loss due to use of low-Q inductors or
capacitors, and consequently causing a poorer efficiency.
426 Chapter 10. Power Amplifier

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Figure 10.1: A graphical representation of the compromise between the linearity

and the efficiency in a typical power amplifier.

In this chapter, PA design specifications are initially discussed. Then, different PA

classes are introduced, followed by assessing a number of linearization techniques.

10.1 PA Specification
In this section, the most vital design specifications of PAs are introduced and studied.
These specifications consist of the efficiency, the output power, the in-band noise, the
gain, the linearity (AM to AM and AM to PM distortion, ACPR, and error vector
magnitude (EVM)), and the stability. In general, power amplification can be discussed
in two categories dependent on the linearity of the operating region. Assume the PA as
a block with a single-tone input as

x(t) = Acos(ωct + θ ) (10.1)

Then, the output signal is given by Equation 10.2

y(t) = |G|Acos(ωct + θ + ∠G) (10.2)

where G is the PA gain. Unlike the linear amplification, the output signal in a nonlinear
amplifier will take the form of

y(t) = M(A(t))cos(ωct + θ + ∠A(t)) (10.3)

M(A(t)) and ∠A(t) show AM to AM and AM to PM conversion, respectively. If the

input contains multiple tones, linear amplification is preferred so that no IM products
are generated, although nonlinear amplification yields a higher efficiency in certain
cases.

10.1.1 PA Efficiency
Efficiency is the most critical parameter in PA design. A PA with 50% efficiency
delivering 1W power (or 30 dBm) to a 50 Ω load, for example, also dissipates 1 W
10.1 PA Specification 427

power in the circuit, and thus having a total power consumption of 2 Watts. The
dissipated power generates heat and necessitates specific measures in the circuit
implementation, also shortening the battery life. In the context of PA design, power-
added-efficiency (PAE) and efficiency are defined as

Pout,RF − Pin,RF
PAE = (10.4)
Ptotal,DC

Pout,RF ∼ Pout,RF
η= = (10.5)
Ptotal,DC + Pin,RF Ptotal,DC

In Equation 10.4, the numerator accounts for the difference between high-frequency
output power and the input power, and the denominator represents the total DC power
dissipation. Equation 10.4 gives the power transferred to the load minus the input power
divided by the DC power, and is called PAE for that matter. As studied in previous
chapters, the output power exhibits a compressive behavior as a function of the input
power as shown in Figure10.2. In other words, owing to nonlinear amplification,
the output signal no longer increases in proportion to the input signal when the input
amplitude exceeds a certain value. The rate of change of the numerator in Equation 10.4
becomes smaller, leading to a compression in PAE as shown in Figure 10.3.
As an example for the importance of PAE in cell phones, the higher the PAE of a
cell phone’s PA, the longer would be the battery lifetime and the call durations.

10.1.2 PA Output Power

Consider Figure 10.4 where a PA is shown followed by a band-pass filter (or a selective
impedance matching network).

Pout
(dBm)
Compression curve
30
25
20
15
Pin
-10 -5 0 5 10 (dBm)

Figure 10.2: Typical compression curve of a power amplifier.

428 Chapter 10. Power Amplifier

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Figure 10.3: Compression curve of the PAE of an amplifier.

PSPEC+L
L PSPEC
PA

Figure 10.4: Power amplifier followed by a matching network.

The band-pass filter (BPF) is used to suppress the spurs and the undesired har-
monics generated by the PA, also providing a proper load impedance for the amplifier.
Nevertheless, the ultimate efficiency is degraded due to the insertion loss of the filter.
To alleviate this issue, the PA must be designed for higher output power and better
efficiency. For Figure 10.4, PAE can be written as
Pout ∗ L − Pin
PAE = (10.6)
Ptotal,DC
Here, L is the insertion loss of the output filter. Note that the numerical value of
L should be used in the above equation instead of its dB value. Each communication
standard allows a specified amount of power to be transmitted. The effective radiated
power (ERP) can be defined as the product of the power supplied to the antenna by the
antenna gain relative to a half-wave dipole in a given direction. Another definition also
exists as equivalent isotropically radiated power (EIRP) which is the product of the
power supplied to the antenna by the antenna gain in a specific direction relative to an
isotropic antenna. In general

EIRP ≈ ERP + 2.2 dB (10.7)

where the 2.2 dB term is the gain of half-wave dipole antenna with respect to an
isotropic antenna.
Table 10.1 shows various specifications of output power for a number of commu-
nication standards.
Another parameter of the PA is characterized with its probability density function
(PDF). To be adapted to the output power requirements (e.g., in a CDMA system), the
10.1 PA Specification 429

Table 10.1: Output power specifications for a few communication systems in

their different classes.

Wireless Standard Maximum mobile station output power

PCS band Class I Class II Class III
CDMA (ERIP) 28–33 dBm 22–30 dBm 18–27 dBm
(IS-95) Cellular band Class I Class II Class III
(ERP) 31–38 dBm 27–34 dBm 23–30 dBm
WCDMA 27 dBm
Class I Class II Class III
AMPS (ERP) 36 dBm 32 dBm 28 dBm
Class 2 Class 3 Class 4
GSM 39 dBm 37 dBm 33 dBm
Class 1 Class 2 Class 3
DCS-1800 30 dBm 24 dBm 36 dBm
4G LTE 23 dBm (maximum possible output power)
IEEE802.11b 20 dBm
Class 1 Class 2 Class 3
Bluetooth 20 dBm 4 dBm 0 dBm

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Figure 10.5: PDF of the transmitted power of the PA for a mobile set in an
urban or suburban area.

mobile unit mostly transmits a power inferior to the maximum value. For this reason,
in urban areas with more base stations, the chances of successful transmissions are
higher even at low power levels, while power should be necessarily high in suburban
areas. The PDF depicts the probability distribution of the power transmitted from a
CDMA transmitter unit, a sample of which is shown in Figure 10.5 for an amplifier in
an urban area or in a suburban area.

10.1.3 Receive-band Noise

Consider the full-duplex system of Figure 10.6. In full-duplex systems such as CDMA,
the PA output at the transmitter degrades the sensitivity of the receiver system. The
430 Chapter 10. Power Amplifier

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Figure 10.6: The effect of the TX-band noise at the receiver in a full-duplex
system.

duplexer provides about 30 to 40 dB isolation between the receive and the transmit
paths the reason for which the transmitted signal could degrade the receiver sensitivity
by leaking to it. In fact, the PA amplifies the noise in the receiver band as well as
the desired signal in the transmitter band. The PA noise itself will be added to the
receiver, as such degrading its performance. Figure 10.6 demonstrates this process.
In Figure 10.6, the base station transmits the signal with a large output level and the
attenuated version of the original signal is received at the receiving antenna. The PA
amplifies the signal in the transmitter band, but it leaks to the receive path through the
duplexer (due to finite isolation between the two paths). In addition, the PA noise in
the receiver band is only slightly attenuated by the duplexer and is added to the receive
path. Consequently, detecting the received signal will be tougher, i.e, the receiver
sensitivity will be degraded.

10.1.4 PA Gain
In practice, the minimum required PA gain is affected by four parameters:
• Maximum output power
• Loss after the PA
• Maximum driver output power
• Loss after the driver
Now, consider the system in Figure 10.7 in which a driver precedes a PA and there are
interstage matching networks with a certain loss.
The overall minimum gain of the power amplifier in Figure 10.7 then can be
obtained as

Gainmin (dB) = PSPEC,out (dBm) + L(dB) + Ld(dB) − Pmax Driver (dBm) (10.8)
10.1 PA Specification 431

PmaxDriver (PSPEC, out+L)

Ld L PSPEC, out
Driver PA

Figure 10.7: A PA with the PA driver and the interstage matching networks.

The maximum permissible gain of the PA is determined by parameters such as the

driver noise in the receive band and the input–output isolation which prevents probable
oscillation in the amplifier chain. The practical PA gain is typically within the range of
10 to 30 dB. Figures 10.8 and 10.9 show the compression effect in a PA.

10.1.5 Linearity Considerations in PA

Another important parameter to assess a PA’s performance is its linearity. Generally,
there are two types of nonlinearities to be considered in PAs:
• Amplitude nonlinearity (AM to AM distortion)

26
24 Pout,Max L
Pout(dBm)

22 PSPEC
20
18
16
Pin,Max
14
-10 -8 -6 -4 -2 0 2 4
Pin(dBm)

Figure 10.8: Typical compression of the output power versus the input power
of a PA.

26
24
Gain (dB)

22
20 Gain compression
18 at peak power
16
Pin,Max
14
-10 -8 -6 -4 -2 0 2 4
Pin(dBm)

Figure 10.9: Typical gain compression in a PA.

432 Chapter 10. Power Amplifier

• Phase nonlinearity (AM to PM distortion)

These nonlinearities have adverse effects on system performance which are stated
below:
• Production of undesired harmonic components
• Spectral regrowth (degradation in ACPR)
• Degradation in noise power ratio (or reduction in SNR)
• Increase in error vector magnitude
Amplitude nonlinearity (AM to AM distortion): The degree of amplitude nonlin-
earity can be defined by parameters such as 1 dB compression point (P1dB ), third-order
intercept point (IP3 ), and carrier to intermodulation ratio (C/I). It is instructive to
restate the important parameters regarding the nonlinearity:
P1dB is the point where the nonlinear output gain of the system drops by 1 dB below
the linear output gain. This point is shown on the curve of the output power in
terms of the input power in Figure 10.10.
IP3 is the point where the linear output power curve of the system intersects the
third-order IM curve (in a two-tone excitation), as shown in Figure 10.10.
C/I is defined as the ratio of the amplitude of the desired signal at the system output to
the maximum intermodulation distortion term (IMD) (typically, C/I > 30dB).
Phase nonlinearity (AM to PM distortion): This type of nonlinearity usually occurs
once there is a nonlinear reactance like a voltage-dependent capacitor in the system
(e.g, junction capacitors). Consider the circuit in Figure 10.11 where a resistor and a
voltage-dependent capacitor are part of the circuit with a sinusoidal excitation current.
Imagine a nonlinear capacitance defined by the following dynamic equation

q = C1 v +C2 v2 +C3 v3 (10.9)

Now, consider this nonlinear capacitance is driven by a sinusoidal voltage

v(t) = V1 cos(ωt) (10.10)

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in a nonlinear system with a two-tone input.
10.1 PA Specification 433

Vout
+
vS R GmvS R CD(V1)
-

vS=VScos(ωt)

Figure 10.11: An amplifier with a nonlinear capacitance at its load.

Then, the capacitance’s charge would have the following form

C2V12 C3V13

3
q = C1 + C3V12 V1 cos (ωt) + (1 + cos (2ωt)) + cos (3ωt) (10.11)
4 2 4
Now, retaining the fundamental term and ignoring the DC and higher harmonic terms,
we can define a large-signal dynamic capacitance as
3
CD (V1 ) = C1 + C3V12 (10.12)
4
Considering this large-signal dynamic capacitance, one can obtain the output as
GmVs R
vout (t) = q cos (ωt + φ (t)) (10.13)
1 + (RωCD (V1 ))2

where
GmVs R
V1 = q (10.14)
1 + (RωCD (V1 ))2

By substituting the value of CD (V1 ) from Equation 10.12, one can rewrite Equa-
tion 10.14 in the following form
2
3 3
RωC3 V16 + (Rω)2 C3C1V14 + 1 + (RωC1 )2 V12 − (GmVS R)2 = 0 (10.15)
4 2
By resolving the above equation, one can obtain the value of V12 , and therefore obtain
the phase value as
φ (t) = −tan−1 (RωCD (V1 )) (10.16)
According to Equation 10.16, the output phase is a function of the input voltage
amplitude. Figure 10.12 shows a sample of phase shift in the output of a system as the
input signal amplitude increases. As the input signal power is raised, the output phase
begins to change significantly after passing a threshold power.
It should be noted that phase modulation results in spectral regrowth. To gain
a better understanding of spectral regrowth, consider the output signal of a phase-
modulated single-tone sinusoid as
Vout(t) = A cos(ωct + k sin(ωbt))
= A cos(ωct) cos(k sin(ωbt)) − A sin(ωct) sin(k sin(ωbt)) (10.17)
434 Chapter 10. Power Amplifier

AM to PM curve
-10

Φout(degree)
-12
-14
-16
-18
-20
-22
-10 -8 -6 -4 -2 0 4
Pin(dBm)

Figure 10.12: A typical AM to PM characteristics for a nonlinear amplifier.

Assuming k 1, Equation 10.17 can be rewritten as below

Vout(t) ≈ A cos(ωct) − Ak sin(ωct) sin(ωbt)

= A cos(ωct) + Ak Ak
2 cos((ωc + ωb )t) − 2 cos((ωc − ωb )t) (10.18)

Figure 10.13(a) shows the one-sided frequency spectrum of Equation 10.18 for k 1,
only the first harmonic of the baseband will appear about the carrier. In the case
where k ≈ 1 or k > 1 (Figure 10.13(b)), the harmonics of ωb will also appear in both
sidebands and we can observe a certain spectral regrowth where in Equation 10.17,
the carrier multipliers cos(k sin(ωbt)) and sin(k sin(ωbt)) can be expressed in terms of
Bessel functions of even and odd order, respectively

cos(k sin(ωbt)) = J0 (k) + 2J2 (k) cos(2 cos(ωbt)) + . . . (10.19)

sin(k sin(ωbt)) = 2J1 (k)(sin(ωbt)) + 2J3 (k)(sin(3ω bt)) + . . . (10.20)

As such, the even and the odd harmonics of the baseband signal will also modulate the
in-phase and the quadrature components of the carrier and the signal spectrum will
grow. In the following sections, some effects of nonlinearity will be briefly discussed:
Generation of undesired harmonic components: High gain and high output
voltage swing limitations lead the PA to perform in a large-signal regime. This results

Vout Vout
k<<1 k<1 or k≈1

ω ω
ωc-3ωb
ωc-2ωb

ωc
ωc-ωb

ωc+ωb
ωc+2ωb
ωc+3ωb
ωc
ωc-ωb
ωc+ωb

(a) (b)

Figure 10.13: Output spectrum of Figure 10.11 due to PM conversion, (a)

k 1, and (b) k < 1 or k ≈ 1.
10.1 PA Specification 435

in distortions in the output signal and production of undesired harmonic components as

depicted in Figure 10.14(a). These components will grow as the input signal power is
raised. To determine the influence of the undesired components, a parameter called the
total harmonic distortion (THD) is defined as the square root of ratio of the summation
of all undesired components to the main harmonic in percentage:
v
u ∞
u ∑ I2
u dn
THD = 100 × t n=22 (10.21)
Id1

where Idn is the current component of the nth harmonic of the main frequency. Further-
more, if two or more blockers are present at the input of the nonlinear system, the IM
causes more spurious components to be generated (Figure 10.14(b)). This is why using
filters in the output of PAs is common to attenuate the undesired harmonic components.

Spectral regrowth: The nonlinear performance of the system results in the gener-
ation of undesired components in the spectrum, having adverse effects on the adjacent
channel. Both AM to AM and AM to PM conversions cause the spectrum to regrow
at the output of the amplifier. Adjacent channel power ratio (ACPR) represents the
amount of spectral regrowth in a PA, thus being a criterion of its linearity. Imagine
a nonlinear tuned amplifier as depicted in Figure 10.15 where its nonlinear dynamic
transconductance is described as follows

i = αv + β v3 + γv5 (10.22)

Here

v = VS1 cos (ω1t) +VS2 cos (ω2t) (10.23)

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Figure 10.14: Generation of undesired harmonic and intermodulation compo-

nents at the output of a nonlinear PA.
436 Chapter 10. Power Amplifier

Vout

+
vS2 +
-
+ v i=f(v) RL CL LL
vS1 -
-

Figure 10.15: A nonlinear tuned amplifier corresponding to its nonlinear

transconductance.

Then

i =α (vS1 + vS2 )

+ β v3S1 + 3v2S1 vS2 + 3vS1 v2S2 + v3S2

+ γ v5S1 + 5v4S1 vS2 + 10v3S1 v2S2 + 10v2S1 v3S2 + 5vS1 v4S2 + v5S1 (10.24)

Putting the sinusoidal voltage terms in Equation 10.24, we can compute the output
fundamental voltages as well as the third and the fifth IM terms which happen to be
within the output bandwidth. The third and fifth IM currents will have the following
forms
2V
3βVS1 S2
I2ω1 −ω2 = cos ((2ω1 − ω2 )t) (10.25a)
4
2
3βVS1VS2
I2ω2 −ω1 = cos ((2ω2 − ω1 )t) (10.25b)
4

3 V2
5γVS1 S2
I3ω1 −2ω2 = cos ((3ω1 − 2ω2 )t) (10.26a)
8
2 V3
5γVS1 S2
I3ω2 −2ω1 = cos ((3ω2 − 2ω1 )t) (10.26b)
8

The output voltage including the IM terms (considering flat impedance, RL , for all of
the terms) can be described by the following expression.

vout 'αRL (VS1 cos (ω1t) +VS1 cos (ω2t))

3β RL 2 2

+ VS1VS2 cos ((2ω1 − ω2 )t) +VS1VS2 cos ((2ω2 − ω1 )t)
4
5γRL 3 2 2 3

+ VS1VS2 cos ((3ω1 − 2ω2 )t) +VS1 VS2 cos ((3ω2 − 2ω1 )t)
8
(10.27)
10.1 PA Specification 437

As it is seen here when there is at least two carrier frequency components at the
input, the output spectrum will be widened by a factor of three due to the third-order
IM and it will be widened by a factor of five due to the fifth-order IM. This results
in a spectral regrowth at the sidebands of the carriers as seen in Figure 10.16. Also,
Figure 10.17 depicts spectral regrowth and the resulting distortion in the time domain.
Note that while the fundamental terms grow with a slope of 10 dB/decade, the

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Figure 10.16: Spectral regrowth in a nonlinear PA as seen in the frequency

domain.

Aout1
Ain1

t t
Vin Vout

f Linear PA f
123 123

Aout1
Ain1

t t
Vin Vout

f Nonlinear PA f
123 123

Figure 10.17: Spectral regrowth in a nonlinear PA, single tone shown in the
time domain.
438 Chapter 10. Power Amplifier

third-order IM terms grow with a slope of 30 dB/decade, and the fifth-order IM terms
grow with a slope of 50 dB/decade. This point indicates that the input of the power
amplifiers should not be more than a specified level in order to maintain the required
signal to IM ratio or the required ACPR.
For instance, in CDMA (IS-95), ACPR is defined as the ratio of the available
power at 1250 kHz offset frequency (with respect to the carrier) in a 30 kHz bandwidth
to the available power in the main channel (at the center frequency) within the same
bandwidth, as shown in Figure 10.18. Therefore, ACPRLo and ACPRHi can be defined
as

PLo
ACPRLo = (10.28a)
Po
PHi
ACPRHi = (10.28b)
Po

The simplest method to measure ACPR in simulations is to excite the PA with a

modulated input. If the fast Fourier transform (FFT) of the output is calculated, ACPR
will be obtained. Simulation time is expected to be very long since the envelope
frequency is mainly much lower than the carrier frequency. Therefore, another method
is used to calculate ACPR which is believed to be more efficient. With a high difference
between the modulation frequency and the carrier frequency, this method can help
to estimate the ACPR through AM to AM and AM to PM characteristics. It can be
performed in the following steps:
1. Measuring or calculating the nonlinear PA gain function (G) to form the AM to
AM curve (AM to AM ⇒ G(A)).
2. Measuring or calculating the nonlinear PA phase function (P) to form the AM
to PM curve (AM to PM ⇒ P(A)).
3. Generating a baseband modulated input signal as Si (t) = A(t)∠φ (t).
4. Estimating the baseband modulated output signal as So (t) = G(A(t))∠[φ (t) +
P(A(t))].
5. Computing the FFT of the signal resulted in the previous step.
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Figure 10.18: ACPR definition in CDMA (IS-95) standard.

10.1 PA Specification 439

Care must be taken with regard to the above method as it is completely an approxi-
mative one. So its result might underestimate the spurious generated in the adjacent
channels (sidebands), because these unwanted components are mainly generated due
to a dynamic IM process.
Decreasing the noise power ratio: The nonlinear performance of PAs increases
the in-band noise power especially at the carrier frequency as well as generating
undesired components at the adjacent channels. This causes a lower SNR and thus
lower sensitivity in the receiver. In other words, the transmitted data will be noisy and
hard to be detected by the target receiver.
One of the ways to determine in-band distortion is measuring the noise power ratio
(NPR). For this purpose, the input signal is initially passed through a very sharp notch
filter to ensure that its in-band spectrum has no components at the carrier frequency.
Then, the resulted signal spectrum is applied to the nonlinear system as an input. The
nonlinear performance of the system will lead to spectral regrowth and increasing the
intermodulation noise floor level at the carrier frequency. Ultimately, the ratio of the
obtained IM noise power at the carrier frequency to the output signal power in the band
is calculated as NPR, as shown in Figure 10.19.
Increase in Error Vector Magnitude: Error vector magnitude (EVM) is defined
as the normalized distance between the desired and actual signal vectors as depicted in
Figure 10.20. Due to the nonlinear performance of the system, the yielded vector is
not expected to coincide with the desired signal vector in practice.
EVM is reported in both rms and peak values. Typical values range from 7% to
12% in the former and from 22% to 33% in the latter.
Increases in EVM can be interpreted as distortion in the data constellation at
the output signal. Undesired changes in phase and amplitude bring about errors in
detecting the modulated data, causing problems in the data transmission process. This
issue becomes more significant when the modulation level is higher, such as in QAM.
Figure 10.21 depicts a sample of data constellation distortion at the output for 16-QAM
modulation.

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Figure 10.19: Degradation of in-band SNR due to nonlinearity.

440 Chapter 10. Power Amplifier

Figure 10.20: Representation of error vector magnitude (EVM) in a sampling

I − Q constellation.

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Figure 10.21: A comparison of the input and the output constellation for a
16-QAM modulation for a nonlinear power amplifier in between.

10.1.6 PA Stability Considerations

Ideally, the PA is supposed to be strictly stable, i.e, it should maintain its stability for
any passive load or source impedances. In practice, PAs are stable for the VSWR≤ 6
(in all phases). Stability must be guaranteed even when the preceding and the following
stages are not perfectly matched. Some of the factors causing instability in PAs include:
• Existing of feedback between various amplifier stages
• Coupling between device terminals or wire-bonds
• Feedback due to device parasitics (e.g., Cµ or Cgd )
• Feedback paths through supply voltage and ground lines
Another factor is the gain peaking at subharmonics (e.g., at half the fundamental fre-
quency or one-third of the fundamental frequency) which could result in subharmonic
spurs and finally bias circuit oscillations.

10.2 PA Topologies
The PA topologies have evolved through the recent decades. Differences in linearity
and efficiency are the main reasons that impose various topologies. Another important
parameter that makes a significant difference in PA performance is the conduction
10.2 PA Topologies 441

angle which varies depending on the operation point of the active device. In addition,
as the efficiency is of great importance in the design of a PA, a method must be sought
to enable minimum power dissipation by the active devices. Harmonic termination can
be helpful in some PA classes. In the next sections, the details of the operation classes
of PA will be studied as well as the relations regarding the efficiency of each class.

10.2.1 Class A Power Amplifier

In class A amplifiers, the quiescent point of the active device is chosen in such a way
that the amplifier is always on, regardless of the input signal; hence, the conduction
angle is 360◦ and a good linearity is expected. In this configuration, the maximum
efficiency at the output is 50% and the power capability is 0.125Vdmax .Idmax . It must be
noted that BPFs with high Q are often used in the output to suppress all high-order
harmonics of the output voltage (and current). Figure 10.22 shows a sample of the class
A amplifier. Figure 10.23(a) shows the quiescent point determination curve for the
amplifier of Figure 10.22. As it is clear in Figure 10.23(a), the quiescent point is set at
the middle of the load line to guarantee that the device remains on in all circumstances,
resulting in a 360◦ conduction angle. Figure 10.23(b) shows the drain voltage and
the drain current of the device and its power loss as a function of time. Considering
Figure 10.22, the following equations can be written for the output current and voltage:

iD (t) = IDC − Iac sin (ωt) (10.29)

vD (t) = VDC +Vac sin (ωt) (10.30)

Given the fact that in class A operation, we should have

Iac ≤ IDC (10.31)

Vac ≤ VDC (10.32)

The maximum output power would be

1
Pac,max = VDC IDC (10.33)
2

VG VDD

id Conduction
RFC RFC angle 360º
C∞ Vout
Vd
ZS C∞
Vin IDC
RL
VS ωt
π

2π

3π

4π

Input matching
network

Figure 10.22: Class A power amplifier.

442 Chapter 10. Power Amplifier

id

Id,max
Ideal
transfer IDC
ID function
t
Quiescent vd
point
Vd,max

VDD
Cut-off
region VTH VGS
t
Output PLoss
waveform
PLoss in the device

Input
waveform
t
(a) (b)

Figure 10.23: (a) Quiescent point determination in class A power amplifiers and
(b) Drain voltage, drain current, and device power loss of the circuit depicted
in Figure 10.22.

The definition of efficiency in PA yields,

1
Pac Vac Iac
η= = 2 (10.34)
PDC VDD IDC
Therefore, for the maximum efficiency, we will have
1
2 VDC IDC
ηmax = = 50% (10.35)
VDC IDC
Note that, for the maximum efficiency, one should choose the load resistance as
VDC
RL = (10.36)
IDC
Therefore, reminding that the drain voltage in Figure 10.22 can maximally swing from
zero to twice the voltage source (2VDD ), and the current can swing from zero to twice
the DC operating current, the power capability can be defined as
1
Pac,max VDD × IDC
Power capability = = 2 = 0.125 (10.37)
Vd,max × id,max 2VDD × 2IDC
10.2 PA Topologies 443

10.2.2 Class B Power Amplifier

In class B amplifiers, the quiescent point of the active device is set at the threshold
of the device (or approximately zero bias) turning on so that it provides the output
current only in half the signal cycle and remains off in the other half-cycle. The
conduction angle is consequently 180◦ , and the maximum efficiency at the output
would be π/4 ≈ 78.5%. This class has the privilege of significant improvement in
efficiency besides a fairly appropriate linearity. The power capability is the same as
class A if one device is used, but with a push–pull configuration at the output stage, this
parameter would be increased to 0.25Vdmax .Idmax . Furthermore, class-B PAs necessitate
the usage of BPFs with high Q at the output to suppress all high-order harmonics of
the output voltage (especially the second harmonic voltage). Figure 10.24 depicts a
sample class B power amplifier with zero input bias. Figure 10.25(a) demonstrates the
quiescent point determination curve for the amplifier of Figure 10.24. Figure 10.25(b)
shows the voltage and drain current of the device and its power loss as a function
of time. To derive the efficiency relations for the class B amplifiers, assume that the
DC current flowing from the voltage source is a half-cycle sinusoidal signal. The
average current can be hence obtained by integrating over one period. Consider the
instantaneous drain current as

A sin (ωt) 0 ≤ ωt ≤ π
id (t) = (10.38)
0 π ≤ ωt ≤ 2π
Then, by taking the time average, we obtain
Z T Z T/2
1 1 A
I0 = Iav = id (t) dt = A sin (ωt) dt = (10.39)
T 0 T 0 π
(10.40)
The fundamental component of the output current can be obtained as
Z T
2 A
I1 = id (t) sin (ωt) dt = (10.41)
T 0 2

VDD

id Conduction
RFC angle 180º
C∞ Vout
Vd
ZS
Vin
RL
VS ωt
π

2π

3π

4π

Input matching
network

Figure 10.24: A class B power amplifier with the corresponding output current
waveform.
444 Chapter 10. Power Amplifier

id

ID2
Id,max

t
vd
Quiescent
point VDD

VTH VGS
t

PLoss
PLoss in the device

t
(a) (b)

Figure 10.25: (a) The quiescent operating point and the corresponding wave-
forms for the class B PA and (b) The output current, the output voltage, and the
power loss waveforms for a single-device class B power amplifier.

Finally, noting that the drain voltage in Figure 10.24 can maximally swing from zero to
the supply voltage, the maximum efficiency is obtained by the ratio of the fundamental
(main harmonic) power to the consumed DC power by the source:
1 VDD Imax
Pac,max 2 2 2 π
ηmax = = VDD Imax
= ≈ 78.5% (10.42)
PDC 2 π
4

Note that in this case, for maximum efficiency, the load resistance should be chosen as
VDD
2 VDD
RL = Imax
= (10.43)
2
Imax

In this case, power capability can be calculated as

1 VDD
Pac,max × Imax
Power capability = = 2 2 2
= 0.125 (10.44)
Vd,max × id,max VDD × Imax
10.2 PA Topologies 445

Class B push–pull case

The above derivation was performed for a single-transistor class B amplifier. For
the push–pull case, the same procedure can be used with the NMOS conducting in the
positive half-cycle and the PMOS conducting in the negative half-cycle. Consequently,
the fundamental current will be doubled and the output power will be doubled. Fur-
thermore, the DC power consumption will be doubled and as such the efficiency would
remain the same as single-transistor class B power amplifier. However, the harmonic
distortion will be reduced and the linearity will be improved. Furthermore, the power
capability will be doubled to 0.25Vdmax .Idmax . Figure 10.26 depicts a sample of the
class B PA with push–pull output stage. Note that in this case, for maximum efficiency,
the load resistance should be chosen as

VDD
RL = (10.45)
2Imax

Therefore, the load impedance in the class B push–pull case would be half the load
impedance in a single-ended class B power amplifier (with the same device and the
same bias).

10.2.3 Class AB Power Amplifier

In class AB amplifiers, the quiescent point of the active device is set higher than the
threshold of the device’s turning on voltage and lower than the middle point of the
load line. So, the device provides the output current in more than half a cycle, and
less than a full cycle. The conduction angle is hence between 180◦ and 360◦ , denoting
that the efficiency of this class exceeds that of class A but cannot reach that of class B,

id1
VDD

M1 id2 ωt
ZS Vout
Vin

VS M2
RL
iout ωt

Input matching -VDD

network

ωt
π

2π

3π

4π

Figure 10.26: A class B push–pull power amplifier with the output current
shown as a summation of the positive and the negative half-cycle currents.
446 Chapter 10. Power Amplifier

while its linearity is better than class B and worse than class A. Figure 10.27 shows the
quiescent point determination curve for class AB amplifiers in general.

10.2.4 Class C Power Amplifier

In class C amplifiers, the quiescent point of the active device is set below the threshold
of turning on. Therefore, the device provides the output current in less than half a
cycle, leading to a conduction angle of less than 180◦ . In case the conduction angle
tends to zero, the efficiency tends to 100%, though the output power will also tend
to zero. Indeed, the lower the conduction angle, the more the efficiency and the
less the linearity will be. In general, class C efficiency exceeds that of class A and
class B power amplifiers while its linearity is worse than the other two. Figure 10.28
shows a sample of the class C amplifier, and Figure 10.29 depicts the quiescent point
determination curve for the amplifier of Figure 10.28.
To calculate the power efficiency of the amplifier in Figure 10.28, consider the
instantaneous current in the active device as

Ip sin (ωt) − ID θ1 ≤ ωt ≤ θ2
id (t) = (10.46)
0 otherwise

Thus, the average current (DC current) will be obtained by integrating the current
waveform over one period:

Z T Z
1 1 θ2
I0 = Iav = id (t) dt = Ip sin (ωt) − ID d (ωt) (10.47)
T 0 2π θ1

ID

Quiescent
point
id Conduction
angle >180º

VTH VGS IDC

ωt
π

2π

3π

4π

Figure 10.27: Class AB PA’s quiescent point and the corresponding current
waveform.
10.2 PA Topologies 447

VG<0 VDD

id Conduction
RFC RFC angle <180º
C∞ Vout
Vd
ZS C∞
Vin 2θ
RL
VS ωt

θ1
θ2
π

2π

3π

4π
Input matching
network

Figure 10.28: A class C power amplifier and its corresponding output current
waveform.

id

ID2

t
vout

Quiescent
point

VTH VGS
t

PLoss
PLoss in the device

t
(a) (b)

Figure 10.29: The quiescent point of a class C amplifier and the corresponding
output current, output voltage, and the power loss waveforms.

Now, take the following notations into consideration

Ip sin θ1 = ID (10.48a)
θ2 − θ1 = 2θ (10.48b)
π
θ1 = − θ (10.48c)
2
π
θ2 = + θ (10.48d)
2
448 Chapter 10. Power Amplifier

where 2θ equals the conduction angle (α) of the PA. The total DC power consumption
will be given by
IP
PDC = VDD I0 = VDD (sin (θ ) − θ cos (θ )) (10.49)
π
To obtain the AC power delivered to the load, the fundamental current is calculated as
Z π +θ
1 2 Ip
I1 = Ip sin (ωt) − ID sin (ωt) d (ωt) = (2θ − sin (2θ ))
π π −θ
2
2π
(10.50)

Finally, assuming the peak output AC voltage as VDD , the efficiency of the class C
amplifier is yielded as
1 I
PO VDD p (2θ − sin (2θ )) 2θ − sin (2θ )
ηmax = = 2 I 2π = (10.51)
PDC VDD πP (sin (θ ) − θ cos (θ )) 4 (sin (θ ) − θ cos (θ ))

where 0 < θ < π. It should be noted that for maximum AC power and efficiency, we
should choose the following value for the load impedance.
VDD VDD VDD 2π
RL = = IP
= (10.52)
I1 2π (2θ − sin (2θ )) IP (2θ − sin (2θ ))

It is helpful to note that Equation 10.51 applies for the efficiency of A, B, and AB
classes as well with the corresponding conduction angles.

10.2.5 Comparison Between Class A, Class B, Class AB, and Class C Amplifiers
One of the most important reasons for PA’s classification is the difference in the
efficiency and power capability of the classes. Figure 10.30 presents a comparison
between A, B, C, and AB classes based on their conduction angles. According to
Equation 10.51, the efficiency approaches 100% as θ (half the conduction angle, α)
tends to zero, although no power is transferred to the output, for zero conduction
angle. In the class A amplifier, θ will reach its maximum value (180◦ ), leading to an
efficiency of 50%. To modify and control the conduction angle, the current amplitude
can be kept constant while the bias current or the quiescent point is changed. A similar
method is performed by acting the other way around. In both cases, the conduction
angle can be altered as desired.

10.2.6 Class D Power Amplifier

Other PA topologies such as classes D, E, F, S, etc., have been presented and discussed
in various references, e.g., [2] and [3], which can theoretically provide 100% efficiency.
In these classes, the active device dissipates theoretically zero power. Transistors
act as switches at RF rate in class D amplifiers. Consider Figure 10.31 where the
input differential signal has been applied to two NMOS transistors. This architecture
actually consists of two class B power amplifiers which have been put in a push–
pull configuration. During the positive half-cycle, the upper transistor is turned on,
10.2 PA Topologies 449

Power
η capability

id or ic
Class A
α=2π
ωt 100% 0.134
π 2π 3π 4π
0.125
id or ic
Class AB
π<α<2π 78.5%
ωt
π 2π 3π 4π
id or ic

Class B
α=π
ωt
π 2π 3π 4π 50%
id or ic

Class C C B AB A C B AB A
α<π
ωt α α
π 2π 3π 4π 0 π 2π 0 π 2π
1.36π

Figure 10.30: The output current waveforms alongside the efficiencies and the
power capabilities corresponding to different classes of power amplifiers as a
function of the conduction angle, α.

A
L C Vin+ VDC Vin- VDC
Vd1 2:1 Vout 0 0
+ id1 ωt ωt
Vin+
M1 VDD Vd1 2VDD Vd2 2VDD
- RL
Vin- - 0 0
M2 ωt ωt
i
+ d2
Vd2 id1 id2
ωt ωt
π 2π 3π 4π π 2π 3π 4π

Figure 10.31: A typical class D power amplifier topology and the corresponding
voltage and current waveforms.

providing the positive half-cycle transformer current. In the negative half-cycle, the
lower transistor is turned on and the negative half-cycle current flows through the
transformer. Finally, the currents are superimposed to make up the appropriate full-
cycle output signal. A band-pass RLC circuit with high Q suppresses all the higher-
order voltage harmonics at the output. The maximum possible efficiency in class
D amplifiers is 100% and the maximum power capability equals (1/π)Vdmax .Idmax ≈
0.32Vdmax .Idmax . This configuration has a better performance at frequencies far lower
than the unity gain frequency of the transistors, as the transistors are better switches
in this range. Figure 10.31 depicts the corresponding waveforms of class D amplifier.
One of the drawbacks of class D PA’s is that it is not applicable for linear modulations
such as AM, SSB, or DSB in normal circumstances.
As Figure 10.31 shows, the drain voltage of the transistors can maximally swing
up to twice the voltage source value. Assuming that the transistors act as ideal switches,
the voltage at node A can be considered as a rectangular wave swinging symmetrically
between ±VDD . Writing the Fourier series expansion of the voltage at node A, we have
450 Chapter 10. Power Amplifier

4 n=+∞ sin ((2n + 1) ωt)

vA (t) = ∑ (10.53)
π n=0 2n + 1

The band-pass circuit at the output selects only the main harmonic of vA . Consequently,
assuming that the amplitude of the first harmonic is 4VDD /π at node A, the output
power will be
2
4VDD
VO 2 π 8VDD 2
PO = = = 2 (10.54)
2RL 2RL π RL
In addition, in order to obtain the average current of each transistor in a period,
reminding that the output current is the superposition of the currents of each transistor
at consecutive half-cycles, one can write
T
1 4VDD 4VDD
Z
2
Iave = sin (ωt) dt = 2 (10.55)
T 0 RL π π RL
Ultimately, due to the presence of two active devices, the total power consumption will
be calculated
4VDD 8VDD 2
PDC = 2 ×VDD 2
= 2 (10.56)
π RL π RL
which has exactly the same expression as Equation 10.54. Hence, in the class
D amplifier, the efficiency is ideally 100%. The above relations are based on the
assumption that the switches are ideal while they might have a limited on-resistance
which decreases the efficiency of the PA. If this resistance is not ignored, the output
power of Equation 10.54 will change as follows
2
8VDD 2

RL
PO = 2 (10.57)
π RL ron + RL
The total power consumption in this case will be calculated as

8VDD 2 RL
PDC = × (10.58)
π 2 RL ron + RL
Finally, the maximum efficiency of the PA considering the on-resistance will be
RL
ηmax = (10.59)
ron + RL
The on-resistance might cause the device to have a saturation voltage when turned
on, noted by Vsat . The drain voltage of neither of the devices will thus reach to the
ground level, as they enter the saturation region. Therefore, VDD should be substituted
by VDD −Vsat , and the output power equation will change as

8(VDD −Vsat )2
PO = (10.60)
π 2 RL
10.2 PA Topologies 451

For the total power consumption, we have

4 (VDD −Vsat ) 8 (VDD −Vsat )VDD

PDC = 2 ×VDD = (10.61)
π 2 RL π 2 RL

Finally, the maximum efficiency of the PA considering the transistor saturation voltage
will be
VDD −Vsat
ηmax = (10.62)
VDD

In case where the output switches have both a turn-on resistance and a saturation
voltage, the maximum efficiency of a class D amplifier can be expressed as

VDD −Vsat RL
ηmax = × (10.63)
VDD ron + RL

Class 1/D power amplifier

The class 1/D amplifier can be considered in a dual mode of what has been
described earlier. In a sense that the current is switched through a parallel RLC circuit.
Consequently, the current waveform will be rectangular and the voltage waveform
will be sinusoidal. Therefore, this mode of operation is somehow the dual of the
class D mode described earlier. For this reason, this mode is categorized as class 1/D,
or current mode. Notice the circuit topology and the corresponding waveforms in
Figure 10.32.

10.2.7 Class E Power Amplifier

In this PA class, the active device acts as a switch again. The design goal is to
minimize the device on-resistance, thus there will be no dissipations in the active
device. The device performance in class E power amplifiers is in such a way that no
current flows through the device when a finite voltage is developed across its output.
Furthermore, the voltage across the device is quite small when current flows from it

VDD VDD
Vin+ VDC Vin- VDC
RFC RFC 0 0
ωt ωt
Vd1 Vd2
ωt ωt
id1 id2
Vin+ Vin- id1 id2
M1 M2
ωt ωt
π 2π 3π 4π π 2π 3π 4π

Figure 10.32: A typical circuit topology and current waveforms of a class 1/D
power amplifier.
452 Chapter 10. Power Amplifier

VDD Vin VDC

0
RFC ωt
L C2 Vd
Vd
ωt
Vin C1 RL id
ωt
π 2π 3π 4π

Figure 10.33: A typical class E power amplifier topology and the corresponding
voltage and current waveforms.

to the load. Figure 10.33 shows a class E power amplifier. The device voltage and
current waveforms are also demonstrated. As shown in Figure 10.33, the drain voltage
and its first derivative will be zero when the device is turned on. This configuration
has the ability to provide 100% efficiency while its power capability is approximately
0.098Vdmax .Idmax .
In the design of class E power amplifiers, the transistor parasitic capacitances are
crucial due to the frequency limit they impose on the circuit. In the design of the
matching network, the following relations can be used [9]
QRL
L= (10.64a)
ω
1 1
C1 = ≈ (10.64b)
ωRL ((π 2 /4) + 1)(π/2) 5.447ωRL

5.447 1.42
C2 ≈ C1 1+ (10.64c)
Q Q − 2.08
In addition, the maximum output power will be calculated by

VDD 2
Po,max ≈ 0.577 (10.65)
RL

10.2.8 Class F Power Amplifier

In class F amplifiers, the harmonic behavior of the output is utilized in its best way by
using multiresonance circuits so that the current waveform of the transistor drain gets
close to an ideal rectangular pulse. This can also minimize the drain-source voltage
and the drain current overlap through time, leading to better efficiency. Figure 10.34
shows a class F power amplifier. The device voltage and current waveforms are also
demonstrated.
In Figure 10.34, the L1C1 and L3C3 resonant circuits are adjusted at f0 (the desired
input frequency) and 3 f0 , respectively. Consequently, the drain voltage will contain a
third harmonic component as well as the first.
10.2 PA Topologies 453

VDD Vin 0v
Tuned to 3f0
L3
RFC ωt
C∞ Tuned to f0 Vout
Vd Vd
C3
Vin
ωt
L1 C1 RL
id
ωt
π 2π 3π 4π

Figure 10.34: A typical class F power amplifier topology and the corresponding
voltage and current waveforms.

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Figure 10.35: A typical class F power amplifier topology using a quarter-

wavelength transmission line.

Figure 10.35 is another representation of the class F amplifier in which a trans-

mission line is used instead of the first resonant circuit at the third harmonic. The
transmission line has the capability to present the inverse impedance (turn a low
impedance into a high impedance) when it is a quarter wavelength long (` = λ /4),
hence having a proper input impedance to pass the desired current. It acts equiva-
lently to LC resonant circuits at odd harmonics of the fundamental frequency ( f0 ),
and therefore helps the transistor drain voltage to approach a rectangular wave (for
even harmonics the transmission line acts as a half-wave length one, and therefore,
no impedance inversion occurs, and the even harmonics of the drain voltages are
suppressed). Ultimately, the output band-pass circuit (the resonant circuit at the fun-
damental harmonic, f0 ) suppresses the higher-order harmonics at the output. In
fact, class F amplifiers can be treated as a type of class D amplifier in single-ended
mode. In this class, the maximum efficiency is 100% and power capability equals to
(1/2π)Vdmax .Idmax ≈ 0.16Vdmax .Idmax [12].
454 Chapter 10. Power Amplifier

10.2.9 Class S Power Amplifier

As observed in section 10.2.6, the active devices act as a switch in class D amplifiers.
The closer the device performance to an ideal switch, the better the resulting efficiency.
One of the methods to ameliorate the switching performance of the device is to increase
the applied voltage to the gate (VGS ). It helps reduce the on-resistance of the device,
leading to increased efficiency. Figure 10.36 shows a general schematic of a class S
power amplifier. A signal converter turns the sinusoidal input signal into a pulse width
modulation (PWM) signal. The PWM signal is applied to the active device in a class
D amplifier, improving its switching performance. Finally, the output signal passes
through a high Q band-pass filter which converts the PWM signal into a sinusoid
(higher-order harmonics are suppressed).
Figure 10.37 shows a typical signal converter. A comparator compares the input
signal to a triangular wave signal which renders a PWM output.

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Figure 10.36: Block diagram of a class S power amplifier and its corresponding
waveforms.

Modulating
signal

t +
t
- PWM
t signal
Chopping
signal

Figure 10.37: A typical class sinusoidal to PWM signal converter.

10.3 Linearization Techniques in Power Amplifiers 455

10.2.10 PA’s Performance Comparison

Considering what was mentioned in previous sections regarding power amplifiers’
classification, Table 10.2 provides a comparison between the performances of different
classes of PAs.

10.3 Linearization Techniques in Power Amplifiers

Since linearity is of great importance in PA design, several techniques to mitigate
nonlinear effects are introduced and studied in this chapter. These techniques can be
classified into four groups as follows
• Nonlinearity correction at the input by means of back-off, predistortion,
Cartesian feedback, and polar feedback.
• Nonlinearity correction at the output by means of feedforward and linear ampli-
fication with nonlinear components (LINC).
• Nonlinearity correction at the supply by means of envelope elimination and
restoration, pulsewidth modulation (PW and AM), and pulse deletion modula-
tion (PDM).
• Nonlinearity correction at the load by means of switchable amplifier chain.
These methods have been shown schematically in Figure 10.38.
As mentioned before, AM to AM conversion can pose problems to data modula-
tion using signal amplitude; however, AM to PM conversion plays the basic role in
modulations based on frequency or phase. In general, comparing different linearization
techniques, it can be said that feedback methods impose instability threats or band-
width problems although their closed-loop nature results in robust linearity. Conversely,
feedforward techniques have better stability and a more acceptable bandwidth. In the
next subsections, the course of improving stability using the mentioned techniques are
briefly explained.

10.3.1 Back-Off
Nonlinearity clearly reduces the gain and increases the IM at the maximum output
power. So, the simplest way to linearize the PA operation is to force a back-off from
its maximum power. The required back-off depends on the distortion caused by AM
to AM and AM to PM conversions. This method benefits from low cost and no extra
complexity but requires a device with higher power rating (a bigger device). Back-off

Table 10.2: Performance comparison among different classes of power

amplifiers.
Output Vd,max id,max Power
Class Gain Linearity Power α ηtyp % ηmax % (Normalized) (Normalized) Capability
A Large Best Moderate 360◦ 35 50 2 2 0.125
B Moderate Good Moderate 180◦ 60 78 2 3.14 0.125
C Small Bad Small <180◦ 70 78–100 2 <0.125
AB Moderate Good Moderate >180◦ 35–60 50–78 2 >0.125
D Small Bad Large 180◦ 75 100 2 1.57 0.318
E Small Bad Large 180◦ 80 100 3.6 2.86 0.098
F Small Bad Large 180◦ 75 100 2 3.14 0.159
456 Chapter 10. Power Amplifier

Nonlinearity correction Nonlinearity correction

at the input at the output

RFin RFout RFin RFout

PA ZL PA ZL

Correction Correction

Nonlinearity correction Nonlinearity correction

at the supply at the load
Correction Correction

RFin RFout RFin RFout

PA ZL PA ZL

Figure 10.38: Different linearization methods in power amplifiers.

phenomenon is shown in Figure 10.39. The drawback of back-off is that the power
efficiency drops significantly as the back-off is increased.

10.3.2 Predistortion
We can linearize a nonlinear system, knowing its nonlinear transfer function, by
applying the input signal to a system, with an amplitude proportional to the inverse
characteristics of the nonlinear system amplitude response. Ideally, the gain is expected
to remain constant and the phase would vary linearly with frequency (the group
delay would remain constant), and the total system is supposed to remain linear.

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Figure 10.39: A typical output power versus input power curve in decibels de-
picting the input back-off and the output back-off with respect to the saturation
point.
10.3 Linearization Techniques in Power Amplifiers 457

Predistortion procedure is shown in Figure 10.40. Let F (u) = G−1 (ku), therefore
−1

y = G G (ku) = ku.
A predistorter conveys the input analog values to the corresponding predistorted
values. A look-up table is perfectly suited for open-loop predistortion. It must be noted
that correcting the distortion caused by the fabrication process, temperature variations,
and aging is difficult. Therefore, it is constructive to upgrade this method to adaptive
predistortion (Figure 10.41). In this method, a demodulator reads the output signal,
followed by an A/D which digitizes it. In the next step, the adaptor block updates the
look-up table data by comparing the input and output signals which have been read.
Finally, a digital predistorter applies the required predistortion to the signal using
the look-up table data. The adaptor loop keeps working until the output signal is
fully corrected. It can be stated that the distortion owing to AM to AM or AM to PM
conversions can be compensated via applying an adaptive predistorter. The drawbacks
of this method include the adaptor loop linearity and delay flatness, and the problems
the look-up table preparation and updating may impose.

Predistorter PA

F(u) G(u)
x F(x) y=G(F(x))=Kx

Vout Vout Vout

F(u) G(u) y

Vin Vin Vin

Figure 10.40: A schematic view of predistortion technique .

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Figure 10.41: The block diagram of an adaptive predistorter technique.

458 Chapter 10. Power Amplifier

10.3.3 Polar Modulation Feedback

The modulated signal can be shown as a complex number using both polar representa-
tion (V = rejθ ) and Cartesian representation (V = VI + jVQ ). Figure 10.42 depicts the
polar representation of a complex number.
The polar feedback method utilizes a negative feedback to correct the system
nonlinearity. In this method, the first feedback loop determines the phase (θ ) by
means of a PLL, whereas the second loop senses the amplitude using an envelope
detector, and the correction signal is fed to a variable-gain amplifier (VGA). In brief,
the feedbacks are split between the phase and the amplitude. The overall structure is
shown in Figure 10.43.
This architecture can improve the efficiency at higher output power, but it has not
proven very useful when power levels are low. It is necessary to note that the presence of
two negative feedback loops causes instability problems, imposing particular problems
regarding the gain, the bandwidth, and the phase error. As a rule of thumb, it can be
stated that the loop envelope detector bandwidth should be at least 10 times higher than
the envelope’s maximum frequency. Generally speaking, this linearization method
increases the cost and the complexity of the system. Of course, in case where the
AM to PM conversion effects are neglected, the phase feedback loop can be omitted
resulting in reduced complexity.

θ
I

Figure 10.42: Amplitude and phase representation of a signal in the I–Q plane.

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Figure 10.43: Block diagram of linearization with polar feedback.

10.3 Linearization Techniques in Power Amplifiers 459

10.3.4 Cartesian Modulation Feedback

A similar linearization method is Cartesian modulation feedback which is demonstrated
in Figure 10.44. The PA output drives a quadrature demodulator to sense the degree
of nonlinearity in the baseband data. Then, the restored signal is compared to the
initial baseband information and passed through a low-pass filter in order to drive a
quadrature modulator. Eventually, the signal is transmitted by the antenna after being
amplified. The local oscillator is followed by a phase adjustment circuit so as to deliver
the corrected signal for the quadrature modulator.
In a same way as the previous method, the Cartesian feedback increases the cost
and the complexity of the circuit, and the stability is still a concern. The architecture is
also sensitive to the phase of the local oscillator. Consequently, automatic adjustment
is required to compensate for the process and temperature variations. Efficiency is
boosted at high output powers only. The loop bandwidth of this structure is higher than
that of the polar feedback, making it more effective for higher bandwidth applications.

10.3.5 Feedforward Method

To avoid the instability problem involved in the aforementioned linearization tech-
niques, the feedforward method has been presented. Consider the configuration shown
in Figure 10.45. The PA output is coupled to an attenuator. The coupler and the
attenuator, in sum, introduce a loss equal to the amplifier gain. A delay line in the
feedforward path (delay1) applies a delay equivalent to the sum of the PA delay and the
attenuator delay to the input signal. Subtracting the two output signals of the attenuator
and the delay line gives an error signal generated due to nonlinearity (mainly the IM
products). This error signal is amplified by a supplementary linear amplifier with equal
gain to the main amplifier. A second delay line (delay2) is implemented at the output of
the power amplifier to compensate the delay of the linear amplifier at the feedforward
path. At last, the signals of both paths are subtracted. Ideally, the main path signal
distortion must be eliminated by the error signal amplified in the feedforward path.

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460 Chapter 10. Power Amplifier

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The main advantage of this method is its superior stability compared to the pre-
vious ones. However, it requires a supplementary linear amplifier, adding to design
complexity even though it is dealing with a small-signal amplitude. Furthermore, delay
lines should both provide matching and low loss. Notice that the power amplifier’s
gain and the coupler plus attenuator’s path loss are necessitated to be equal with high
precision. High sensitivity to parameters such as fabrication process, temperature, and
aging can be mentioned as this system’s drawback.
10.3.6 Linear amplification with nonlinear components
Linear amplification with nonlinear components is based on converting the amplitude
information into phase and amplifying constant-envelope signals. This method provides
capability of linear amplification at high output powers and it is shown in Figure 10.46.
Since the efficiency is proportional to the average output power, this configuration
is not efficient for modulations with large peak to average ratio (PAR). To improve
linearity, envelope feedback can be used. In the topology depicted in Figure 10.46,

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10.3 Linearization Techniques in Power Amplifiers 461

consider the input signal as

s(t) = b(t) cos(ωt + φ (t)) (10.66)

Consequently, the separator must generate the following signals

s1 (t) = A cos(ωt + φ (t) + α(t)) (10.67a)

s2 (t) = A cos(ωt + φ (t) − α(t)) (10.67b)

The parameter added to phase in the output can be defined as

α(t) = cos−1 (b(t)/2A) (10.68)

The amplitude information is hence placed within the signal phase at the output signal
of the separator and the signal envelope will take a constant value, leading nonlinearity
to have a less adverse impact on the data. The total output signal would have the
following form

sout (t) = 2AK cos(α(t)) cos(ωt + φ (t)) = Kb(t) cos(ωt + φ (t)) (10.69)

One of the drawbacks of this method is the analog implementation of the input signal
separator which could be demanding.

10.3.7 Envelope Elimination and Restoration

As mentioned in Chapter 5, a limiter circuit eliminates the amplitude variations but
keeps the changes lying in the phase. Consider the architecture shown in Figure 10.47
where two distinct paths to the output are separated by a separator. The first path
utilizes a limiter circuit to extract the phase-modulated information solely. The other
path contains an envelope detector to obtain the amplitude modulated data and transfer
it to the voltage source (power supply) modulation circuit. In other words, the PA has
a modulating voltage source if this technique is used. Altogether, the outputs of these
two paths reconstruct the amplified input signal.
This configuration necessitates an efficient source modulator with low loss for
which switched capacitor DC/DC converters are an appropriate choice. The method
has the capability of providing 100% efficiency at both low and high output powers,
and hence it is proper for power amplifiers whose output power is saturated (classes C,
D, E, and F). Envelope feedback can also help improve linearity in this technique. The
disadvantages of envelope elimination and restoration include AM to PM distortion
due to source variations as well as unequal delay between the two paths that can cause
distortion.

10.3.8 Pulse Amplitude and Width Modulation

Amplitude modulation can be performed by controlling the width of the pulse applied
to the device or the conduction angle. Indeed, the conduction angle determines the
length of the time when the amplifier is on, and it flows current to the load. Consider
Figure 10.48.
462 Chapter 10. Power Amplifier

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tion method.

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As shown in Figure 10.48, the signal with constant envelope and the bias voltage
have been both applied to the transistor gate. The voltage bias value is calculated
through an envelope control circuit. By applying this input signal, square sine-wave-
tips currents are generated in the drain that can reduce the device loss and thus increase
its efficiency. The impedance matching network is placed at the output. In the design of
the bias circuit, it must be noted that the bandwidth must be higher than the envelope’s
maximum frequency. The efficiency of this architecture is higher than class A and
class AB, and lower than class C. Applying the envelope feedback can result in further
improvements in linearity.

10.3.9 Switching Parallel Amplifiers

Consider Figure 10.49 where three power amplifiers are preceding a switch array.
10.4 Conclusion 463

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Figure 10.49: Block diagram of a switchable parallel amplifier array used for
power control.

Each PA has been designed for a certain value of output power. The output of these
PAs is connected to a transmission line with characteristic impedance, Z0,i with λ /4
length which isolates either of them once its switch is short-circuited. The amplifier
array is connected to the load by means of a 3-bit switch control. The weighted
combination of the amplifiers’ powers appears at the load depending on the switch
states [11]. As such, there would be seven (23 − 1) levels of controllable power which
can be interpreted as a linearity improvement as a function of the input. Furthermore,
the efficiency would be ameliorated as well. Switches must have low loss to guarantee
desirable performance. This architecture has a moderate design complexity.

10.4 Conclusion
In this chapter, we discussed the general requirements and characteristics of the power
amplifiers. Normally, the power amplifier is a block which generates harmonics as
well as IM products due to its nonlinear operation. Furthermore, its gain is normally
saturated by increasing the input amplitude. AM to AM conversion and AM to PM
conversion are among the most important nonlinear characteristics of a power amplifier.
Power amplifiers have different topologies and modes of operation. Class A, class B,
class AB, class C, class D, class E, class F, and class S power amplifiers were introduced
in this chapter along with their corresponding efficiencies and power capabilities.
Linearization techniques in power amplifiers are of great importance in the mod-
ern RF circuitry. Different linearization techniques were introduced in this chapter
including predistortion, polar modulation feedback, Cartesian modulation feedback,
464 Chapter 10. Power Amplifier

feedforward, linear amplification with nonlinear components, envelope elimination and

restoration, and switching parallel amplifiers. Each method has its own possibilities
and complexities.

10.5 References and Further Reading

1. B. Razavi, RF Microelectronics, second edition, Castleton, NY: Prentice-Hall,
2011.
2. S. Cripps, RF Power Amplifiers for Wireless Communications, Nowrood, MA:
Artech House, 1999.
3. A. Grebebbikov, RF and Microwave Power Amplifiers Design, Boston, MA:
McGraw-Hill, 2005.
4. J. Everard, Fundamentals of RF Circuit Design with Low Noise Oscillators,
United Kingdom: J. Wiley & Sons, Inc., 2000.
5. U.L. Rohde, A.M. Pavio, G.D. Vendelin, Microwave Circuit Design Using
Linear and Nonlinear Techniques, Hoboken, NJ: J. Wiley & Sons, Inc., 2005.
6. J.R. Smith, Modern Communication Circuits, second edition, New York, NY:
McGraw Hill, 1997.
7. K.K. Clarke, D.T. Hess, Communication Circuits, Analysis and Design, United
States: Krieger Publishing Company, 1994.
8. R. Chi-Hsi Li, RF Circuit Design, Hoboken, NJ: J. Wiley & Sons, Inc., 2009.
9. N. O. Sokal, A. D. Sokal, “Class E-A New Single-Ended Class of High-
Efficiency Tuned Switching Power Amplifiers,” IEEE J. Solid-State Circuits,
Vol. 10, pp. 168–176, 1975.
10. J.Y. Hasani, M. Kamarei, “Analysis and Optimum Design of a Class E RF Power
Amplifier,” IEEE Transactions on Circuits and Systems I: Regular Papers, Vol.
55, Issue 6, pp. 1759–1768, July 2008.
11. A. Shirvani, D. K. Su, and B. A.Wooley, “A CMOS RF power amplifier with
parallel amplification for efficient power control,” IEEE J. Solid-State Circuits,
vol. 37, no. 7, pp. 684–693, June 2002.
12. Hae-Seung Lee and Michael H. Perrott, course materials for 6.776 High Speed
Communication Circuits, Spring 2005. MIT OpenCourseWare (http://ocw.mit.edu/),
Massachusetts Institute of Technology.
10.6 Problems 465

10.6 Problems
Problem 10.1 In a handheld transceiver as shown in Figure 10.50, the power am-
plifier has a maximum RF output power of 20 dBm, the transmitter bandpass filter
has a 2 dB insertion loss, and the duplexer’s isolation is about 30 dB. If the receiver
has a bandpass filter with 1 dB insertion loss and 90 dB out-of-band rejection at fTX ,
determine the minimum possible sensitivity of the receiver for a required C/I of 8 dB.

1dB
Duplexer LNA

PA
2dB 20dBm

Figure 10.50: Block diagram of the handheld transceiver RF front-end.

Problem 10.2 An active device has a nonlinear transconductance which can be

described by the following equation

i = αv + β v2 + δ v5 (10.70)

For an input with the following form, determine the third-order IM products, further-
more, show that if the modulating signals a (t) and b (t) are band limited to W , the
bandwidth of the third-order IM product components would be 5 W:

v1 = a (t)V1 cos (ω1t) (10.71)

v2 = b (t)V2 cos (ω2t) (10.72)

Problem 10.3 In a MOS transistor, the nonlinear gate–source capacitance is modeled

as the following
C0
Cgs Vgs = q (10.73)
V
1 + Vgs0

First, determine the nonlinear q − V characteristics of the junction capacitance, by

integrating the above equation with respect to Vgs . Then, develop the Taylor’s series
expansion of this characteristics up to Vgs3 term. Now, considering a large-signal input
voltage of the form Vgs = V1 cos (ωt), determine the large-signal input capacitance of
the gate–source junction. For the given values of the transistor’s equivalent circuit
model, compute the AM-PM characteristics (φout versus VS ) for the given stage at
5 GHz. For this purpose, assume that the value of VS varies between 200 mV and 2 V.
466 Chapter 10. Power Amplifier

RS Vout
+
vS Vgs Cgs(V) gmVgs rds Cds RL
-

RS=50Ω rds=500Ω
C0=200fF Cds=90fF
V0=1V RL=500Ω
gm=4mS

Figure 10.51: The equivalent circuit of the MOS stage with a nonlinear gate–
source capacitance.

Problem 10.4 A power MOSFET has the following square-law transfer characteris-
tics IDS = k (VGS −VTH )2 , with a threshold voltage of 0.2V , and k = 50 mA
V2
. We intend
to design a class A power amplifier with VDD = 1V and RL = 100 Ω. First, determine
the required bias point of the transistor, and the maximum drain current and the maxi-
mum drain voltage. Secondly, determine the gain of the stage, and the required input
voltage swing to achieve the maximum output power. What would be the maximum
output power in this case?

Problem 10.5 Consider the transfer characteristics of a power MOSFET as

IDS = k (vGS −VTH )2 vGS > VTH (10.74)

IDS = 0 vGS ≤ VTH (10.75)

Now, consider the input gate–source voltage as

vGS = VGS0 +V1 cos (ω0t) (10.76)

where VGS0 ≤ VTH . Determine the output current conduction angle as a function of
V1 and VGS0 , and the output current waveform in this case. Now, compute the DC
component and the first harmonic component of the output current, and consequently,
compute the AC and the DC powers and the efficiency of this amplifier for class B and
class C operation.
10.6 Problems 467

VG<VTH VDD

RFC LD
CD Vout
RS C∞
Vin
RL
VS

Input matching
network

Figure 10.52: A MOSFET class B or class C power amplifier with bias and
matching circuits.
Index

π/4 QPSK, 6 AM radio, 3

90◦ phase shift AM to AM conversion, 426, 438, 455
FM detector, 134–135 AM to PM conversion, 426, 432, 438,
Transmission line, 150 455, 458
16-QAM modulation, 236–237 Amplifier
16-QAM signal constellation, 237 bilateral conjugate matching,
1dB compression point 385–386
overview, 174, 177–179, 195, design, 377, 391, 399–403
196 single-stage, 406–409
power amplifier, 427, 431–438 two-stage, 409–410
64-QAM modulation, 235, 237, 240 performance, 380
64-QAM signal constellation, 235, maximum available power
238 gain, 384–386
stability, 380–384
AC coupling, 320–322 power gain contours, 391–398
ACPR bilateral conditionally stable,
power amplifiers, 425–426, 398
438–439 bilateral unconditionally stable,
standard specification, 180 391–392
Adjacent channel interference sepecifications, 377
ACPR, 180, 425 available power gain, 379
DAMPS, 6, 11–14 operational power gain, 379
third-order intermodulation, transducer power gain,
172–177 378–379
ADS simulation, 154, 217, 339 unilateral conjugate matching,
AGC in receivers, 18, 258, 265 385
AM demodulation, 224–226, 233–234 Amplifier nonlinear behavior, 49

469
470 INDEX

Amplitude Balun, 239

oscillators, 30–33, 76, 91 Band-pass filter
power amplifiers, 450, 458 harmonic selection, 55–56,
Amplitude detector, 268–270 58–61, 65
logarithmic signal level indicator, mixer, 179, 190, 226, 228
269–270 Q, 47, 49
Amplitude mismatch, 240–243 transceiver, 4–5, 10–16
Amplitude modulation (AM) transmitter, 427, 428
AM radio, 3 Bandwidth
detection, 231–234 amplifier, 266, 377
distortion, 431–434 efficiency, 223, 229, 240–244
DSBSC, 229–230 harmonic selection, 56
implementation, 226–228 matching network, 307, 322
overview, 223–224 multistage amplifier, 259–261,
PA linearization, 455–456, 273–277
460–462 noise, 399
quadrature amplitude modulation PLL, 150, 159
(QAM), 235–237 power amplifier, 455–459
zero-IF receivers, 244–248 Bandwidth improvement methods
Amplitude nonlinearity, 431 fT doubler, 274
An Introduction to Oscillators, 27 decreasing input capacitance,
Analog modulation, 6 276–277
Antenna high speed transistors, 273
based station, 8 inductive load, 274–276
impedance matching, 284, 313, Barkhausen’s criteria, 30, 75
425 Base-emitter junction
in receiver, 10, 18 fT doubler, 274
in transmitter, 19, 425 mixer, 203
Attenuation oscillator, 37
channel, 13, 14 Baseband
image, 12, 18 demodulation, 130, 224–225
Automatic gain control (AGC) mixer, 226–228
amplifiers, 258 modulation, 129–130, 223–224
bandwidth improvement noise, 31
methods, 273–277 Basic concepts
feedback changing, 266–267 demodulation, 130
gain control methods, 265–267 modulation, 127
load resistor changing, 266 noise figure, 400
multipliers, 270 scattering parameter, 351
overview, 265–267 third-order intermodulation, 174
switching between amplifiers, Bias in varactor, 91–93
267 Bilateral amplifier, 385–386
transconductance changing, conditionally stable, 398
265–266 unconditionally stable, 391–392
Auxiliary amplifier in PA, 459–460 Binary phase shift keying (BPSK), 235
Available power gain, 379, 384–385, generation, 238–239
398 Bipolar transistor linearity, 203–205
INDEX 471

Blocker, 12, 177 real capacitor loss resistance, 55

Blocking real capacitor model, 47–49
channel blocking, 176 real inductor model, 47–49
DC blocking, 314, 328 shunt peaking, 275
Bond wire, 440 synthesis of capacitor by T-line,
Breakdown voltage of diode, 92 305
Buffer varactor
AGC, 263 frequency modulation, 127
oscillator, 67 junction capacitor, 432
Butler oscillators, 103 VCO, 91–93, 156–158
voltage divider, 37
Cadence IC design simulation, 217 Capacitive coupling, impedance
Calbration circuits, 359 transformer, 67
Calibration in network analyzer, Capacitive division, 75
357–360 Capacitive impedance transformer,
Calibration process for network 67–69
analyser, 359–360 Capacitive step-up transformer, 69–71
Capacitance and capacitor Carrier extraction, 233
fT doubler, 274–277 Carrier frequency, 129, 229–230, 232
AM demodulation, 224 Carrier injection, 276
AM to PM distortion, 432–434 Carrier radian frequency, 129–130
amplitude detector, 268–269 Carrier to intermodulation ratio, 431
as lossy element, 48 Cartesian feedback, 459
capacitive matching circuit, 194 Cascaded stages, 209
capacitive step-up transformer, CDMA, 429, 438
38, 63, 65–72, 74–76 Cellular system, 3, 427
charge pump in PLL, 161–164 Center tapped capacitive transformers,
crystal model, 42–44 67–72
decreasing input capacitance by Center tapped inductive transformers,
series feedback, 276–277 66–72
low-pass filter in PLL, 160 Channel blocking with
lumped model of T-line, 286 intermodulation
matching network components, 176–177
T matching network, 320 Channel length modulation, 273
π matching network, 316–317 Channel selection filter, 14–18
L-section approach, 306–312 Channels
mechanically variable capacitor, attenuation, 12–14, 18
91 DAMPS, 13
Miller capacitance in feedback, interferers, 178, 193
264 transceiver, 3–7
offset cancellation loop, 262–264 Characteristic impedance
parasitic effect open-circuit, 300
amplifier, 274 short-circuit, 299–300
class E power amplifier, 452 termination, 298
oscillation in amplifier, transmission line, 285–288,
283–284 291–293
oscillator, 46–47 Charge pump, 161–163
472 INDEX

Class A power amplifiers, 441–442 Conversion of Network matrices,

Class AB power amplifiers, 445–446 369–370
Class B power amplifiers, 443–445 Cost of fabrication, 16, 66
Class C power amplifiers, 446–448 Coupling
Class D power amplifiers, 448–451 bond wire, 440
Class E power amplifiers, 451–452 capacitance, 67
Class F power amplifiers, 452 Cross-coupled oscillator, 92, 156
Class S power amplifiers, 454 Crystal oscillator, 41–46, 77–78, 241
Closed-loop gain Current source
oscillator, 36, 38, 90, 91 amplitude detector, 268–270
PLL, 157 automatic gain control, 265–266,
Cluster of seven cell frequency 270
distribution, 7 charge-pump in PLL, 161
Coherent transceiver, 32, 241 limiting circuits, 257–258
Colored noise, 29 nonlinear mixer, 170–171
Colpitts oscillator, 38–41, 74–75
emitter degeneration, 82 DAMPS, 5
Combination of amplifier and mixer, Data rate, 235
210–212 Datasheet
Common-base oscillator, 37 crystal oscillators, 45–46
Common-collector oscillator, 37–38 VCO, 108
Common-emitter amplifier, 50, 82 dB, 8
Common-emitter oscillator, 36 dBm, 8
Common-mode noise, 257, 267 DC coupling, 320, 322
Common-mode stability, 264 DC offset
Common-source amplifier, 274 offset cancellation loop, 262
Compression Decibels (dB), 8
gain, 173–174, 178–179, 195, Degeneration resistor, 203–205
196 Delay
mixer, 174 EER technique in PA, 461
PA, 427–438 feedforward technique in PA,
Conduction angle, 440, 441, 443, 446, 459–460
461 in TDMA, 6
Consideration in radio frequency predistortion technique in PA,
design, 10 456–457
Constant noise figure contours, 403 quadrature modulation, 243
Constant-envelope signal, 460, 461 S-parameters measurement,
Constellation 357–358
effect of phase and amplitude transmission line, 284–286
mismatch, 240–243 Demodulation, 18, 130–141
signal, 235–237, 239, 241, 242 Design
Conversion amplifier, 377–379, 391,
AM to AM, 426, 438, 455 399–403
AM to PM, 426, 432, 438, 455, LC tank, 44
458 matching network, 306–311
Conversion gain mixer, 203
mixer, 185–187, 203, 205, 206 modulator, 240
INDEX 473

oscillator, 30 power amplifier, 426, 455, 457

PA, 425–440 third-order intermodulation, 178
phase detector, 134 transmisson line, 284–285
PLL VCO, 93
type I, 156–161 Distortion cancellation, 457
type II, 161–164 Divider
RF system, 10–16, 177–180 frequency synthesizer, 17–19,
single-stage amplifier, 406–409 159
SSBSC, 229–230 voltage divider, 27–30
two-stage amplifier, 409–410 Double-balanced mixer, 184, 186–192,
wireless system, 3 208–209
Detection Double-sideband suppressed carrier
AM signal, 231–233 (DSBSC), 229–230
digital modulation, 244 Downconversion and downconversion
FM signal, 244 mixer
peak detector, 269 DAMPS transceiver, 18
QPSK, 242 demodulator, 231–233
receiver, 12, 178, 179 heterodyne receiver, 11, 14
Differential fT doubler, 274 receiver, 4, 169
Differential amplifier, 257, 265 third-order intermodulation,
for oscillator, 90–91 175–176
Differential demodulator, 232–233 unbalanced mixer, 188–189
Differential mixer, 190, 207 zero-IF receiver, 5
Differential modulator, 226–228 Downlink, 6
Differential pair, 209 Drain current in power amplifier,
Differential passive mixer, 186 443–446
Differential power amplifier, class D, Dual-gate MOS transistor in VGA,
449 266
Differential transmission line, 286 Duplexer, 429
Digital demodulation, 18 Dynamic range, 9, 265
Digital modulation, 3–6
16-QAM, 236–237 Effective radiated power (ERP), 428
64-QAM, 235, 237, 240 Efficiency
GMSK, 235, 243–244 modulation, 230
M-QAM, 161, 235 power amplifier, 426–427
QAM, 235 class A, 441–442
signal constellation, 235–237, class B, 443–445
239, 241, 242 class C, 446–448
Digitally-controlled oscillator, 5 class D, 448–451
Diode junction, 92 class E, 451–452
Diode on-resistance, 170, 268 class F, 452
Direct digital synthesis (DDS), 161 Electrical delay
Direct-conversion receiver, 241 calibration, 358
Direct-conversion transmitter, 240 Electromagnetic wave propagation
Distortion model, 349
amplifier, 257, 399 Envelope
PLL, 138, 161 AM demodulator, 224
474 INDEX

AM modulator, 223 channel selection, 18

power amplifier linearization, front-end band-pass, 4, 16
455 front-end low-pass, 5
Envelope detection Gaussian, 243–244
envelope elimination and harmonic selection, 55–56, 59
restoration (EER), 461 integer-N frequency synthesizer,
polar modulation, 458 18, 160
Envelope elimination and restoration mixer, 185
(EER), 455, 461 modulation, 158
Equivalent isotropically radiated notch filter in NPR measurement,
power (EIRP), 428 439
Error effect in QPSK modulation, 241 offset cancellation loop, 262, 264
Error vector magnitude (EVM), 426, PA, 435, 454
439 PA linearization technique, 459
Excessive interference, 4 PLL, 141–145, 150–151
Exclusive-OR in phase detector S-parameter calculation, 354
(XOR), 130 Sallen-Key filter, 138
External excitation, 33 transmission line, 298
FM radio, 3
fT doubler, 274 Fourier series
Fading, 9 LO waveform, 185–187
Fast Fourier Transform (FFT), 438 mixer, 184–185
Feedback power amplifier, 449
amplifier, 399 Fourier series coefficients, 185, 228
automatic gain control, 265–267 Fourier transform of LO waveform, 32
decreasing device capacitance, Free-running frequency of VCO,
276–277 141–144, 151–152
integer-N frequency synthesizer, Frequency
17 fT doubler, 274
offset cancellation, 259–264 bandwidth, see Bandwidth
oscillator, 27–32, 36–41 demodulation, 130–138
PA instability, 440 increasing bandwidth methods,
PA linearization techniques 273–276
Cartesian modulation, 459 integer-N synthesizer, 17–19,
polar modulation, 458 158–161
predistortion, 456–457 mixer, see Mixer
PLL, 141–145, 156, 163 modulation, 127–129
Feedforward multi-stage amplifier, 259–261
power amplifier linearization, oscillator, 46–47
455, 459–460 Frequency demodulation, 130
Feedthrough in mixer, 185 Frequency demodulator by quadrature
Figure of merit of oscillator, 27 phase detector, 139
Filter Frequency detector in PLL, 160
AM demodulation, 224, 233 Frequency deviation, 136–137,
band-pass in transmitter, 428 158–159
band-pass transfer function, Frequency hopping, 177
47–49 Frequency locked loop (FLL), 143
INDEX 475

Frequency modulation (FM), 127–129, Gaussian minimum shift keying

135 (GMSK), 235, 243–244
Frequency multiplication, 11 Gilbert cell
Frequency response AM demodulator, 232
amplifier, 54, 56, 275 applications, 234–235
digital modulator, 240 automatic gain control, 270–272
Gaussian filter, 244 mixer, 178, 192
LC tank, 47 phase detector, 130–134, 151
matching network, 307, 320, 322 Global system for mobile (GSM), 4–8
multi-stage amplifier, 259
oscillator, 33 Harmonic
PLL, 145 AM modulator, 226–228
Frequency selective, 29, 307 Large-Signal Transconductance,
Frequency stability, as a merit of 53–59
oscillator, 111 mixer, 170–174
Frequency synthesizers, 17–19, oscillator, 81
158–161 PA nonlinearity, 425, 434–435
Frequency-dependent impedance, 313 class A, 441
Friis’ NF equation, 409 class B, 443–445
Friis’ relation, 403 class D, 449
Front-end band-pass filter, 12, 16 class F, 452–453
Full-duplex system, 429–430 class S, 454
transceiver, 169
Gain Harmonic based amplifiers, 53
AGC, 265, 267 Harmonic tuned amplifier, 53–63
amplifier, 377–378 Hartley oscillator, 38–41
availabe power gain, 379 Heterodyne receivers, 11–12
operational power gain, 379 High efficiency power amplifier, 461
transducer power gain, High-pass filter, 127
378–379 High-pass/AC coupled L-section, 319,
conversion gain in mixer, 322
185–192 High-performance transceivers, 161,
gain control based on multipliers, 169
270–272 High-speed transceivers, 161
limiter, 257–258 Higher harmonics in oscillation, 58
LNA, 210 higher order harmonics, 57
oscillator, 27–32 higher order resonance frequencies, 44
PA, 430–431
PLL, 143–145 I-V characteristic
receiver chain, 10–12 amplifying, 172, 194
S-parameters definition, 351–352 bipolar, 50
transmission line, 285 hypothetical element, 89
Gain compression, 173–174, 178–179, mixing, 174, 187–190
427 MOS, 83, 95
Gain mismatch, 242 oscillation, 90
Gaussian distribution, 262 I/Q demodulation, 240, 244
Gaussian filter, 243–244 I/Q modulation, 241
476 INDEX

I/Q receiver, 24 matching network quality factor,

IF (Intermediate frequency), 5, 14–16 308
zero-IF, 19 on-chip inductor, 48, 275
Image signal, 12, 16, 18–20 parasitic effect
Impedance oscillation in amplifier,
AGC, 274 283–284
amplifier, 377–386, 403 quality factor
design, 406–414 discrete inductor, 65
antenna, 425 on-chip inductor, 65
crystal, 42–43, 78 real inductor loss resistance, 55
matching network, 283–286, real inductor model, 47–49
306–322 self-resonance, 275
mixer, 187, 194 shunt peaking, 274–276
noise, 399 spiral inductor model, 275
offset cancellation loop, 261–264 synthesis of inductor by T-line,
oscillator, 46, 55–60 305
PLL, 134–138 Inductive impedance transformer,
power amplifier, 427–429, 448, 66–67
453 Inductive step-up transformer, 71–72
reference, 8 Injection
carrier, 276
S-parameters, 351–352
signal, 235
transformers, 65–74
Input capacitance
transmission line, 284–286,
fT doubler, 274–277
291–293
offset cancellation loop, 262–264
Impedance transformation
Input impedance
capacitive, 67–69
amplitude detector, 269
inductive, 65–67
class F power amplifier, 453
tranmission line, 285, 286–305 detector, 135
In-band interferes, 7 mixer, 194
In-band loss, 11 offset cancellation loop, 261–264
Incident current, 288 transformers, 65–72
Incident voltage, 288 transmission line, 295–296,
Incident wave, 294, 301–302, 351–352 301–303
Inductance and inductor Input matching
active inductor, 275 amplifier, 377–379, 384–386
crystal model, 42–44 Gilbert cell, 217
implementation with stubs, 306 mixer, 193–194
inductive step-up transformer, offset cancellation loop, 261–264
65–72 Smith chart, 322–327
inductive transformer, 61 transmission line, 283–286,
lumped model of T-line, 286 306–312, 320
matching network two-port network, 353
T matching network, 320 Input noise
π matching network, 316–317 oscillator, 27–30
L-section approach, 306–312 two-port, 399–403
mixer, 194 variable gain amplifier, 266
INDEX 477

Input reflection coefficient, 293–296 single-ended bipolar amplifier,

Input resistance, 277 182–183
Input third intercept point (IIP3), Large-signal tree in Gilbert cell,
173–174, 177–179, 234–235
194–202, 432 LC matching network (L-section),
Integer-N frequency synthesizer, 17 306–311
Integrator in PLL, 144, 163 LC oscillator, 34–41
Interference in transceiver, 4–5, 8–9 LC tank, 44, 47, 452
Interferer Leakage
AM modulator, 228 mixer, 169, 185–192
mixer, 180, 190 multistage amplifier, 277–278
transceiver, 10–11, 177 power amplifier, 430
Intermediate frequency (IF), 5, 158 limiting circuits, 257–258
Intermodulation, 171–180, 194–202 Limiting stages oscillation, 277–278
Inverse Laplace transform, 160 Linear amplification, 426
IP3 (third intercept point), 172–180, Linear amplification with nonlinear
432 components, 460–461
IS-95 CDMA, 438 Linear system, 27, 177
Isolation Linearity
duplexer, 429–431 passive mixers, 186
transformer, 61 two-tone test, 195
two-port, 359 Linearity and linearization
amplifier, 267, 277
Johnson noise, 399 mixer, 203–205
Junction capacitor, 432 nonlinearity, see Nonlinearity
PA, 425–426, 431–439, 455–463
L-Section approach, 306–316 back-off, 455–457
Laplace domain, 144 Cartesian modulation
Laplace transform, 144 feedback, 459
Large-signal behavior in power class A, 441
amplifier, 425 class AB, 446
Large-signal bipolar transistor, 54 class B, 443
Large-signal current in oscillators, 102 class C, 446
Large-signal loop of oscillators, 74–77 class D, 449
Large-signal MOS transistor, 83 class F, 452
Large-signal resistance, 104 class S, 454
Large-signal transconductance, 53–63 comparison among different
bipolar differential pair amplifier, classes, 455
63–65 envelope elimination and
bipolar single-ended amplifier, restoration, 461
53–63 feedforward, 459–460
emitter degeneration effect, 82 LINC, 460–461
loop gain analysis, 74–77, 82 polar modulation feedback,
MOS differential pair amplifier, 458
86–89 predistortion, 456–457
MOS single-ended amplifier, pulse amplitude and width
83–85 modulation, 461–462
478 INDEX

switching amplifiers chain, in combination with mixer,

462–463 210–212
Local oscillator (LO), 5 in receiver, 18, 283–284
AM detection, 233–234 trade-off in design, 405
Gilbert cell applications, 234, Low-pass behavior in PLL, 145
235 Low-pass filter
mixer, 170–171 in receiver chain, 5, 19, 138
double-balanced mixer, 186 in transmitter chain, 459
leakage issue, 185 mixer, 185, 192
single-balanced mixer, 185 modulator, 127, 233, 243
usual mixer, 185 offset cancellation loop, 262–265
phase noise, 30–32 PLL, 141, 143, 144, 150–156
Logarithmic signal level indicator, S-parameter calculation, 354
269–270 Low-pass frequency, 263–264
Loop Low-pass version of π matching
integer-N synthesizer, 17–19 network, 319
oscillator, 27–32, 74–76 Low-pass/DC coupled L-section, 319,
oscillator gain, 36, 38, 77–78, 322
89–91 Lumped matching network, 338
phase locked, see phase-locked Lumped model of a transmission line,
loop (PLL) 286–287, 289
Loss
M-QAM modulation, 161, 235
attenuator in feedforward
Main tone in crystal resonance, 44
technique, 459–460
Matching network
dielectric, 48
amplifier, 377–379, 384–386,
energy storage element, 307 406
filter in-band loss, 11, 16, 67 Gilbert cell, 217
filter out-of-band loss, 10, 277 harmonic selection, 61
matching network, 425, 430 loss, 425, 430
resonator resistance, 33, 66, 428 mixer, 194
Loss resistance, 55 offset cancellation loop, 261–264
Lossless inductor, 48 power amplifier, 425, 431
Lossless transmission line, 285, S-parameter, 352, 353
291–293, 296 Smith chart, 322–327
mismatch, 301–303 transmission line, 283–286, 295,
Lossy component, 15, 48 305–322
Lossy transmission line, 289–291 Matching resistor in offset
Low phase noise, as a merit of cancellation loop, 262
oscillator, 111 Matrix representation of two-port
Low-frequency application, 65 network, 349–350
Low-frequency building blocks, 262 Maximum output power in amplifier,
Low-frequency component in noisy 392
signal, 152 Mechanically variable capacitor, 91
Low-frequency parameters, 351 Microstrip transmission line, 66
Low-noise amplifier (LNA) Microwave circuits, 3, 283, 349
gain, 12 Microwave link, 10
INDEX 479

Microwave theory, 283, 286 single-balanced, see

Microwave transistor-based amplifier, Single-balanced mixer
377–379, 399–400 third-order intermodulation, see
Miller capacitance in feedback, 264 Third order intermodulation
Miller effect, 276 unbalanced, see Unbalanced
Mismatch mixer
amplitude mismatch, 240–243 upconversion, see Upconversion
direct-conversion transmitter, 241 and upconversion mixer
effect on signal constellation, zero-IF receiver, 5, 19
240–243 Mobile networks, 6–8
gain mismatch in constellation, Mobile unit, 429
242 Modeling of coupling circuits, 67
lossless transmission line, Modified Bessel functions, 52–53
301–303 Modulation
mixer, 186 AM, see Amplitude modulation
phase mismatch, 240–243 (AM)
power amplifier linearization, analog, 6
461 bandwidth efficiency
two-port network, 351 improvement, 243–244
VSWR, 306, 440 channel length, 273
Mismatch loss, 310 digital, see Digital modulation
Mixer frequency modulation (FM), 19,
active bipolar mixers, 180–183 127–129, 135
analysis by Fourier series with PLL, 156–161
expansion, 184–192 modern practical modulation,
basic concept, 169–171 235–240
classification, 184 PA linearization
conversion gain, see Conversion Cartesian modulation
gain feedback, 459
double-balanced, see polar modulation feedback,
Double-balanced mixer 458
downconversion, see pulse amplitude and width
Downconversion and modulation, 461–462
downconversion mixer phase, 31, 426, 431, 432
feedthrough, 185 pulse width modulation (PWM),
in combination with LNA, 454, 455
210–212 MOS design, 277
linearization methods, 203–209 MOS switch, 186, 187
matching, 194 MOS transistor, 61, 83, 133
nonlinear model, 170–171 as resistor in triode region, 267
nonlinearity analysis by Bessel dual-gate, 266
function, 180–183 linearity, 203–205
oscillator, see Local oscillator maximum frequency, 273
overview, 169 offset voltage problem, 261
passive switching mixer, MOS varactor, 156–157
186–187 Multipath fading, 9
single diode mixer, 169–170 multipath media, 9
480 INDEX

Multiple reflections of waves, 8 oscillator, 27–30

Multiple stages phase noise, see phase noise
IP3, 209 random movement of electrons,
noise figure, 403 399
Multiple tones in input, 426 random noise signal, 31, 32, 173
receive band noise, 429–430
Narrowband application, 54, 61, 305 sensitivity, 9–10, 173, 241, 266
Narrowband filter, 11 signal-to-noise ratio (SNR), 173,
Natural frequency of oscillation, 158 241, 266, 306, 401
Natural frequency of PLL, 145, 147, substrate, 93
160 supply voltage, 93
Natural resonances of crystal, 41 thermal noise, 28, 32, 399
Negative active-feedback two-port network, 399–403
offset cancellation loop, 262–263 white noise, 29, 399
Negative feedback Noise floor, 178
amplifier, 399 Noise performance of amplifier, 12,
frequency synthesizer, 17, 158 402
offset cancellation loop, 261 Noise sidebands, 29
polar modulation technique, 458 Nonlinear behavior in amplifiers,
Negative resistance 49–52
amplifier, 380 Nonlinear systems, 171, 177–178
oscillator, 27, 32–34 Nonlinearity
NMOS transistor 1dB compression point, 174,
class D power amplifier, 449 177–179
mobility, 273 AGC, 258
Noise distortion, 257
bandwidth, 399 effect of quality factor, 138
colored noise, 29 effect on demodulation process,
common-mode noise, 267 225
common-mode noise rejection, intermodulation, 173–180,
257 194–202
contours in Smith chart, 398, cascaded stages, 209
403–406 mixer, 12, 170–171
effect of gain, 265 mixing product, 171–172, 190
Friis’ relation, 403 oscilator, 27
intrinsic noise of amplifier, 399 oscillator, 49–52
Johnson noise, 399 oscillator’s loop gain, 29–30,
LNA, see Low-noise amplifier 36–37
(LNA) power amplifier, 425–426
minimum noise figure, 403 AM to AM distortion, 432
noise figure (NF), 400–403 AM to PM distortion, 432–434
noise floor, 178 error vector magnitude (EVM),
noise model of two-port 439
amplifier, 399 spectral regrowth, 435–439
noise power ratio (NPR), 439 undesired harmonic
noisy signal as input, 152 components, 434–435
offset cancellation loop, 278 varactor, 157
INDEX 481

Number of turns overview, 27

transformer, 61 phase noise, 30–32, 158
topologies, 34–41
Odd symmetry, 209 Colpitts, 38–41
Offset cancellation feedback, 259 Colpitts with emitter
Offset cancellation loop, 261–264 degeneration, 82–83
cut-off frequency, 263–264 common-base, 37
Offset compensation circuit, 261–264 common-collector, 37–38
Offset frequency common-emitter, 36
ACPR, 438 differential, 90–91
filter attenuation, 13 Hartley, 38–41
Offset QPSK (OQPSK), 243 VCO, see voltage-controlled
Offset voltage oscillator
limiter, 261–264 Out-of-band attenuation in filter, 10,
mixer output, 186 277
On-chip inductor, 48, 65, 275 Out-of-band blockers, 12
Open loop gain Output admittance
PLL, 144 capacitive transformer, 70
Open-loop inductive transformer, 72
multistage amplifier, 259 Output capacitance
PLL Type-I, 151 oscillator, 51
PLL Type-II, 163 shunt peaking, 275
Operational power gain, 379–380, Output impedance
391–398 amplifier, 377
Orthogonal direction in QPSK, 236 stability issue, 380
Oscillation in limiting stages, 277, 278 gain control methods, 266
Oscillator matching network, 194
analysis offset cancellation loop, 262
negative Output matching
resistance/conductance, amplifier, 377–379, 384–386
32–34 mixer, 193–194
positive feedback, 27–32 Smith chart, 322–327
Butler oscillator, 103 transmission line, 283–286, 295
calculation of oscillation Output power control, 392, 399
frequency, 46–47 Output power in PA, 426–430
cross-coupled oscillator, 92, 156 back-off linearization technique,
crystal oscillators, 41–45 455–456
datasheet, 45–46 class B push-pull, 445
DAMPS transceiver, 18–19 class D, 450
harmonic calculation, 81 class E, 452
hypothetical model, 89–90 compression, 431
increasing Q and frequency efficiency, 427
stability, 77–78 LINC linearization technique,
integer-N frequency synthesizer, 460
17–18, 158–161 switching amplifier chain, 463
large-signal loop analysis, 74–76 Output third intercept point (OIP3),
LO, see Local oscillator (LO) 173–174, 177–179, 194–202
482 INDEX

Output voltage swing signal in transceiver, 3

automatic gain control, 257 transceiver, 176
nonlinear amplifier, 49–52 Periodic output of PFD, 161
power amplifier, 425 Phase detector
class A, 442 frequency demodulation,
class B, 443 130–138
class D, 449 frequency synthesizer, 17,
Output waveform for basic mixer, 170 158–161
Overdrive voltage effect on unity Gilbert cell as a phase detector,
current gain frequency, 273 131–134, 234
Overlap in phase detector, 130 PLL, 141–145, 150–152
Overlap of drain voltage in class F quadrature phase (FM) detector,
power amplifier, 452 134–138
Overtone in crystal resonance, 44 Phase error
DUT, 358
Parallel capacitor using stubs, 306 QPSK, 241
Parallel inductor using stubs, 306 Phase feedback in polar modulation,
Parallel resistanc 458
quality factor, 56 Phase locked loop (PLL)
Parallel resistance as frequency synthesizer, 19
quality factor, 311 Phase margin of PLL, 152–153, 157,
Parameters of transfer function, 164
349–351 Phase mismatch, 240–243
Parameters, scattering, 351–357 Phase modulation (PM), 31, 223
Parasitic capacitance, 284 AM to PM conversion, 426, 432,
inductor, 65 438, 455, 458
power amplifier, 440, 451 AM to PM distortion, 426, 431,
transistor, 46, 274, 277 461
Parasitic effect power amplifier, 461
oscillator, 46–47 spectral regrowth, 433–434
Parasitic inductor, 284 Phase noise, 30–32, 158
Passive component, 283 Phase offset, 17
filter, 10 Phase shift
lossy element, 48 BPSK, 235
positive resistor, 32 BPSK modulator, 238–239
reactive element, 49 GMSK, 243–244
Passive source and load lossless transmission line, 293
matching, 322 OQPSK, 243–244
PA stability, 440 oscillator, 36, 134
stability, 377, 380–384 QPSK, 235–236, 239–240,
Passive switching mixer, 180, 186–187 243–244
Peak detection, 269 SSBSC, 229–230
Peak to average ratio (PAR), 459 Phase shift keying (PSK), 235
Peak value of EVM, 439 Phase shifter, 117
Performance phase-locked loop (PLL)
amplifier, 377, 380–384 applications, 150–161
mixer, 171 as frequency modulator, 156–158
INDEX 483

as frequency synthesizer, 17 switching amplifiers chain,

basic concept, 141–144 462–463
charge pump, 161–163 nonlinearity
loop bandwidth, 141–143, AM to AM distortion, 432
150–151 AM to PM distortion, 432–434
phase detector, see Phase detector decreasing NPR, 439
phase/frequency detector, see increasing EVM, 439
Phase/frequency detector spectral regrowth, 435
setteling time, 5 undesired harmonic
tradeoff in design, 161 components, 434–435
type I, 144–145 specifications, 426
type II, 161 efficiency, 426–427
Phase/frequency detector (PFD), gain, 430–431
161–164 linearity considerations,
Phases 431–432
16-QAM, 236 output power, 427–429
64-QAM, 237 receive-band noise, 429–430
BPSK, 235 stability, 440
charge pump, 161–164 topologies, 440
polar modulation feedback, 458 class 1/D, 451
QPSK, 235 class A, 441–442
PLL response, 152 class AB, 445–446
Polar modulation power amplifier, 458 class B, 443–445
Port-to-port leakage in mixer, 169, class C, 446–448
186, 187 class D, 448–451
Positive feedback in oscillator, 27–32 class E, 451–452
Power added efficiency (PAE), class F, 452–453
426–428 class S, 454
Power amplifier (PA) transmitter chain, 5
comparison between classes, 448, Power combining
455 envelope elimination and
considerations, 425–426 restoration PA, 461
DAMPS transceiver, 19 feedforward PA, 459–460
linearity and linearization, see switching amplifiers chain PA,
linearity and linearization 463
linearization techniques, 455 Power consumption
back-off, 455–456 fT doubler, 274
Cartesien modulation amplifier, 377
feedback, 459 modulator, 233
EER, 461 power amplifier, 425, 450
feedforward, 459–460 Power consumption cost, 12, 16
LINC, 460–461 Power control in PA, 429
polar modulation feedback, Power conversion gain in mixer, 193
458 Power dissipation
predistortion, 456–457 power added efficiency (PAE),
pulse amplitude and width 426–427
modulation, 461–462 power amplifier
484 INDEX

class A, 442 Quadrature transmitter, 179, 240

class B, 445 Quality factor (Q)
class C, 448 band-pass filter, 55–56
class D, 451 capacitive transformer, 68
class E, 452 crystal, 77–78
class F, 452 crystal oscillator, 41–43
quality factor of reactive definition, 15–16, 307–308
elements, 47–48 detector, 134–138
Power gain discrete inductor, 65
amplifier design, 377, 405–406 inductive transformer, 67
available, 379, 384–385, 398 matching networks, 311–322
noise figure calculation, 401 on-chip inductor, 66
operational, 379, 391–398 reactive elements, 47–49
transducer, 378, 385 transformer, 65
Power gain contours, 391–398 Quantifying linearity in PA, 431–439
Power spectral density (PSD), 28–32 Quantization noise, 399–403
Power splitter, 357
Power-efficient supply modulator in Radiation
EER linearization technique, air, 277
461 undesired radiation risk, 306
Predistortion linearization technique, Random function, as offset voltage,
455–457 262
Predriver, 425 Random movement of electrons, 32,
probability density function (PDF), 399
429 Random noise signal, 31, 173
Programmable counter, 17 Random phase noise of carrier, 32
Propagation in transmission line, 284, Random phase shift, 32
286–291 Random process, as noise, 28–32
Propagation in two-port network, 349 Rayleigh fading, 8–10
Pulsewidth modulation, 455, 461–462 RC network, 310
Receive band noise, 426, 429–431
QPSK signal constellation, 236 Receive band of GSM, 4
Quadrature amplitude modulation Receiver (RX)
(QAM), 235, 243 channel selection, 16
Quadrature constellation, 235 coherent receiver, 32
Quadrature digital modulation, 19, DAMPS, 10–16, 18
243, 459 frequency synthesizer, 17
Quadrature frequency demodulation, intermodulation issue, 176
245, 459 spectral behavior, 13–15
Quadrature mismatches, 241 detection, 12, 134
Quadrature phase detector, 19, direct-conversion, 241
134–138 frequency synthesizer, 158–161
Quadrature phase shift keying (QPSK), gain in receiver chain, 10–16
161, 235–237, 241, 243–244 general block diagram, 4
generation, 239–240 GSM, 4
Quadrature receiver, 242 heterodyne, 11–12, 179
Quadrature tank, 136–137, 159 intermodulation issue, 176–179
INDEX 485

QPSK, 240 inductor Q, 48

quadrature receiver architecture, loss resistance, 55
242–243 matching
Rayleigh fading, 8 offset cancellation loop, 262
receive-band noise, 429–430 T-line, 306–322
sensitivity, 261 mixer
signal-to-noise ratio, 173, 439 degeneration resistor, 203–205
standard specification, 180 diode mixer on-resistance, 170
superheterodyne, 11–12 switch mixer on-resistance,
zero-IF, 5, 19 186
Reference Driscoll oscillator, 121 MOS transistor in triode region,
Reference frequency in integer-N 267
frequency synthesizers, negative resistance in oscillator,
17–19 27, 32–34
Reference impedance power amplifier
decibels (dB), 8 switch on-resistance in class D,
matching networks, 283 450
network analyzer, 359 switch on-resistance in class E,
scattering parameters, 351 451
Reference power switch on-resistance in class S,
dBm, 8 454
Reflected signal from DUT, 357 power splitter, 357
Reflected wave quality factor (Q), 54–56
lossless transmission line, real capacitor model, 49
301–303 real inductor model, 48
scattering parameters, 351–352 series resistance in charge-pump,
transmission line, 288, 294–296 163
Regulatory organizations, 180 T-line
Representation of two-port networks, lossless T-line, 292
349–357 lumped model of T-line, 286
Resistance and resistors matching, 306–322
active inductor model, 275 terminating resistor, 285
amplifier thermal noise, 28, 399–400
stability issue, 380 Resistive termination in noise
terminating resistor, 377 calculation, 400
capacitor Q, 49 Resonance condition in oscillators, 40
constant resistance contours, Resonance frequency
323–324 crystal oscillator, 41–44
cross-coupled oscillator, 157 phase noise, 30–32
decreasing input capacitance, quality factor, 15, 47–49
276–277 VCO, 91–93
degeneration resistor in AGC, Reverse biased diodes, as varactor,
270–272 91–93
diode on-resistance, 268 Reverse isolation
emitter dynamic resistance, 49 S-parameter calculation, 355, 364
gain control methods, 265–266 RF choke (RFC), 358
gate resistance, 273 RF Feedthrough, 185
486 INDEX

Ripple Shunt peaking, increasing AGC

peak detector, 268 bandwidth, 274–276
supply voltage, 93 Sideband
Rollett’s stability factor, 384 DSBSC, 229–230
noise, 29
Sampling mixer, 170 SSBSC, 229–230
Scattering parameters Signal constellation, 235–237, 239,
amplifier design, 377 241, 242
calibration, 358–360 Signal injection, 235
definition, 351–352 Signal-to-noise ratio (SNR), 173, 241,
measurement, 357–360 266, 306, 401
network analyzer, 357–358 Simulation
simulation time for IIP3 , 212–213
two-port networks, 349–352
Single-balanced mixer, 184–185, 187,
Second-order band-pass filter, 47
190–191
Second-order nonlinearity, 208
Single-ended class D amplifier, 452
Self-resonance frequency of inductor,
Single-sideband suppressed carrier
275
(SSBSC), 229
Sensing nonlinearity in Cartesian
Skin effect, 48–49
feedback, 459
Slope of quadrature characteristic, 136
Sensing output of PA in feedforward
Small-signal tree in Gilbert cell,
technique, 459
234–235
Sensing signal in amplitude detector, Smith chart, 322–327
270 Smith chart rules, 327
Sensitivity Spectral purity, as a merit of oscillator,
DAMPS, 8 111
definition, 6 Spectral regrowth, 433–438
GSM, 8 Spiral inductor, 275
LNA effect on receiver Spur
sensitivity, 283 PLL, 161–164
mixer, 178 power amplifier, 428, 440
offset effect on receiver Square-wave LO, 170, 185
sensitivity, 261 Stability
PA effect on receiver sensitivity, amplifier, 377–384
429 conditionally stable, 380
wireless standards, 9 contours on Smith chart,
Serial-to-parallel converter, 240 381–384
Series inductance Rollett’s factor, 384
crystal model, 43 unconditionally stable,
implementation with stubs, 306 380–381
lumped model of T-line, 286 in temperature, 41
Series resistance multi-stages amplifier, 259
capacitor model, 49 offset cancellation loop, 263–265
crystal model (HC-49/U), 45 PLL type II, 161–164
inductor model, 48 power amplifier, 440
lumped model of T-line, 286 feedforward linearization
Settling time in PLL loop, 5, 158 technique, 459–460
INDEX 487

receiver front-end, 12 T-line, see Transmission line

signal oscillation, 27, 77 Tail current
Stability circles on Smith chart, automatic gain control, 265–266,
381–384 270
Standard, wireless limiter, 257
AMPS, 5 Terminals of a crystal, 41
DAMPS, 5, 6, 8, 10, 11, 13–18 Terminated transmission line,
GSM, 4–8 293–296, 298–300
GSM 850, 5 open-circuit, 300
IS-95 CDMA, 429, 438 short-circuit, 299–300
Static mode of oscillator, 144 to intrinsic impedance, 298
Statical model, Rayleigh distribution, Terminating resistor in amplifier, 377,
9 400
Subharmonic spurs in power amplifier, Terminating resistors in T-line, 285,
440 310
Substrate leakage, 277 Thermal noise, 28, 399
Substrate noise, 93 resistor, 32, 399
Switch on-resistance Thermal voltage VT , 50, 131
class D power amplifier, 450 Third intercept point (IP3), 172–180,
class E power amplifier, 451 194–202, 432
mixer, 186 cascaded stages, 209
Switch transistor Third-order intermodulation IM3 , 12
automatic gain control, 267 Third-order intermodulation IM3 ,
charge pump, 163 172–180, 194–202
class D power amplifier, 449–451 Time constant of control voltage in
class E power amplifier, 451–452 VCO, 127, 160
Gilbert cell, 234 Time division multiple access
mixer, 180, 185–188 (TDMA), 6
Switchable amplifier chain, 455, Time varying voltage in varactor, 93
462–463 Time-variant transconductance, 222
Switched-capacitor DC to DC Tone
converter, 461 modulation, 157
Symbol PLL, 137, 151
16-QAM, 237 power amplifier, 426, 433
64-QAM, 237 RF circuits simulation, 213
BPSK, 235 Total bandwidth in multistage
QPSK, 235 amplifier, 259–261
Symbol rate, 240 Total capacitance in VCO, 92, 157
Symmetrical swing in class D power Total DC power dissipation in PAE
amplifier, 449 calculation, 427
Synchronous AM detection, 231–233 Total gain-bandwidth, 260
Synthesizer, 17–19, 91, 158, 161 Total IIP3 of cascaded stages, 209
System level design Total NF in multistage amplifier, 409
PFD, 161 Total noise power in amplifier, 399
PLL, 157 Total phase
SSBSC, 229, 230 modulation, 129
transceiver, 3 PLL, 144
488 INDEX

Total quality factor Transformer

T matching network, 322 capacitive step-up, 38, 65–74
π matching network, 319 inductive, 61, 65–74
band-pass filter, 55 transmission line, 304–305
Total receive bandwidth, 7 Transformer in class D power
Trade-off in design amplifier, 449
amplifier, 399, 402, 405 Transformer ratio m, 75
Tradeoff in design Transient response of PLL loop, 152
modulator, 240 Transistor-based amplifier, 377
PLL, 161 Transistors
power amplifier, 425 as varactors, 156
Transceiver cross-coupled oscillator, 156
channel selection, 7, 10–16 high speed transistors, 273
considerations, 10–16 linearity, 203–205
DAMPS, design example, 5–8, MOS, 61, 83, 133–134
18 as resistor in triode region, 267
harmonic issue, 169 dual-gate, 266
receiver, see Receiver (RX) offset voltage problem, 261
speed and performance, 161, 176
oscillator, 53–54
system design, 3–5
stability issue, 377–379
transmitter, see transmitter (TX)
Transmission line (T-line)
Transconductance
λ /4 line (Impedance Inverter),
amplifier, 435
304–305
automatic gain control, 265–266
characteristic impedance,
increasing bandwidth method,
291–293
273–277
mixer, 170 frequency response, 284–286
oscillator, 53–63, 74–76 ideal lossless T-line, 284–286
common-emitter with emitter impedance matching, 283–286,
degeneration, 82–83 322
differential pair, 90–91 T matching network, 320
hypothetical model, 89–90 π matching network, 316–317
Transducer power gain, 378, 380, 385 L-section approach, 306–312
Transfer function quality factor, 311–312
band-pass filter, 47 Smith chart mapping, 322–327
demodulator, 138 impedance transformation, 285
filters, 13 lumped model, 286
frequency synthesizer, 158–161 microstrip, 66
low-pass filter, 143 mismatch, 301–303
PLL overview, 283
type I, 144–156 synthesis of capacitor by T-line,
type II, 161–164 305
S-parameters, 349–351 synthesis of inductor by T-line,
Transformation, passive impedance 305
capacitive, 67–69 terminated T-line, 293–296
inductive, 65–67 line characteristic impedance,
transmission line, 285, 286–305 298
INDEX 489

open-circuit load impedance, Upconversion and upconversion mixer

300 DAMS transceiver, 19
short-circuit load impedance, direct-conversion transmitter, 240
299–300 modulator, 224, 226
voltage standing wave ratio, SSBSC, 230
305–306 transmitter, 5, 179, 425
wave propagation, 286 unbalanced mixer, 189–190
lossless T-line, 286–289 Uplink, 6
lossy T-line, 289–291
Transmit band, 429 Varactor
Transmitted wave in scattering modulation, 127
parameters, 351 types, 91–93
Transmitter (TX) VCO, 91, 156–158
consideration in design, 180 Variable-delay in transmission line,
DAMPS, 10–11, 18–19 285
Frequency synthesizer, 158–161 Variable-gain amplifier, 265–267,
general block diagram, 4–5 270–272, 458
GMSK, 244 Variable-load in matching, 308
minimum required power, 306 Voice signal, 12, 127, 137
power amplifier, see Power Voltage controlled oscillator (VCO)
amplifier (PA) in PLL loop, 163
power specifications, 428 Voltage swing
probability density function AGC, 257
(PDF), 429 nonlinear amplifier, 49–52
quadrature direct-conversion, 241 power amplifier, 425
quadrature heterodyne class A, 442
transmitter, 179 class B, 443
transmit-band noise, 429–430 class D, 449
Tunability in matching network, 307 Voltage to current conversion, 98, 186,
Tuned amplifier, 51, 53–63, 435 295
Tuning voltage in VCO, 91–93 voltage-controlled oscillator (VCO), 5,
Two terminal oscillator, 32, 33 17–19
Two terminal resonator, 32, 33 characteristics, 151
Two-port network free-running frequency, 141–144,
generic model, 349–350 152
Two-tone test frequency modulation, 127–129
intermodulation, 194–202, 209, in PLL loop, 156–161
432 overview, 91–93
power amplifier, 432 Voltage-dependent capacitor, 432

Unbalanced mixer, 184–185, 188–190 Wave propagation

Unilateral amplifier, 385, 391 methods, 3
Unilateral device, 385, 391, 405 through T-line, 283, 286–291
Unilateral network, stability, 380 White noise, 28, 29, 399
Unit, 429 White spectrum, 28
Unity power gain ( fmax ), 273 Wireless communication overview,
Unity-gain frequency, 259, 274, 449 3–8
490 INDEX

Wireless standard World of wireless, 3–8

AMPS, 5
DAMPS, 5, 6, 8, 10, 11, 13–18 XOR in phase detector
GSM, 4–8 (Exclusive-OR), 130
GSM 850, 5
IS-95 CDMA, 429, 438 Zero-IF receiver, 5, 19
Authors Biographies

Forouhar Farzaneh was born in Tehran, Iran in 1957. He received his B.S. in
Electrical Engineering from the University of Shiraz, in 1980, Master degree
from E.N.S.T., Paris in1981, DEA and Doctorate from University of Limoges,
France in 1982 and 1985, respectively. He was with Tehran Polytechnic from
1985 to 1989. Since 1989 he has been with the Department of Electrical
Engineering, Sharif University of Technology where he is a Professor. He was
the Chairman of the Department of Electrical Engineering, from 1992 till 1995.
His main areas of interest are Nonlinear RF Circuits, Microwave and
Millimeter wave systems, Antenna Arrays and Wireless Communications. He
is the author of a book in the field of Communication Circuits in Persian,
published by Sharif University Press.
He has been a Senior Member of IEEE since 1997. He was a co-recipient
of the Microwave Prize-European Microwave Conference in 1985, a recipient
of the Maxwell Premium of IEE, U.K. in 2001, and co-recipient Mojtahedi
Innovation Award (Sharif University of Technology) in 2010. He was also
the recipient of the 2015 Hakkak award, in recognition of his tremendous
life-time contribution to national development and propagation of research in
Communications Engineering presented by IEEE-Iran Section.

Ali Fotowat was born in Tehran, Iran, in 1958. He received the B.S. degree in
Electrical Engineering from the California Institute of Technology, Pasadena,
CA, USA, in 1980, and the M.S. and Ph.D. degrees in Electrical Engineering
from Stanford University, Stanford, CA, USA, in 1982 and 1991, respectively.
492 Authors Biographies

He started his career at Philips Semiconductor in Sunnyvale, CA, USA,

in 1987 where he developed several integrated circuits for mobile phones. In
1991 he joined the Electrical Engineering Department of Sharif University of
Technology, Tehran, Iran. His research interests include advanced integrated
circuits for energy savings and communication/positioning applications. Due
to his interests in entrepreneurial engineering, he has been the co-founder of
several companies, including KavoshCom Asia R&D Company, alongside
advising his students in the field.
Dr. Fotowat-Ahmady is a three times recipient of the Khwarizmi Science
and Engineering Award for his work on low-power microelectronics and com-
munication ICs. He is a member of the IEEE Solid-State Society and has been
the adviser of the society’s Sharif Electrical Engineering student chapter.

Mahmoud Kamarei received M.S. in Electrical Engineering from University

of Tehran in 1979, M.S. in Communications Engineering from E.N.S.T., Paris,
France, in 1981, and Ph.D. degree in electronics from the Institute National
Polytechnique de Grenoble (INPG), Grenoble, France, in 1985.
He was a Researcher at the Laboratoire d’Electromagnétisme Micro-ondes
et Optoélectronique, INPG, from 1982 till 1985. He was a Master of Confer-
ences at the J. Fourier University of Grenoble from 1985 till 1991. He has been
with the University College of Engineering, School of Electrical and Computer
Engineering, University of Tehran since 1991, where he is currently a Profes-
sor of Electrical Engineering. He was the Dean of the University College of
Engineering, University of Tehran for 8 years, 2009-2017. He is also a faculty
member at the Center of Excellence on Applied Electromagnetic Systems,
School of Electrical and Computer Engineering, University of Tehran.
His main research interest areas include RF CMOS IC Design, Design and
Linearization of the RF Power amplifiers, Low-phase-noise oscillator design,
PLLs and Injection Locked Oscillators.

Ali Nikoofard was born in Tehran, Iran, in 1990. He received his B.S. in
Electrical Engineering from Shahed University, Tehran, in 2012, M.S. in Elec-
tronics from Sharif University of Technology, Tehran, in 2014, and M.S. from
Case Western Reserve University, Cleveland, OH, USA, in 2017 in integrated
circuit design. He was with KavoshCom Asia R&D Company from 2014 to
2015. He is now working toward Ph.D. at University of California at San Diego,
La Jolla, CA, USA, on ultra-low-power transceiver design with new power
efficient modulation schemes. He is a member of the IEEE Solid-State Circuits
Society since 2013. His current research interests include wireless transceivers,
frequency synthesizers, phase-locked loops and ultra-low-power circuit.
Authors Biographies 493

Mohammad Elmi was born in Tehran, Iran, in 1988. He received his B.S.
degree in Electrical Engineering from Noshirvani University of Technology,
Babol, Iran, in 2013, and M.S. degree in Electrical Engineering (Analog Elec-
tronics) from Shahid Beheshti University, Tehran, Iran, in 2015. He has been
with KavoshCom Asia R&D Company since 2015. He is now working on a
low-power wireless heart monitoring system as a member of research team at
KavoshCom Asia. His research interests include RF integrated circuits design,
low-power analog circuit design, wireless communication transceivers, and
mm-wave integrated circuits.
River Publishers Series in Circuits and Systems

Introduction to Wireless

Communication Circuits
Introduction to Wireless
Communication Circuits
Introduction to Wireless

2nd Edition
2nd Edition

Forouhar Farzaneh, Ali Fotowat,

Communication Circuits
Mahmoud Kamarei, Ali Nikoofard 2nd Edition
and Mohammad Elmi
Forouhar Farzaneh
Over the past decade the tremendous development of Wireless Ali Fotowat
Communications has changed human life incredibly. Considerable
advancement has been made in the design and architecture of Mahmoud Kamarei
communications related RF and Microwave circuits. This book is focused
on special circuits dedicated to the RF level of wireless Communications.
Ali Nikoofard
From Oscillators to Modulation and Demodulation and from Mixers to Mohammad Elmi I
RF and Power Amplifier Circuits, the topics are presented in a sequential

Mahmoud Kamarei, Ali Nikoofard

Forouhar Farzaneh, Ali Fotowat,
manner. A wealth of analysis is provided in the text alongside various
Q
worked out examples. Related problem sets are given at the end of each
chapter. Basic concepts of RF Analog Circuit Design are developed in π/2

and Mohammad Elmi

÷N VCO
the book.
Technical topics discussed in the book include: PLL ÷M
• Wireless Communication System
• RF Oscillators and Phase Locked Loops
• Modulator and Demodulator Circuits
I
• RF Mixers
• Automatic Gain Control and Limiters +
• Microwave Circuits, Transmission Lines and S-Parameters Q
• Matching networks π/2
PLL

• Linear Amplifier Design and Power Amplifiers

• Linearization Techniques
Foreword by
Behzad Razavi, UCLA, USA

River Publishers River River Publishers