FPGA

• FPGA Basics
• FPGA Architecture
– CLBs
– I/O Blocks
– Switch Matrix
• Xilinx FPGAs
• System Development Boards

2
Advantages of FPGA
• The FPGA is one of the most popular logic circuit components
and has revolutionized the way digital systems are designed.
Some FPGA advantages include:
– Low-cost
– Fast-turnaround prototype implementation
– Supported by CAD/EDA tools
– High density
– High speed
– Programmable and versatile
– Flexible
– Reusable
– Large amounts of logic gates, registers, RAM and routing resources
– Quick time-to-market
– SRAM FPGA provide the benefits of custom CMOS

3
FPGA
• There are two primary FPGA architectures:
– fine-grained
– coarse-grained

• Another difference in architectures is the underlying

technology used to manufacture the device. The
common technologies are:
– PROM/EPROM/EEPROM/FLASH based
– Anti-fuse based
– SRAM based

4
Programmable Switch Technology
• SRAM
• Antifuse
Control Pass Gate
• EPROM
SRAM SRAM
Cell Cell

0 1

Multiplexer

0 or 1 MUX

5
Programmable Switch Technology
• SRAM
• Antifuse
Disadvantages
• EPROM Volatile
External Permanent Memory
Required
Large Area Required

Advantages

Reprogrammable, easily and quickly

Requires only standard integrated
circuit process technology (as
opposed to Antifuse)
6
Programmable Switch Technology
• SRAM
• Antifuse
• EPROM 0

7
AntiFuse Technology
• Growing an antifuse
Programmable Switch Technology
• SRAM
• Antifuse
Disadvantages
• EPROM Not reprogrammable; links made are
permanent
Requires extra circuitry to deliver
the high programming voltage

Advantages

Small size
Relatively low series resistance
Low parasitic capacitance
9
Programmable Switch Technology
• SRAM
• Antifuse Word Line
Control Gate
• EPROM

Bit Line
-- Oxide Layer
Floating Gate
1

Drain Source

Word Line
Control Gate
Bit Line

------- Oxide Layer

Floating Gate 0

Drain Source

10
Programmable Switch Technology
• SRAM
• Antifuse
Disadvantages
• EPROM High resistance of EPROM
transistors
High static power consumption
UV light exposure needed to
reprogram

Advantages

No external memory required; retains

memory even without power
Reprogrammable

11
Programmable Switch Technology
• A summary of programmable switches

12
FPGA Architectures
• Fine-grained Architecture
– Fine-grained made up of a sea of gates or
transistors or small macro cells
– With programmable interconnect between them

Almost the opposite of a CPLD

13
FPGA Architectures
• Coarse-grained Architecture
– Coarse-grained FPGAs include bigger macrocells
– The macrocells usually include Flip-Flops and Look
Up Tables (LUTs) which are used to implement
combinatorial logic functions
– In a majority of these architectures, four-input look-
up table (think of it as a 16x1 ROM) implement the
actual logic
– The larger logic block usually results in improved
performance when compared to fine-grained
architectures

14
FPGA Process Technology
• PROM/EPROM/EEPROM/FLASH based
– These implementations are typically programmed
out of circuit and can or cannot be reprogrammed
• PROM is one time programmable (OTP) device can only be
programmed once
– EPROM cells are electrically programmed in a
device programmer
– Some EPROM-based devices are erasable using
ultra-violet (UV) lights if they are in a windowed
package
– EEPROMs are in low-cost plastic packaging for
production
• Plastic packages cannot be UV erased, they are electrically
erased

15
FPGA Process Technology
• PROM/EPROM/EEPROM/FLASH based
– An Electrically-Erasable-Programmable-Read-Only-
Memory (EEPROM) memory cell is physically
larger than an EPROM cell but offers the advantage
of being erased electrically with no special UV
erasers require.
• EEPROM devices can be erased, even in low-cost plastic
packaging.
– FLASH-erased (or bulk erased) electrically erasable
programmable read-only memory.
• FLASH has the electrically erasable benefits of EEPROM
but the small, economical cell size of EPROM technology.

16
FPGA Process Technology
• Anti-fuse based
– Anti-fuse is a one-time programmable (OTP)
– Fuses are permanently put in place
– The anti-part of anti-fuse comes from its
programming method
• Instead of breaking a metal connection by passing current
through it, a link is grown to make a connection
– Anti-fuses are either amorphous silicon or metal-to-
metal connections

17
FPGA Process Technology
• Anti-fuse based
– The advantages of anti-fuse FPGAs include:
• They are usually physically quite small
• They have low resistance interconnect
– Disadvantages include
• They require large programming transistors on the device
• They cannot be reused (they are OTP)

18
FPGA Process Technology
• SRAM based
– SRAM cells are implemented as function generators to
simulate combinatorial logic and also are used to
control multiplexors and routing resources
– This is by far the most popular process technology
– This method is similar to the technology used in static
RAM devices but with a few modifications
• The RAM cells in a memory device are designed for fastest
possible read/write performance
• The RAM cells in a programmable device are usually designed
for stability instead of read/write performance
• Consequently, RAM cells in a programmable device have a
low-impedance connect to VCC and ground to provide maximum
stability over voltage fluctuations
19
FPGA Process Technology
• SRAM based (cont.)
– Because static memory is volatile (the contents
disappear when the power is turned off), SRAM-
based devices are "booted" after power-on
– This makes them in-system programmable and re-
programmable, even in real-time
– As a result, SRAM-based FPGAs are common in
reconfigure computing applications where the
device's function is dynamically changed

20
FPGA Process Technology
• SRAM based (cont.)
– The configuration process typically requires only a
few hundred milliseconds at most
– Most SRAM-based devices can boot themselves
automatically at power-on much like a
microprocessor
– Most SRAM-based devices are designed to work
with either standard byte-wide PROMs or with
sequential-access serial PROMs

21
FPGAs
• Historically, FPGA architectures and
companies began around the same time as
CPLDs
• FPGAs are closer to “programmable ASICs”
– Large emphasis on interconnection routing
– Timing is difficult to predict -- multiple hops vs. the
fixed delay of a CPLD’s switch matrix
– But more “scalable” to large sizes
• FPGA programmable logic blocks have only a
few inputs and 1 or 2 flip-flops, but there are a
lot more of them compared to the number of
macrocells in a CPLD
22
FPGAs
• General FPGA chip architecture, coarse-grained

a.k.a. CLB: “configurable logic block”

23
FPGAs
• FPGAs do not contain AND or OR planes
• Three major elements:
Interconnection
– Logic blocks Switches
Logic
Block
– I/O blocks
– Interconnection wires
and switches

all elements are

programmable

I/O Block

24
Other FPGA Building Blocks
• Clock distribution
• Embedded memory blocks
• Special purpose blocks:
– DSP blocks:
• Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers
– High-speed serial transceivers
FPGA – Basic Logic Element
• LUT to implement combinatorial logic
• Register for sequential circuits
• Additional logic (not shown):
– Carry logic for arithmetic functions
– Expansion logic for functions requiring more than 4 inputs

Select

Out

A
B
C LUT
LUT D Q

Clock
Look-Up Tables (LUT)
• Look-up table with N-inputs can be used to implement
any combinatorial function of N inputs
• LUT is programmed with the truth-table

A
B
C LUT
LUT Z
D

LUT implementation

A
B
Z
C
D

Truth-table Gate implementation

LUT Implementation
• Example: 3-input LUT
• Based on multiplexers X1
X2
(pass transistors) 0/1
• LUT entries stored in 0/1
configuration memory 0/1
cells 0/1
F
0/1
0/1
0/1
0/1
configuration memory cells
X3
Other FPGA Building Blocks
• Clock distribution
• Embedded memory blocks
• Special purpose blocks:
– DSP blocks:
• Hardware multipliers, adders and registers
– Embedded microprocessors/microcontrollers
– High-speed serial transceivers
Special Features
• Clock management
– PLL,DLL
– Eliminate clock skew between external clock input
and on-chip clock
– Low-skew global clock distribution network
• Support for various interface standards
• High-speed serial I/Os
• Embedded processor cores
• DSP blocks
Configuration Storage Elements
• Static Random Access Memory (SRAM)
– Logical configuration is controlled by the state of
SRAM bits
– FPGA needs to be configured at power-on by
another separated ROM
• Flash Erasable Programmable ROM (Flash)
– Logical configuration is implemented by floating-
gate transistors that can be turned off by injecting
charge onto its gate.
– FPGA itself holds the program
– reprogrammable, even in-circuit
FPGA
• Xilinx refers to the “interconnection switches” as the
switch matrix IOB IOB IOB IOB

IOB
IOB
CLB CLB CLB CLB
SM SM SM
Programmable
Switch Matrix

IOB
IOB CLB CLB CLB CLB
SM SM SM

IOB
IOB

CLB CLB CLB CLB

SM SM SM

IOB
IOB

CLB CLB CLB CLB

IOB IOB IOB IOB
32
FPGAs
• Programmable Switch Matrix

programmable switch element

turning the corner, etc.

33
FPGA Logic Block
• The storage cells in the LUTs in an FPGA are volatile
– losing stored contents whenever the power is off
• Using PROM to hold data permanently
• The storage cells are loaded automatically from
PROM when the chip is initialized

Select
Logic Block x1
Out 0/1
In1 0/1
In2 LUT 0/1
f
In3 LUT D
0/1
In4 Q
Clock x2

34
FPGAs
• An example of programming an FPGA
x3 f

f1 = x1 x2
x1 f 2 = x2 x3
x1 0 x2 0
0
f1
1
f2 f = x1 x2 + x2 x3
0 0
1 0
x2 x2 x3

f1 0
1 x1
f3
1 0/1
0/1
1 LUT 0/1
f
f2 0/1
x2

35
FPGAs
• An example of programming an FPGA
x3 f

f1 = x1 x2
x1 f 2 = x2 x3
x1 0 x2 0
0
f1
1
f2 f = x1 x2 + x2 x3
0 0
1 0
x2 x2 x3

f1 0
1 x1
f3
1 0/1
0/1
1 LUT 0/1
f
f2 0/1
x2

36
Xilinx 4000-Series FPGAs
• Characteristics of the Xilinx 4000-series FPGAs

37
Configurable Logic Block (CLB)

38
Logic Function Generators
• Look-Up Tables (LUT)
– Memory to store truth tables
• F, G
– 16 x 1 SRAMs
•H
– 8 x 1 SRAM

• Can be configured as memory

39
CLB function generators (F, G, H)
• Use RAM to store a truth table
– F, G: 4 inputs, 16 bits of RAM each
– H: 3 inputs, 8 bits of RAM
– RAM is loaded from an external PROM at system
initialization.
• Broad capability using F, G, and H:
– Any 2 funcs of 4 vars, plus a func of 3 vars
– Any func of 5 vars
– Any func of 4 vars, plus some funcs of 6 vars
– Some funcs of 9 vars, including parity and 4-bit
cascadable equality checking

40
FPGAs
• CLB input and output connections – buried in the sea
of interconnect

CLB

41
Detail

CLB
connections
controlled by
RAM bits

42
The Fitter’s Job
• Partition logic functions into CLBs
• Arrange the CLBs
• Interconnect the CLBs
• Minimize the number of CLBs used
• Minimize the size and delay of interconnect
used
• Work with constraints
– “Locked” I/O pins
– Critical-path delays
– Setup and hold times of storage elements

43
I/O Blocks

44
Spartan-II FPGA

45
Logic Fabric
• Logic Cell
I3
– Lookup table (LUT) I2
O 0 1
SET
CE
I1
– Flip-Flop D Q
I0
RST
– Carry logic
– Muxes (not shown)
• Slice I3
I2 SET
O 0 1
CE
– Two Logic Cells I1 D Q
I0
• Spartan-3E FPGAs RST

– 2K to 33K logic cells

46
Memory
• Block RAM DIA DOA
DIPA DOPA
– RAM or ROM
ADDRA
– True dual port
CLKA
• Separate read and write ports
– Independent port size DIB DOB
DIPB DOPB
• Data width translation
ADDRB
– Excellent for FIFOs CLKB
Block RAM Configurations
Configuration Depth Data bits Parity bits
16K x 1 16Kb 1 0
8K x 2 8Kb 2 0
4K x 4 4Kb 4 0
2K x 9 2Kb 8 1
1K x 18 1Kb 16 2
512 x 36 512 32 4

47
Multipliers
• 18 x 18 Multipliers
– Signed or unsigned 18 bit
– Optional pipeline stage 36 bit
– Cascadable
18 bit

48
Clock Management
• Digital Clock Managers (DCMs)
– Clock de-skew
– Phase shifting CLKIN CLK0

– Clock multiplication CLK90

– Clock division CLKFX

– Frequency synthesis

49
CLB Logic Cells (x4)

50
Dual-Port Block Ram (SRAM)

51
BASYS Board Components
• A training resource

52
BASYS Board Components
• 100K FPGA
• USB2 Port
• Flash ROM
• I/O Devices
• PS/2 and VGA
• Clock
• Expansion
Connectors

53
FPGA Selection Guide
• Xilinx Spartan-3 series FPGAs

54
Summary
• Complex Programmable Logic Devices
– Function Blocks
• AND Arrays and Macrocells
– Programmable Interconnect
– I/O
• Field Programmable Gate Arrays
– Configurable Logic Blocks
• Look-up Tables
– Programmable Interconnect
– I/O

55
Digital System Design
Lecture 8: Xilinx FPGAs

Amir Masoud Gharehbaghi

[email protected]
Table of Contents

{ Introduction
{ Xilinx FPGAs
z XC3000
z XC4000
z XC5000
z New series

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Introduction

{ The largest manufacturer of SRAM-

based FPGAs
{ Main Families:
z XC2000
z XC3000
z XC4000
z XC5000
z …

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Xilinx Series Comparison
Series I/O CLBs FFs Gate
Blocks Count
XC2000 58-74 64-100 122- 800-
174 1,800
XC3000 64-176 64-484 256- 1,300-
1,320 9,000
XC4000 64-256 64- 256- 1,600-
1,024 2,569 25,000
XC5000 148- 196- 784- 6000-
244 484 1,936 15000

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Xilinx FPGA Structure
{ Fixed array of
Configurabe Logic
Blocks (CLBs)
connectable by a
system of pass-
transistors, driven
by SRAM cells

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XC3000 CLB
{ 32-bit (5-input)
look-up table
{ CLB propagation
delay is fixed (LUT
access time) and
independent of the
logic function
{ 7 inputs to the
XC3000 CLB:
z 5 CLB inputs (A–E)
z 2 FF outputs (QX
and QY)

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XC3000 CLB Configurations
{ Use 5 (of 7) inputs with the
entire 32–bit LUT (CLB
outputs F and G are then
identical)
{ Split the 32-bit LUT in half
to implement 2 functions (F
and G) of 4 variables each;
choose 4 inputs (from 7)
{ Split the 32-bit LUT in half, 2

using one of the 7 input

variables as a select input to
a 2:1 MUX that switches
between F and G (to
implement some functions of
6 and 7 variables)

3
1

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Methods of Interconnection
{ Direct interconnect:
Adjacent CLBs are wired
together in the horizontal
or vertical direction. The
most efficient interconnect
(< 1 ns delay)
{ General-purpose
interconnect: used mainly
for longer connections or
for signals with a moderate
fan-out
z Few, so problem in fitting
a large design into
XC3000, and 2000
{ Long line interconnect: for
time critical signals (e.g.
clock signal need be
distributed to many CLBs)

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Design Example
Q2* = Q2’ Q1 + Q2 Q0
Q1* = X’ Q2’ Q1’ Q0 + X’ Q2’ Q0’ + X’ Q2 Q0’ + Q1 Q0
Q0* = Q0’
Z = X Q1 + X’ Q1’
{ Functions have maximum 4 variables
z 4 LUT of 4 variables
z 3 FFs
z 2 CLB required
{ FPGA Implementation
z Q2*, Q0* in one CLB
z Q1*, Z in one CLB

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Design Example Implementation

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Xilinx 4000 Series

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Xilinx 4000 Specs
{ Two FF per CLB + Two per I/O cell
{ 25 gates per CLB for logic
{ 32 bits of RAM per CLB
{ Special fast carry logic between CLBs
{ Interconnects:
z Direct and general-purpose wires replaced with
more efficient single-length and double-length
lines.
z Sufficient resources for most applications.

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Xilinx 4000 CLB

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CLB Function Generators
{ Use RAM for truth tables
z F, G: 4 input -> 16 bits of RAM (each)
z H: 3 input –> 8 bits of RAM
z RAM is loaded at system initialization from
external PROM
{ MUX control logic maps 4 control inputs
into 4 inputs:
z LUT input H1
z Direct In (DIN)
z Enable Clock (EC)
z Set/Reset control (S/R) for FFs
z Control F,G LUTs as 32 bit SRAM

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CLB Function Generators (cont.)

{ Broad capability:
z Any 2 functions of 4 variables plus a
function of 3 variables
z Any function of 5 variables
z Any function of 4 variables plus some
functions of 6 variables
z Some functions of 9 variables
{ Parity
{ 4-bit cascadable equality checking

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CLB input and output connections

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Programmable Switch Matrix

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XC5200 Logic Block
{ Similar to
CLBs in
XC2000/3000
/4000, but
simpler
{ A group of 4
Logic Cells
(LCs) is a CLB
in XC5200
{ LC contains
4-input LUT

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State-of-the-art FPGAs
{ XCS00/XL (Spartan)
z 5v, 3v
z 2,000-40,000 typical gate
{ XC2S00/XL (Spartan-II)
z 2.5v
z 6,000-150,000 typical gate
{ XCV00 (Virtex)
z 2.5v
z 34,000-1,124,000 typical gate

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State-of-the-art FPGAs (cont.)

{ 1999: Virtex-E
{ 2000: Virtex-II
{ 2002: Vitex-II Pro
z 125,136 logic cell
z 10 Mb RAM
z 556 18*18 Multiplier
z Up to 4 PowerPC 405 cores
{ 300 MHz+, 420 MIPS

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