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Algorithm Imp (Add, Multi)

- Addition and subtraction of numbers in two's complement form involves treating the sign bit like other bits and discarding any carry out of the sign bit position. Overflow is detected with an exclusive-OR gate comparing the last two carries. - Multiplication of signed-magnitude numbers is done by successively shifting and adding the multiplicand for each bit of the multiplier. Hardware implements this by accumulating partial products in a register using an adder and shifting partial products right instead of the multiplicand left. The multiplier is stored in register Q and its sign in Qs.

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S.Ramesh raja
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15 views

Algorithm Imp (Add, Multi)

- Addition and subtraction of numbers in two's complement form involves treating the sign bit like other bits and discarding any carry out of the sign bit position. Overflow is detected with an exclusive-OR gate comparing the last two carries. - Multiplication of signed-magnitude numbers is done by successively shifting and adding the multiplicand for each bit of the multiplier. Hardware implements this by accumulating partial products in a register using an adder and shifting partial products right instead of the multiplicand left. The multiplier is stored in register Q and its sign in Qs.

Uploaded by

S.Ramesh raja
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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II B.

Sc CS - Computer Architecture

• The sign of the result is the same as the sign of A. so no change in A is required.
However, when A < B, the sign of the result is the complement of the original
sign of A
• The final result is found in register A and its sign in As.

Addition and Subtraction with signed2’s complement data


• The left most bit of binary number represents the sign bit; 0 for positive and 1
for negative.
• If the sign bit is 1, the entire the entire number is represented in 2’s complement
form.
• The addition of two numbers in signed-2’s complement form consists of adding
the number with the sign bits treated the same as the other bits of the number . A
carry out of the sign bit position is discarded .
• The subtraction consists of first taking the 2’s compliment of the subtrahend and
then adding it to the minuend When two numbers of n digits each are added and
the sum occupies n+1 Digits, we say that an overflow occurred.
• When the two carries are applied to an exclusive-OR gate, the overflow is
detected when the output of the gate is equal to 1.

• The left most bit in AC and BR represents the sign bits of the numbers
• The over flow flip-flops V is set to 1 if there is an overflow. The output carry in
this case is discarded.

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II B.Sc CS - Computer Architecture

• The sum is obtained by adding the contents of AC and BR(including their sign
bits).
• The overflow bit V is set to 1 if the ex-OR of the last two carries is 1,and it is
cleared to 0 otherwise.

2. Multiplication algorithms

Multiplication of two fixed point binary numbers in signed magnitude representation is


done with paper and pencil of successive shift and add operation if the multiplier bit is a
1,the multiplicand is copied down; otherwise zero are copied down.

Hardware Implementation for Signed-Magnitude data


• Multiplication is conveniently implemented with two changes in the process
- Use an adder to add binary numbers as there are bits in multiplier and
successively accumulate the partial products in a register.
- Instead of shifting the multiplicand to the left , the partial product is shifted to
the right
• The hardware for multiplication consists of registers Q, A and B.
• The multiplier stored in the Q register and its sign in Qs.

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