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org MOS Capacitors: Theory

online simulations and more and Modeling

1. Introduction
2. MOS Capacitor Electrostatics
A. Delta-Depletion Approximation
B. Exact Analytical Model
C. SCHRED: Self-Consistent Schrödinger-
Poisson Solver
3. Ideal MOS Capacitor Capacitance
4. Deviations from the Ideal Model

Dragica Vasileska, ASU

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1. Introduction

• The Si MOSFET is the most important solid-state device

for modern electronics. To understand its operation, we
first need to understand the MOS capacitors:

V
oxide thickness metal
dox
oxide

Semiconductor
(p-type or n-type)

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nanoHUB.org Energy-band diagram of IDEAL MOS
online simulations and more capacitor
 M   sc
n-type semiconductor p-type semiconductor
Vacuum level
 sc  sc
 sc  sc EC
M M

EC Ei
q F
E FM E FS E FM E FS
Ei EV
q F
EV

Eg Eg
 M   sc   q F  M   sc   q F
2 2
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Accumulation
• Ideal MOS capacitor under accumulation bias conditions:
 VG

EC

p-type SC E FM Ei
E FS
holes
EV

qVG
(x ) QS
Accumulation of
majority holes

x Energy
d ox
 QG
x-axis
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Depletion
• Ideal MOS capacitor under depletion bias conditions:
VG
EC

Ei
W E FS
EV
p-type SC qVG
E FM W
(x )

QG Qs   qN AW
d ox d ox  W Energy
x
-qNA
x-axis
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Inversion
• Ideal MOS capacitor under inversion bias conditions:
VG Accumulation of
minority electrons EC

W Ei
E FS
EV
p-type SC
electrons qVG
(x )
Wf
E FM
QG Qs  Q N  qN AW f
d ox d ox  W f Energy
x
-qNA
QN x-axis
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Terminology

EC (a) Bulk potential:

q( x) q F  Ei (bulk )  E FS
Ei
q F k BT  N A 
E FS p-type SC:  F  ln    0
q s q  ni 
EV
k BT  N D 
n-type SC:  F   ln   0
q  ni 
Wf
(b) Potential:
(x) q( x )  Ei (bulk )  Ei ( x )

s (c) Surface potential:

q s  Ei (bulk )  Ei (0)
x
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Regions of operation

• Regions of operation for MOS capacitor with p-type SC:

(a) accumulation:  s  0
(b) depletion: 0   s  2 F

(c) inversion:  s  2 F

• The condition s=2 F is called onset of inversion:

 E FS  Ei (0)   q F  
n s  ni exp    ni exp   n  p (bulk )
 k BT   k BT   s

  2
 Ei (0)  E FS   q F   ns p s  ni
p s  ni exp    ni exp  
 k BT   k BT  

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Fields and dielectrics

Tangential components Normal components

Ft1 Fn1
k1 0 k1 0
k2 0 k2 0 Fn 2
Ft 2
Dn1  Dn 2
Ft1  Ft 2
k1 0 Fn1  k 2 0 Fn 2

• Electric field profile for a F (x )

MOS capacitor with p- Fox  3Fsc
type SC under depletion Fox

condition: Fsc
x
d ox d ox  W f

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2. MOS Capacitor Electrostatics

• The potential distribution (profile) in the semiconductor

side of a MOS capacitor is described with the 1D Poisson
equation: d 2 ( x )
2

dx k s 0
where the space charge density is given by:
( x)  q p  n  N D  N A 
  

• The 1D Poisson equation can be solved using one of the

following approaches:
(1) Delta-depletion approximation
(2) Exact analytical model
(3) Using numerical solution techniques

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online simulations and more Approximation
Accumulation:
( x ) • Accumulation charge is replaced
QS with a delta-charge positioned right
 d ox at the semiconductor interface.
x • The electric field and the electro-
0
static potential are:
 QG F ( x )  ( x )  0 for x  0
Inversion:
( x ) • The charge associated with the
minority carriers resides in an
QG Q S  Q N  qN AW f extremely narrow region at the
0 Wf SC/oxide interface.
x • To first order we can assume that:
-qNA
 s  2 F for VG  Vth
QN

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Depletion
( x ) • The charge density is given by:
QG Q s   qN AW ( x )   qN A
0 W • The boundary conditions for the 1D
 d ox x Poisson equation are:
-qNA (W )  F (W )  0, (0)   s
• Final expressions for the electric
( x )
field, electrostatic potential and the
width of the depletion region:
VG VG   s  Vox qN A
F ( x)  W  x 
k s 0
qN A
s ( x )  W  x 2
2k s  0
x 2k s  0 s
W
qN A
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Depletion, Cont’d
• The surface potential is an internal parameter. We therefore
need to relate s to the gate voltage VG using:
VG  Vox   s  Fox d ox   s
where:
ks k s qN AW qN AW
Fox  Fs  
kox kox k s  0 kox  0
• Final expression for the VG-s relationship:
1 kox 0
VG   s  2 qN Ak s  0 s , where Cox 
Cox d ox

• Threshold voltage definition:

Vth  VG for which  s  2 F
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Depletion, Cont’d

• Graphical representation of the VG-s relationship:

VG Delta-depletion • Surface potential varies rapidly

approximation with VG when the device is
depletion biased. Gate voltage
is divided proportionally
Exact
between the semiconductor and
Vth solution the oxide.
• When the semiconductor is
s accumulated or inverted, it
 s  2 F takes large VG to produce small
change in s. Changes in the
applied bias are almost all
dropped across the oxide.

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B. Exact Analytical Model

• To solve for the electrostatic potential and the electric field

profile under arbitrary bias conditions, one needs to go
beyond the delta-depletion approximation and use the exact
expression for the charge density (x) in the 1D Poisson
equation:
( x )  q  p  n  N D  N A 
 q p po e  / VT  n po e / VT  N D  N A
 
• Analytical tricks that we need to use to get to the answer:
2
(1) d  d  d  d  d  d udu d
2
      , u   F ( x)
dx dx  dx  d  dx  dx d dx
(2) ( x)  0 in the semiconductor bulk, where =0.

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Exact Analytical Model, Cont’d
• Integrating the 1D Poisson equation from the bulk up to
some point at a distance x from the SC/oxide interface
(at which point the potential is ) we get:

2 2qp poVT    / VT   n po   / VT  
F ()   e   1  e   1
k s  0  VT  p po  VT 
  
f 2 ( )
• Now, introducing the extrinsic Debye length LD , we can
write:
k s  0VT 2VT
LD   F ()   f ()
qp po LD

(+) sign is for positive 

(-) sign is for negative 
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Exact Analytical Model, Cont’d
• At the SC/oxide interface we have =s, which leads to the
following results for:
(a) electric field: Fs  F ( s )   2VT f ( s ) / LD
(b) total sheet-charge density:
Qs   k s  0 Fs
2k s  0VT    / V
s T
 s  n po   s / VT  s  
  e   1  e   1 
LD  VT  p po  VT 

- flat-band condition:  s  0  Qs  0
- depletion regime: 0   s  2 F  Qs  0
- inversion regime:  s  2 F  Qs   exp s / 2VT 
- accumulation regime:  s  0  Qs  exp  s / 2VT 
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Exact Analytical Model, Cont’d
• The corresponding gate voltage equals to:
ks
VG   s  Vox  s  Fs d ox
kox
• Simulation results for NA=1016 cm-3 and dox=4 nm:

Surface potential 2 10
12
Sheet-charge density
2.5

12
2 1.5 10
 F  0.35 V
12
1.5 1 10 accumulation
VG  VTH  0.7 V
11
1 5 10

|Q /q| [cm ]
-2
[V]

0.5 0
G

Delta
V

s
11
0 approximation -5 10

12
depletion
-0.5 -1 10
inversion
-1
2 F -1.5 10
12

12
-1.5 -2 10
-0.4 -0.2 0 0.2 0.4 0.6 0.8 1 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1

 [V] Surface potential  [V]

s s

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online simulations and more Schrodinger-Poisson Solver

• SCHRED location:
http://www.nanohub.org
• Existing SCHRED Features:
 Classical and quantum-mechanical charge description
Fermi-Dirac and Maxwell-Boltzmann Statistics (for classical)
Fermi-Dirac for quantum-mechanical calculation
 Multiple-valley conduction and valence bands
 Metal and poly-silicon gates: SG and DG structures
 Partial ionization of the impurity atoms
 Exchange and correlation corrections to the ground
state energy of the system

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SCHRED Flow-Chart

Read data from

input file

classical quantum

Solve Poisson’s Solve 1D Poisson’s

equation equation

no
Update (x) Solve 1D Schrödinger
Converged? equation
yes
for both, electrons and holes
no
Update (x)
Converged?
yes

Write data
in files

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Classical simulation results
19
5 10
Classical charge distribution
19 18 -3
4 10 N =10 cm
A

n [cm ]
-3
19
3 10

19
2 10
4
Classical charge distribution: 1 10
19
3
18 -3
N =10 cm , d =4 nm
A ox
2 V =1 V 0
E [eV]

G
10 15 20 25 30
1
depth [nm]
c

0 0

-1 Referent level is the

Fermi level (E =0) -2 1018

(x)/q [cm ]
F

-3
-2
0 10 20 30 40 50 60 70 80 -4 10
18 semiconductor charge
depth [nm]
18
-6 10

18
-8 10

-1 1019
0 10 20 30 40 50 60 70 80

Depth [nm]
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nanoHUB.org 3. Ideal MOS Capacitor Capacitance
online simulations and more

• The capacitance per unit area of an MOS capacitor is cal-

culated using: V G
dQG dQs 1
Ctot   
dVG d Vox  s  dVox ds
 
dQs dQs Cox Cs
1 Cox (x)
  QG QS  QN  QB  QP
1/ Cox 1/ Cs 1  Cox / Cs 0 W
x
 dox
where:
(x)
- Cox is the oxide capacitance
VG
- Cs is the SC capacitance VG   s  Vox

s
x
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online simulations and more Capacitance, Cont’d
• In general, the charge in the semiconductor is represented
as a sum of the inversion layer charge density QN, depletion
layer charge density QB and the accumulation layer charge
density QP, which gives:
dQs dQ N dQ B dQ P
Cs       Cinv  Cdepl  Cacc
d s d s d s d s

• The total gate capacitance is, thus, given by:

Cox Cox Cox
Ctot  
1  Cox / Cs Cox
1
Cinv  Cdepl  Cacc
kox0 Cinv Cdepl Cacc
Cox  Semiconductor
dox capacitance Cs

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online simulations and more Capacitance - Accumulation
• Using the analytical model expression for the semiconduc-
tor charge per unit area Qs, we get:
  s / VT n po
1 e 
p po
e / V  1
s T

dQs
Cs    Cso
d s 2 f ( s )
1/ 2
  / V
s T
s n po   s / VT  s 
f (  s )  e  1  e   1
 VT p po  VT 
k s 0
C so   Flat-band capacitance
LD
(A) Accumulation regime:
 s  0  f ( s )  exp  s / 2VT 
  Ctot  Cox
dQ N  0, dQ B  0
The total gate capacitance is approximately equal to the
oxide capacitance.
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Depletion Regime
(B) Depletion regime:
In depletion regime, the inversion charge is negligible when
compared to the depletion charge. Hence:
0   s  2 F  f ( s )   s / VT  Cso k s  0 qN A
  Cs  
dQ N  0, dQ P  0  2 s / VT 2 s

The total capacitance is, thus, given by:

Cox Cox kox0
Ctot   
Cox Cox 2s
1 1 dox  kox0
Cs Cdepl ks0qNA
Important remarks:
 If NA increases, then Ctot increases.
 If dox increases, Ctot decreases.
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Inversion Regime
(C) Inversion regime:
• Most of the charge induced at the
SC-oxide interface comes from the
electron-hole pair generation (via EC
recombination-generation centers).
• The build-up of minority carriers Ei
proceeds at a rate limited by the EFS
process of generation of electron- EV
qVG
hole pairs.
• Hence, depending upon the
frequency of the applied signal and W
the sweep-rate of the gate voltage,
one can measure:
- low-frequency (LF) CV-curves
- high-frequency (HF) CV-curves
- deep-depletion (DD) CV-curves
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online simulations and more Different Conditions
Graphical illustration of the three different cases:

Ctot
Flat-band capacitance
C acc  Cox
LF
A C
FB

Determine Determine NA
dox
B
C HF HF
DD
VG

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Low-Frequency CV-curve
• AC-frequency low and sweep-
QG
rate low to allow for the gene-
ration of the inversion layer 0 W
electrons and their response to x
the applied AC signal. Qs

• Inversion layer and total gate capacitance:

 s  2 F  f ( s )  exp s / 2VT  n po  / 2V
  C s  Cinv  C so e s T
dQ P  0  2 p po
Cox Cox
Ctot    Cox
1  Cox / Cs 1  Cox / Cinv

The total gate capacitance is approximately equal to the

oxide capacitance.
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High-Frequency CV-Curve
• AC-frequency high, which pre-
QG
vents the response of the mino-
rity carriers. The sweep-rate is 0 Wf
low, thus allowing for the gene- x
ration of the inversion layer Qs
electrons.

• Depletion layer and total gate capacitance:

 s  2 F  f ( s )  2 F / VT  k s  0 qN A
  Cs  Cdepl 
dQN  0, dQP  0 2( 2 F )
Cox Cox
Ctot    const.
1  Cox / Cdepl 2(2F )
1  Cox
ks0qNA
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Deep-Depletion CV-Curve
• AC-frequency high, which pre-
QG
vents the response of the mino-
rity carriers. The sweep-rate is 0 W
also high, thus preventing the x
generation of the inversion layer Qs
electrons.

• Depletion layer and total gate capacitance:

f ( s )   s / VT  k s  0 qN A
  C s  Cdepl 
dQ N  0, dQ P  0  2 s
Cox Cox
Ctot  
Cox 2s
1 1 Cox
Cdepl ks0qNA
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What is Low Frequency?

• The SCR generation current density equals to:

J SCR  qniW /  g
• While JSCR flows in the semiconductor, the current flowing through the
oxide is:
J D  Cox dV / dt
• For the inversion charge to be able to respond, we must have that the
SCR current must be able to supply the required displacement current,
i.e.
qniW
Cox dV / dt  qniW /  g  dV / dt 
Cox  g
Example: dox=100 nm, W=1 m, Cox=3.4510-8 F/cm2 :
g=10 s, dV/dt  0.65 V/s, feff=45 Hz (not a severe constraint)
g=1 ms, dV/dt  6.5 mV/s, feff=0.4 Hz (severe constraint)

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SCHRED Capabilities

- Capable of modeling MOS capacitors and Dual-Gate

structures
- SCHRED is able to calculate separately the inversion
layer capacitance Cinv and the depletion layer capaci-
tance Cdepl
- SCHRED also gives as an output the LF gate capacitance
- With simple post-processing, one can also calculate the
HF capacitance, using:

Cox Cox
Ctot  
Cox Cox
1 1
Cs Cdepl

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SCHRED Results
• Comparison of the simulation results obtained by using
SCHRED and the analytical model results. The MOS capa-
citors have NA=1016 cm-3 (NA=1018 cm-3) and dox=4 nm.
Low-frequency
Low-frequencyCV-curves
CV-curves
1 1

SCHRED SCHRED
analytical model Analytical model
0.8 0.8
16 -3

Capacitance [F/cm ]
N =10 cm
Capacitance [F/cm ]

2
2

A
t =4 nm
ox
0.6 0.6

0.4 0.4

18 -3
N =10 cm
0.2 0.2 A
t =4 nm
ox

0 0
-1 -0.5 0 0.5 1 1.5 2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5

V [V] Gate voltage [V]

G

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nanoHUB.org 4. Deviations from the
online simulations and more Ideal Model

There are several factors that lead to deviation of the

measured CV-curves from what the ideal model predictions
are:
• Work-function difference
• Oxide charges (interface-trap, fixed-oxide, oxide-trap
and mobile oxide charges)
• Depletion of the poly-silicon gates
• Quantum-mechanical space-quantization effects

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A. Workfunction Difference

Ideal MOS capacitor with Real MOS capacitor with

a p-type semiconductor a p-type semiconductor

  VFB   SC   M
 SC SC

M EC  SC
EC
Ei
q F M
E FM E FS Ei
EV E FM E FS
EV

W
Eg
 M   sc   q F
2

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nanoHUB.org Workfunction Difference,
online simulations and more Cont’d
• The flat-band voltage VFB equals the required gate voltage
to achieve flat-band conditions.
• The workfunction difference modifies the relationship
between the surface potential and the applied bias. This
gives rise to threshold voltage shift between the ideal and
real CV-curves:
' 1 1
VG  VG  VG   MS   M   SC 
q q

Voltage applied to real Voltage applied to ideal

MOS capacitor MOS capacitor

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Simulation Example
• Influence on the LF CV-curves:
1

Ideal MOS capacitor

non-ideal MOS capacitor

0.8
Capacitance [F/cm ]
2

0.6

0.4
VG CFB N =10
A
16
cm
-3

t = 4 nm
ox
0.2

0
-1.5 -1 -0.5 0 0.5 1 1.5 2

Gate voltage [V]

• Same effect is also observed on the HF and the DD CV-

curves.
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B. Oxide Charges

• The charges that exist in a realistic MOS structure can be

classified into four different categories:

 +
(1) Mobile ionic charges + Na K
(2) Oxide-trapped charges +- +- +- +- +- +-
(3) Fixed oxide charges
+ + + +
(4) Interface-trap charges

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Oxide Charges, Cont’d
• Mobile oxide charges: Due to ionic impurities such as Na,
K, etc.
• Oxide-trapped charge: May be positive or negative and is
due to holes or electrons trapped in the bulk of the oxide.
• Fixed oxide charges: Due to structural defects (ionized
silicon) in the oxide layer.
• Interface-trapped charges: Positive or negative charges due
to:
 structural, oxidation induced defects
 metal impurities
 other defects due to bond-breaking processes
Unlike other oxide charges, interface-trapped charge is in
electrical communication with the underlying silicon and
can be charged and discharged.
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Oxide Charges, Cont’d
• The expression for the voltage drop across the oxide layer
Vox in the presence of a non-zero charge distribution (x) is
found from the solution of the 1D Poisson equation, using
the boundary conditions: ox(0)=0 and ox(dox)=Vox .
• The final result of this calculation is given below:
d ox
 xox ( x)dx
Qox 1 0
Vox  d ox Fox (d ox )   ,  d ox
Cox d ox
 ox ( x) dx
0
• Special cases:
 uniform charge distribution: =1/2
 Charges at the SC/oxide interface: =1
 Charges at the metal/oxide interface: =0
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Oxide Charges, Cont’d
• The threshold voltage shift due to workfunction difference
and charges in the oxide is given by:

Oxide charges Work function

difference
Qox 1
VG  VG  VG'     MS  VFB
Cox q
Flat-band
voltage
Voltage applied to real
MOS capacitor with Voltage applied to ideal
oxide charges MOS capacitor

• Important note: All the charges (mobile ion charges, fixed

oxide charges, oxide trapped charges) except the interface-
trap charges lead to rigid shift of the CV curve.
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Interface-Trapped Charges
• More information on interface-trapped charges:
 Most of the interface-trapped charges can be neutralized
by low-temperature hydrogen annealing.
 The interface trap density is given by:

Dit

1 dQit  # of charges  <111>

Dit   2 
q dE  cm eV  <100>

0 Eg
 Interface trap charges can be:
- acceptor-like (above the intrinsic level)
- donor-like (below the intrinsic level)
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online simulations and more Charges, Cont’d
 Use simplified model that all of the states below the Fermi
level are full and all of the states above the Fermi level are
empty.

Depletion: Accumulation:
EC

Ei EC
E FS
EV Ei
E FS
EV

The excess negative charges The excess positive charges

lead to positive shift. lead to negative shift.
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 Modification of the HF-CV curve due to interface-trapped
charges.
Gate
C tot
Cox Cox

Interface-traps close
Interface-traps close to conduction band.
to valence band.

Cinv Cdepl Cacc Cit

Interface-traps
close to mid-gap. CHF
VG

Contribution from the charging and

discharging of the interface traps.
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online simulations and more Poly-Silicon Gates
In real MOS capacitors, the gate is usually made of heavily-doped poly-
silicon. Even though the doping of the poly-silicon gate is large, there
is always some finite depletion region, which gives rise to poly-gate ca-
pacitance Cpoly that degrades Ctot .
Gate
3
Poly-gate
2
C poly
depletion
E [eV]

1 Cox
0 18 -3
c

N = 10 cm
A

-1 N = 5x10
19
cm
-3
D
t = 1.5 nm
Cinv Cdepl Cacc Cit
-2 ox

30 40 50 60 70 80
depth [nm] Substrate

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SCHRED Simulation Results
• Simulation results obtained with SCHRED. They clearly
show the role of poly-gate depletion on Ctot .

30 2.5
T = 300 K 19
ND=5x10 cm
-3
Classical calculation:
25 18
NA=10 cm
-3
ND=8x1019 cm-3 2 N =1018 cm-3

[F/cm ]
[F/cm ]
2

2
tox=1.5 nm A
ND=1x1020 cm-3
20 20 -3 t = 1.5 nm
ND=2x10 cm 1.5 ox

15
Al gate
1 19 -3
poly (N =5x10 cm )
poly

10

tot
D 19 -3
poly (N =8x10 cm )
C

C
D
5 0.5 20 -3
poly (N =1x10 cm )
D
20 -3
poly (N =2x10 cm )
D
0 0
-0.5 0 0.5 1 1.5 2
-0.5 0 0.5 1 1.5 2
V [V] VG [V]
G

Important remark:
• The poly-gate depletion introduces gate-voltage dependence on the
total gate capacitance in strong inversion conditions for MOS capaci-
tors on p-type substrates.
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online simulations and more Charge Description
• 1D Poisson equation:
  1  


z  ( z ) z 
  eN 
D ( z )  N 
A ( z )  p ( z )  n( z ) 

 
EF • 1D Schrödinger equation:

 2   1   
 
 i

  V ( z )   ij ( z )  Eij  ij ( z )
 2 z  m ( z ) z  
VG>0 z-axis [100]
(depth) • Electron density:
n( z )   N ij  ij2 ( z )
i, j

4-band m||i k BT   EF  Eij 

N ij  ln 1  exp 
 2   k BT 

2-band :
2-band :
mm=m =0.916m , m =m =0.196m
=ml l=0.916m00, m||||=mt t=0.196m00
4-band:
2-band 4-band: 1/2
mm=m =0.196m , m = (m m ) 1/2
=mt=0.196m0, m||= (ml mt)
t 0 || l t

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SCHRED Simulation Results
• Simulation results obtained with SCHRED. They clearly
show the role of both poly-gate depletion and quantum-me-
chanical space-quantization effect.
2x1020 1.0
VG= 2.5 V 25 SCNP QMNP
20
20 0.8 C
1.5x10 ox
zav [Å]

[F/cm ]
15 QM
n(z) [cm-3]

2
SC
10
0.6
1x1020 5 SCWP
QMWP
SC 0 11 12 13

tot
10 10 10
QM -2 0.4
N [cm ]

C
19
5 x0 s
1 1 1 1
  
0.2 Ctot C poly Cox Cinv
0
0 5 10 15 20 25 30 35 40 -0.5 0.0 0.5 1.0 1.5 2.0 2.5

Distance from the SiO /Si interface [Å] V [V]

G
2

Theclassical
The classicalcharge
chargedensity
densitypeaks
peaksright
right
atatthe SC/oxide interface.
the SC/oxide interface. C reduces Ctot by about 10%
inv reduces Ctot by about 10%
Cinv
Thequantum-mechanically
The quantum-mechanicallycalculated
calculated
charge
charge density peaks at a finitedistance
density peaks at a finite distance Cpoly++CCinv reduce
C
poly reduceCCtot by
inv byabout
about20%
20%
tot
from
from the SC/oxide interface, whichleads
the SC/oxide interface, which leads
totolarger average displacement
larger average displacement of of Withpoly-depletion
With poly-depletionCCtottothas
haspronoun-
pronoun-
electrons ced gate-voltage dependence
electronsfrom
fromthat
thatinterface.
interface. ced gate-voltage dependence

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Technology Trends
• More simulation results on the degradation of the total gate
capacitance Ctot (low-frequency CV-curve) in strong inver-
sion conditions.
1
0.9
0.8
T=300 K, N A=1018 cm-3
ox

0.7
C /C

classical M-B, metal gates

0.6 classical F-D, metal gates
tot

0.5 quantum, metal gates

19 -3
quantum, poly-gates N =6x10 cm
0.4 D
20 -3
quantum, poly-gates N =10 cm
D
0.3 quantum, poly-gates N =2x10
20
cm
-3
D
0.2
1 2 3 4 5 6 7 8 9 10
Oxide thickness t [nm]
ox
Degradation
Degradationofofthe
theTotal
TotalGate
GateCapacitance
CapacitanceCCtot
tot
for Different Device Technologies
for Different Device Technologies
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