Encoder
Encoder
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Contents
1. What is an encoder?
2. How is an encoder different from a multiplexer?
3. How to design a 4:2 Encoder?
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10/17/21, 4:58 PM Priority Encoders, Encoders and Decoders - Simple explanation & designing
What is an encoder?
An encoder is a combinational logic circuit that can be used to
convert 2^n lines of digital input into n bits of coded binary
output. However, in a simple encoder, only one of the inputs is
considered to be high out of all the 2^n inputs. In simple terms,
an encoder takes in 2^n binary inputs, one at a time, and codes
them into n bits of one output code.
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10/17/21, 4:58 PM Priority Encoders, Encoders and Decoders - Simple explanation & designing
The first input line has a physical address of 1. The first output is
00 (binary) = 0 (decimal). 2^0 = 1, which is the physical address
of the first input line. The combination of all the first inputs is
0001 (=1 in decimal).
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
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0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1
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10/17/21, 4:58 PM Priority Encoders, Encoders and Decoders - Simple explanation & designing
Y0 = G + E + C + A
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Y1 = F + E + B + A
Y2 = A + B + C + D
A is high when I2 and I3 are high. Regardless of what the lower NOR universal gates
bits are. So this means that A is one for Half Adder, Full Adder, Half
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Subtractor & Full Subtractor
A =1
Comparator – Designing 1-bit, 2-
for 01xx, which when we expand becomes 0100, 0101, 0110, bit and 4-bit comparators using
logic gates
0111. Thus A is high for all four of these values.
Multiplier – Designing of 2-bit
for 1xxx, which when we expand becomes 1000, 1001, 1010, and 3-bit binary multiplier circuits
1011, 1100, 1101, 1110, 1111. Thus A is high for all eight of 4-bit parallel adder and 4-bit
parallel subtractor – designing &
these values too.
logic diagram
Plotting the K-map for these values, we get for output A Carry Look-Ahead Adder –
Working, Circuit and Truth Table
A = I2 + I3
and for B
B = I3 + I1I2′
From the above equations for A and B, we get the following logic
circuit for a 4:2 priority encoder.
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0 0 0 0 0 1
0 1 0 0 1 0
1 0 0 1 0 0
1 1 1 0 0 0
Y0 = A’B’
Y1 = A’B
Similarly,
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Y2 = AB’
and
Y3 = AB
2:4 Decoder
0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 1 1 0 0 0 0 1 0 0
1 0 0 0 0 0 1 0 0 0
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1 0 1 0 0 1 0 0 0 0
1 1 1 1 0 0 0 0 0 0
Y0 = A’B’C’
Y1 = A’B’C
Y2 = A’BC’
Y3 = A’BC
Y4 = AB’C’
Y5 = AB’C
Y6 = ABC’
Y7 = ABC
3:8 Decoder
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However, one of the pins is an enable pin. And both the 3:8
decoders cannot be active at the same time. Hence, the enable
pin to the second decoder is connected with an inverter. So at a
time, only one of the decoders is working.
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Umair Hussaini
Umair has a Bachelor’s Degree in Electronics and Telecommunication Engineering. He
also holds a Post-Graduate Diploma in Embedded System Design from the Centre of
Development of Advanced Computing (Pune, India). Currently, Umair is pursuing his
MS in Electronics Engineering from the University of Hertfordshire (Hatfield, UK).
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10/17/21, 4:58 PM Priority Encoders, Encoders and Decoders - Simple explanation & designing
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