4

5
6
74LS138

G1
G2A
G2B
Y0
Y1
Y2
15
14

13
12
5
Y3
11
1
2
A
B
Y4
Y5
Y6
10
9
COMBINATIONAL
3
C
Y7 7
LOGIC DESIGN
PRINCIPLES

E X E R C I S E S O L U T I O N S
5.4 READY′ is an expression, with ′ being a unary operator. Use a name like READY_L or /READY instead.
5.8 Both LOW-to-HIGH and HIGH -to-LOW transitions cause positive transitions on the outputs of three gates (every
second gate), and negative transitions on the other three. Thus, the total delay in either case is
t p = 3t pLH(LS00) + 3t pHL(LS00)
= 3 ⋅ 15 + 3 ⋅ 15
= 90 ns
Since t pLH and t pHL for a 74LS00 are identical, the same result is obtained using a single worst-case delay of
15 ns.
5.12 The smallest typical delay through one ’LS86 for any set of conditions is 10 ns. Use the rule of thumb, “mini-
mum equals one-fourth to one-third of typical,” we estimate 3 ns as the minimum delay through one gate.
Therefore, the minimum delay through the four gates is estimated at 12 ns.
The above estimate is conservative, as it does not take into account the actual transitions in the conditions
shown. For a LOW-to-HIGH input transition, the four gates have typical delays of 13, 10, 10, and 20 ns, a total
of 53 ns, so the minimum is estimated at one-fourth of this or 13 ns. For a HIGH -to-LOW input transition, the
four gates have typical delays of 20, 12, 12, and 13 ns, a total of 57 ns, so the minimum is estimated at 14 ns.
5.15 A decoder with active-low outputs ought to be faster, considering that this decoder structure can be imple-
mented directly with inverting gates (which are faster than noninverting) as shown in Figures 5–35 and 5–37.
5.16 The worst-case ’138 output will have a transition in the same direction as the worst-case ’139 output, so we use
tpHL numbers for both, which is the worst combination. The delay through the ’139 is 38 ns, and from the

5–1
5–2 DIGITAL CIRCUITS

active-low enable input of the ’138 is 32 ns, for a total delay of 70 ns. Using “worst-case” numbers for the parts
and ignoring the structure of the circuit, an overly pessimistic result of 79 ns is obtained.
We can also work the problem with 74HCT parts. Worst-case delay through the ’139 is 43 ns, and from the
active-low enable input of the ’138 is 42 ns, for a total delay of 85 ns. Ignoring the structure of the circuit, an
overly pessimistic result of 88 ns is obtained.
We can also work the problem with 74FCT parts. Worst-case delay through the ’139 is 9 ns, and from the
active-low enable input of the ’138 is 8 ns, for a total delay of 17 ns. Ignoring the structure of the circuit, a
slightly pessimistic result of 18 ns is obtained.
Finally, we can work the problem with 74AHCT parts. Worst-case delay through the ’139 is 10.5 ns, and from
the active-low enable input of the ’138 is 12 ns, for a total delay of 22.5 ns. Ignoring the structure of the circuit,
a slightly pessimistic result of 23.5 ns is obtained.

5.19
(a) 74LS138 (b) 74LS138
+5 V +5 V
R R 74LS10
Y0 15
Y0 15 1
6 6
G1 14 G1 14 2 12
F
4 Y1 74LS10 4 Y1 13
G2A 13 1 G2A 13
5 Y2 5 Y2
G2B 12 2 12 G2B 12 U2
Y3 F Y3
13
11 11
1 Y4 1 Y4
Z A 10 U2 C A 10
2 Y5 2 Y5
Y B 9 B B 9
3 Y6 3 Y6
X C 7 A C 7
Y7 Y7

U1 U1

5.21 Both halves of the ’139 are enabled simultaneously when EN_L is asserted. Therefore, two three-state drivers
will be enabled to drive SDATA at the same time. Perhaps the designer forgot to put an extra inverter on the
signal going to 1G or 2G, which would ensure that exactly one source drives SDATA at all times.
5.22 The total delay is the sum of the decoding delay through the 74LS139, enabling delay of a 74LS151, and delay
through a 74LS20: 38 + 30 + 15 = 83 ns .
5.25 The worst-case delay is the sum of the delays through an ’LS280, select-to-output through an ’LS138, and
through an ’LS86: 50 + 41 + 30 = 121 ns .
5.30 The worst-case delay is the sum of four numbers:
• In U1, the worst-case delay from any input to C4 (22 ns).
• In U2, the worst-case delay from C0 to C4 (22 ns).
• In U3, the worst-case delay from C0 to C4 (22 ns).
• In U4, the worst-case delay from C0 to any sum output (24 ns).
Thus, the total worst-case delay is 90 ns.
5.35 With the stated input combination, Y5_L is LOW and the other outputs are HIGH . We have the following cases:
(a) Negating G2A_L or G2B_L causes Y5_L to go HIGH within 18 ns.
(b) Negating G1 causes Y5_L to go HIGH within 26 ns.
(c) Changing A or C causes Y5_L to go HIGH within 27 ns (the change propagates through 3 levels of logic
internally), and causes Y4_L or Y1_L respectively to go LOW within 41 ns (2 levels).
(d) Changing B causes Y5_L to go HIGH within 20 ns (2 levels), and causes Y7_L to go LOW within 39 ns (3
levels). The delays in the ’LS138 are very strange—the worst-case t pHL for 3 levels is shorter than for 2 levels!
EXERCISE SOLUTIONS 5–3

5.39
a D b D
DC DC
A + C′
BA 00 01 11 10 BA 00 01 11 10

00 1 d 1 00 1 1 d 1
A′ + B + C + D A′ + B + C′
01 1 d 1 01 1 d 1
A A
11 1 1 d d 11 1 1 d d
B B
10 1 d d 10 1 d d

B B′ + D′
C A + B′ + C′ C
not minimal not minimal

c D
DC
BA 00 01 11 10
C′ + D′
00 1 1 d 1

01 1 1 d 1
A
11 1 1 d d
B
10 1 d d

A + B′ + C C
not minimal
5.46 The inputs are active low and the outputs are active high in this design.
I0_L

I1_L

Y0

I2_L
I3_L

Y1

I4_L
I5_L
I6_L
I7_L
Y2

I8_L
I9_L
I10_L
I11_L
Y3
I12_L
I13_L
I14_L
I15_L
5–4 DIGITAL CIRCUITS

5.47
74x04
1 2
I7
U2

3 4
I6
74x04
U2
5 6 A2
5 6 74x148
I5 U3
5 EI
U2 I7_L 4 I7 9 8 A1
9 8 I6_L 3 6
I4 I6 A2 U3
I5_L 2 7
U2 I5 A1
I4_L 1 9 11 10
I4 A0 A0
11 10 I3_L 13
I3 I3
I2_L U3
12 I2 14
U2 GS
I1_L 11 15 13 12
I1 EO IDLE
13 12 I0_L 10
I2 I0
U3
U2
U1
1 2
I1
U3

3 4
I0
U3
EXERCISE SOLUTIONS 5–5

5.54 An internal logic diagram for the multiplexer is shown below.

(23)
1D0

(1)
1D1 (2)
1Y

(2)
1D2

(3)
2D0

(4)
2D1 (21)
2Y

(5)
2D2

(6)
3D0

(7)
3D1 (20)
3Y

(8)
3D2

(9)
4D0

(10)
4D1 (19)
4Y

(11)
4D2

(18)
5D0

(17)
5D1 (15)
5Y

(16)
5D2

(13)
S0

(14)
S1
5–6 DIGITAL CIRCUITS

A truth table and pin assignment for the mux are shown below.
74LS998
Inputs Outputs 13
S0
S1 S0 1Y 2Y 3Y 4Y 5Y 14
S1
23
0 0 1D0 2D0 3D0 4D0 5D0 1D0
1
1D1
0 1 1D1 2D1 3D1 4D1 5D1 2
1D2 1Y 22
3
1 0 1D2 2D2 3D2 4D2 5D2 2D0
4
2D1 2Y 21
1 1 0 0 0 0 0 5
2D2
6
3D0 3Y 20
7
3D1
8
3D2 4Y 19
9
4D0
10
4D1 5Y 15
11
4D2
18
5D0
17
5D1
16
5D2

The mux can be built using a single PLD, a PAL20L8 or GAL20V8; the pin assignment shown above is based
on the PLD. The corresponding ABEL program, MUX3BY5.ABL, is shown below.

module Mux_3x5
title '5-Bit, 3-Input Multiplexer
J. Wakerly, Marquette University'
MUX3BY5 device 'P20L8';

" Input pins

I1D0, I1D1, I1D2 pin 23, 1, 2;
I2D0, I2D1, I2D2 pin 3, 4, 5;
I3D0, I3D1, I3D2 pin 6, 7, 8;
I4D0, I4D1, I4D2 pin 9, 10, 11;
I5D0, I5D1, I5D2 pin 18, 17, 16;
S0, S1 pin 13, 14;
" Output pins
Y1, Y2, Y3, Y4, Y5 pin 22, 21, 20, 19, 15;

" Set definitions

BUS0 = [I1D0,I2D0,I3D0,I4D0,I5D0];
BUS1 = [I1D1,I2D1,I3D1,I4D1,I5D1];
BUS2 = [I1D2,I2D2,I3D2,I4D2,I5D2];
OUT = [Y1, Y2, Y3, Y4, Y5 ];

" Constants
SEL0 = ([S1,S0]==[0,0]);
SEL1 = ([S1,S0]==[0,1]);
SEL2 = ([S1,S0]==[1,0]);
IDLE = ([S1,S0]==[1,1]);

equations

OUT = SEL0 & BUS0 # SEL1 & BUS1 # SEL2 & BUS2 # IDLE & 0;

end Mux_3x5
EXERCISE SOLUTIONS 5–7

5.55 This is the actual circuit of a MUX21H 2-input multiplexer cell in LSI Logic’s LCA 10000 series of CMOS
gate arrays. When S is 0, the output equals A; when S is 1, the output equals B.
5.60
74x151
7
EN
11
S0 A
10
S1 B
9
S2 C
4 5
Ai D0 Y Fi
3 6
Bi D1 Y
2
D2
1
Ci D3
15
D4
14
Di D5
13
D6
12
D7

U1 – U18

5.67 The ’08 has the same pinout as the ’00, but its outputs are the opposite polarity. The change in level at pin 3 of
U1 is equivalent to a change at pin 4 of U2 (the input of an XOR tree), which is equivalent in turn to a change at
pin 6 of U2 (the parity-generator output). Thus, the circuit simply generated and checked odd parity instead of
even.
The change in level at pin 6 of U1 changed the active level of the ERROR signal.
5.69 This problem is answered in Section 5.9.3 of the text, which makes it a silly question.
5–8 DIGITAL CIRCUITS

5.75
P
Q
74x682 74x682
P0 2
P0
P16 2
P0
Q0 3
Q0
Q16 3
Q0
P1 4
P1
P17 4
P1
Q1 5
Q1
Q17 5
Q1
P2 6
P2
P18 6
P2
Q2 7
Q2
Q18 7
19 EQ0_L Q2 19 /EQ2
P3 8 P EQ Q P19 8 P EQ Q
P3 P3
Q3 9
Q3
Q19 9
Q3
P4 11
P4
P20 11
P4
Q4 12
Q4 GT0_L
Q20 12
Q4 /GT2
1 1
P5 13 P GT Q P21 13 P GT Q
P5 P5
Q5 14
Q5
Q21 14
Q5
P6 15
P6
P22 15
P6
Q6 16
Q6
Q22 16
Q6
P7 17
P7
P23 17
P7
Q7 18
Q7
Q23 18
Q7
U1 U3

1 74x27
74x682
2 12
P8 PEQQ
2
P0 13
Q8 3 U4
Q0
P9 4
P1 3 74x27
Q9 5
Q1 4 6
P10 6
P2 5
Q10 7 U4
Q2 19 EQ1_L
P11 8 P EQ Q 74x02
P3 74x02 74x27 8
11
Q11 9 2 10
Q3 1 10 8 9 PGTQ
P12 11 3
P4 9
U5
Q12 12 U5 U4
Q4 1 GT1_L
P13 13 P GT Q 74x02
P5
Q13 14 5
Q5 4
P14 15 6
P6
Q14 16 U5
Q6
P15 17
P7
Q15 18
Q7
U2

5.79 The function has 65 inputs, and the worst 65-input function (a 65-input parity circuit) has 2 65 – 1 terms in the
minimal sum-of-products expression. Our answer can’t be any worse than this, but we can do better.
The expression for c 1 has 3 product terms: c 1 = c 0 ⋅ x 0 + c 0 ⋅ y 0 + x 0 ⋅ y 0
The expression for c 2 is c 2 = c 1 ⋅ x 1 + c 1 ⋅ y 1 + x 1 ⋅ y 1
If we substitute our previous expression for c1 in the equation above and “multiply out,” we get a result with
3 + 3 + 1 = 7 product terms. Let us assume that no further reduction is possible.
Continuing in this way, we would find that the expression for c 3 has 7 + 7 + 1 = 15 product terms and, in
general, the expression for c i has 2 i + 1 – 1 product terms.
Thus, the number of terms in a sum-of-products expression for c 32 is no more than 2 33 – 1 , fewer if minimiza-
tion is possible.
EXERCISE SOLUTIONS 5–9

5.80
16-bit group 74S182
MSBs
G3
P3

C3
16-bit group

G2
P2

C2
16-bit group

G1
P1

C1
16-bit group
74LS181 74S182

G G3
CIN
P P3 G GOUT
P POUT

C3
74LS181

G G2
CIN
P P2

C2
74LS181 G G0
P P0
G G1
CIN
P P1

C1
74LS181

G G0
C0 CIN
P P0 C0

LSBs
C0
5–10 DIGITAL CIRCUITS

5.82
74LS00
1
3
74LS138 2 F1
+5V
R 15 U2
6 Y0 74LS00
G1 14 4
4 Y1 6
G2A 13 5 F2
5 Y2
G2B 12 U2
Y3 74LS00
11 12
1 Y4 11
Z A 10 13 F3
2 Y5
Y B 9 U2
3 Y6 74LS00
X C 7 9
Y7 8
10 F4
U1
U2
5.91
S0
74x153

14
S1 A
2
S2 B
1
B[0:3] 1G
B0 6
C[0:3] 1C0
C0 5
D[0:3] 1C1 BCDE0
D0 4 1Y 7
E[0:3] 1C2
E0 3
1C3
15
2G
B1 10
74x157
2C0
C1 11 15
2C1 BCDE1 G
D1 12 2Y 9 1
2C2 S T[0:3]
E1 13 A0 2
2C3 1A 4 T0
U1 3 1Y
1B
A1 5
2A
2Y 7
74x153 T1
6
2B
14 A2 11
A 3A
3Y 9
T2
2 10
B 3B
1 A3 14
1G 4A
4Y 12
T3
B2 6 13
1C0 4B
C2 5
1C1 7 BCDE2
D2 4 1Y U3
1C2
E2 3
1C3
15
2G
B3 10
2C0
C3 11
2C1 BCDE3
D3 12 2Y 9
2C2
E3 13
2C3
U2

A[0:3]
5.93 The obvious solution is to use a 74FCT682, which has a maximum delay of 11 ns to its PEQQ output. How-
ever, there are faster parts in Table 5–3. In particular, the 74FCT151 has a delay of only 9 ns from any select
input to Y or Y. To take advantage of this, we use a ’138 to decode the SLOT inputs statically and apply the
resulting eight signals to the data inputs of the ’151. By applying GRANT[2–0] to the select inputs of the ’151,
we obtain the MATCH_L output (as well as an active-high MATCH , if we need it) in only 9 ns!