Chapter 14

Processor Structure and Function

 Processor requirements include

◦ Fetch instruction: The processor reads an
instruction from memory (register, cache, main
memory)
◦ Interpret instruction: The instruction is decoded to
determine what action is required
◦ Fetch data: The execution of an instruction may
require reading data from memory or an I/O
module

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◦ Process data: The execution of an instruction may
require performing some arithmetic or logical
operation on data
◦ Write data: The results of an execution may require
writing data to memory or an I/O module

 In order to do these things the processor

needs to store some data temporarily and
therefore needs a small internal memory.

 Notice that the major components of the

processor are an arithmetic and logic
unit(ALU) and a control unit(CU).
◦ The ALU does the actual computation or processing
of data.
◦ The control unit controls the movement of data and
instructions into and out of the processor and
controls the operation of the ALU.

 In addition, CPU consists of a set of storage

locations, called registers.

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CPU with the system bus
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 ALU operates only on data in the internal

processor memory.

 Thus, data transfer between the various

registers and ALU is needed which is the
responsibility of internal processor bus.

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Internal structure of the CPU
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 The registers in the processor perform two

roles:
◦ User-visible registers: Enable the machine- or
assembly language programmer to minimize
main memory references by optimizing use of
registers.
◦ Control and status registers: Used by the control
unit to control the operation of the processor and
by privileged, operating system programs to
control the execution of programs.

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 A user-visible register is one that may be
referenced by means of the machine
language that the processor executes.

 We can characterize these in the following

categories:
◦ General purpose (data, address)
◦ Data
◦ Address
◦ Condition codes (flags)

 Four registers are essential to instruction

execution:
◦ Program counter (PC): Contains the address of an
instruction to be fetched
◦ Instruction register (IR): Contains the instruction
most recently fetched
◦ Memory address register (MAR): Contains the
address of a location in memory
◦ Memory buffer register (MBR): Contains a word of
data to be written to memory or the word most
recently read

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 Typically, the processor updates the PC after
each instruction fetch so that the PC always
points to the next instruction to be executed.
 A branch or skip instruction will also modify
the contents of the PC.
 The fetched instruction is loaded into an IR,
where the opcode and operand specifiers are
analyzed.
 Data are exchanged with memory using the
MAR and MBR.

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 Many processor designs include a register or

set of registers, often known as the program
status word (PSW), that contain status
information.

 The PSW typically contains condition codes

plus other status information.

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 Common fields or flags include the following:
◦ Sign (sign bit of the last arithmetic operation)
◦ Zero (set when the result is 0)
◦ Carry (set if an operation resulted in a carry)
◦ Equal (set if a logical compare result is equality)
◦ Overflow (used to indicate arithmetic overflow)
◦ Interrupt Enable/Disable (used to enable or disable
interrupts)
◦ Supervisor (used to indicate supervisor or user mode)

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 The Motorola MC68000 (16-bit microprocessor)
partitions its 32-bit registers into eight data
registers and nine address registers.
 Data registers are used primarily for data
manipulation and are also used in addressing as
index registers.
 The width of the registers allows 8-, 16-, and
32-bit data operations, determined by opcode.
 The MC68000 also includes a 32-bit program
counter and a 16-bit status register.

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 The Intel 8086 (16-bit microprocessor) takes a

different approach to register organization.
Every register is special purpose, although
some registers are also usable as general
purpose.
 The 8086 contains four 16-bit data registers.
The data registers can be used as general
purpose in some instructions.
 Three of the four segment registers are used in
to point to the segment of the current
instruction.

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 The Intel 80386-Pentium 4 (32-bit
microprocessors) uses 32-bit registers.
 However, to provide upward compatibility for
programs written on the earlier machine, the
80386 retains the original register organization
embedded in the new organization.
 Given this design constraint, the architects of
the 32-bit processors had limited flexibility in
designing the register organization.

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 An instruction cycle includes the following

stages:
◦ Fetch: Read the next instruction from memory into the
processor.
◦ Execute: Interpret the opcode and perform the
indicated operation.
◦ Interrupt: If interrupts are enabled and an interrupt
has occurred, save the current process state and
service the interrupt.
◦ Indirect: Fetching an indirect address can be
considered as one more instruction stage.

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 Once an instruction is fetched, its operand

specifiers must be identified. Each input
operand in memory is then fetched, and this
process may require indirect addressing.
 Register-based operands need not be fetched.
 Once the opcode is executed, a similar process
may be needed to store the result in main
memory.
 Following execution, an interrupt may be
processed before the next instruction fetch.

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Instruction Cycle State Diagram

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Fetch Cycle
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 During the fetch cycle, an instruction is read
from memory. The PC contains the address of
the next instruction to be fetched. This address
is moved to the MAR and placed on the address
bus.
 The control unit requests a memory read, and
the result is placed on the data bus and copied
into the MBR and then moved to the IR.
 Meanwhile, the PC is incremented by 1,
preparatory for the next fetch.

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Indirect Cycle
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 Once the fetch cycle is over, the control unit
examines the contents of the IR to determine if
it contains an operand specifier using indirect
addressing.
 If so, an indirect cycle is performed.
 The rightmost N bits of the MBR, which contain
the address reference, are transferred to the
MAR.
 Then the control unit requests a memory read,
to get the desired address of the operand into
the MBR.

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 The execute cycle takes many forms; the form

depends on which of the various machine
instructions is in the IR.

 This cycle may involve transferring data among

registers, read or write from memory or I/O,
and/or the invocation of the ALU.

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Interrupt Cycle
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 The current contents of the PC must be saved

so that the processor can resume normal
activity after the interrupt.
 Thus, the contents of the PC are transferred to
the MBR to be written into memory. The special
memory location reserved for this purpose is
loaded into the MAR from the control unit.
 The PC is loaded with the address of the
interrupt routine. As a result, the next
instruction cycle will begin by fetching the
appropriate instruction.

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 As computer systems evolve, greater
performance can be achieved by taking
advantage of improvements in technology,
such as faster circuitry.
 In addition, organizational enhancements to
the processor can improve performance such
as the use of multiple registers rather than a
single accumulator, and the use of a cache
memory.
 Another organizational approach, which is
quite common, is instruction pipelining.

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To apply this concept

to instruction
execution we must
Similar to the use of recognize that an
an assembly line in a instruction has a
manufacturing plant number of stages

New inputs are

accepted at one end,
previously accepted
inputs appear as
outputs at the other
end

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Two-Stage Instruction Pipeline
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 There are times during the execution of an

instruction when main memory is not being
accessed. This time could be used to fetch the next
instruction in parallel with the execution of the
current one.
 The first stage fetches an instruction and buffers it.
When the second stage is free, the first stage
passes the buffered instruction.
 While the second stage is executing the instruction,
the first stage takes advantage of any unused
memory cycles to fetch and buffer the next
instruction.

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 This is called instruction prefetch or fetch
overlap.

 Note that this approach, which involves

instruction buffering, requires more registers.

 In general, pipelining requires registers to store

data between stages.

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 To gain further speedup, the pipeline must

have more stages.

 Consider the following decomposition of the

instruction processing.
◦ Fetch instruction (FI)
 Read the next expected instruction into a buffer
◦ Decode instruction (DI)
 Determine the opcode and the operand specifiers

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◦ Calculate operands (CO)
 Calculate the effective address of each source operand
◦ Fetch operands (FO)
 Fetch each operand from memory
 Operands in registers need not be fetched
◦ Execute instruction (EI)
 Perform the indicated operation and store the result, if
any, in the specified destination operand location
◦ Write operand (WO)
 Store the result in memory

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 Example: Timing diagram for instruction pipeline operation

with 9 instructions.

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 The diagram assumes that each instruction
goes through all six stages of the pipeline
where each step has equal duration.
 In particular, it is assumed that there are no
memory conflicts.
◦ For example, the FI, FO, and WO stages involve a
memory access. However, the desired value may be
in cache, or the FO or WO stage may be null.
◦ Thus, much of the time, memory conflicts will not
slow down the pipeline.

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 A possible difficulty is the conditional branch

instruction, which can invalidate several
instruction fetches.

 A similar unpredictable event is an interrupt.

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 Example: The effect of a conditional branch on instruction
pipeline operation.

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 Assume that instruction 3 is a conditional

branch to instruction 15.

 Until the instruction is executed, there is no

way of knowing which instruction will come
next.

 The pipeline, in this example, simply loads

the next instruction in sequence (instruction
4) and proceeds.

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 This is not determined until t=7.
 At this point, the pipeline must be cleared of
instructions that are not useful.
 During t=8, instruction 15 enters the
pipeline.
 No instructions complete during time units 9
through 12; this is the performance penalty
incurred because we could not anticipate the
branch.

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 Figure indicates
the logic needed
for pipelining to
account for
branches and
interrupts.

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Alternative Pipeline
Depiction
 Figure shows
same sequence
of events in last
examples, with
time progressing
vertically down
the figure, and
each row
showing the state
of the pipeline at
a given point in
time.

 Instruction
pipelining is a
powerful
technique for
enhancing
performance but
requires careful
design to
achieve optimum
results with
reasonable
complexity.

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 Occur when the pipeline, or some portion of
the pipeline, must stall because conditions do
not permit continued execution.

 Also referred to as a pipeline bubble.

 There are three types of hazards:

◦ Resource
◦ Data
◦ Control

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 A resource hazard occurs when two or more

instructions that are already in the pipeline
need the same resource.

 The result is that the instructions must be

executed in serial rather than parallel for a
portion of the pipeline.

 A resource hazard is sometimes referred to

as a structural hazard.

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 A data hazard occurs when there is a conflict in
the access of an operand location.
 Assume that two instructions in a program are
to be executed in sequence and both access a
particular memory or register operand.
◦ If the two instructions are executed in strict sequence,
no problem occurs.
◦ However, if the instructions are executed in a pipeline,
then it is possible for the operand value to be updated
in such a way as to produce a different result than
would occur with strict sequential execution.
◦ In other words, the program produces an incorrect
result because of the use of pipelining.

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 Control hazard occurs when the pipeline

makes the wrong decision on a branch
prediction and therefore brings instructions
into the pipeline that must subsequently be
discarded.

 Also known as branch hazard.

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