8155 STATIC RAM WITH I/O PORTS AND TIMER

Control Word Format

Status Word
Timer Set Command Word
8255A PROGRAMMABLE PERIPHERAL INTERFACE (PPI)

 8255 is a programmable peripheral interface IC and is a multiport

input/output device and is used to give the CPU access to programmable
parallel I/O.
 This is a general-purpose programmable I/O device, which may be used with
many different microprocessors.
 There are 24 I/O pins, which may be individually programmed in 2 groups
of 12 and used, in 3 major modes of operation.
 The I/O ports can be programmed in a variety of ways as per requirement of
the programmer.
 Compatible with 8085, 8086, 8088.
 Direct bit set-reset capability.
FUNCTIONAL BLOCK DIAGRAM OF 8255 PPI
 The 8255A has 24 I/O pins that can be grouped primarily in two 8-bit
parallel ports: A and B with the remaining eight bits as port C. The eight bits
of port C can be used as individual bits or be grouped in to 4-bit ports:
CUpper (Cu) and CLower (CL). The function of these ports is defined by
writing a control word in the control register.
 Data Bus Buffer: This three-state bi-directional 8-bit buffer is used to
interface the 8255 to the system data bus. Data is transmitted or received by
the buffer upon execution of input or output instructions by the CPU.
Control words and status information are also transferred through the data
bus buffer.
 Read/Write and Control Logic: The function of this block is to manage all
of the internal and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in
turn, issues commands to both of the Control Groups.
 Group A and Group B Controls: The functional configuration of each port
is programmed by the systems software. In essence, the CPU "outputs" a
control word to the 8255. The control word contains information such as
"mode", "bit set", "bit reset", etc., that initializes the functional configuration
of the 8255. Each of the Control blocks (Group A and Group B) accepts
"commands" from the Read/Write Control logic, receives "control words"
from the internal data bus and issues the proper commands to its associated
ports.
 Ports A, B, and C: The 8255 contains three 8-bit ports (A, B, and C). All
can be configured to a wide variety of functional characteristics by the
system software but each has its own special features or "personality" to
further enhance the power and flexibility of the 8255.
Port A One 8-bit data output latch/buffer and one 8-bit data input latch.
Port B One 8-bit data input/output latch/buffer and one 8-bit data input
buffer.
Port C One 8-bit data output latch/buffer and one 8-bit data input buffer
(no latch for input). This port can be divided into two 4-bit ports under
the mode control. Each 4-bit port contains a 4-bit latch and it can be
used for the control signal output and status signal inputs in
conjunction with ports A and B.
PIN DIAGRAM OF 8255 PPI

D0-D7 Data Bus. These are 8-bit bi-directional buses, connected to 8086 data
bus for transferring data.

CS’ Chip Select. A "low" on this input pin enables the communication
between the 8255 and the CPU.

RD’ Read. A "low" on this input pin enables 8255 to send the data or status
Information to the CPU on the data bus. In essence, it allows the CPU
to "read from" the 8255.

WR’ Write. A "low" on this input pin enables the CPU to write data or
control words into the 8255.

A0 -A1 Port Select 0 and Port Select 1. These input signals, in conjunction
with the RD’ and WR’ inputs, control the selection of one of the three
ports or the control word register. They are normally connected to the
least significant bits of the address bus (A0 and A1).

A1 A0 SELECTION
0 0 PORT A
0 1 PORT B
1 0 PORT C
1 1 CONTROL REGISTER

RESET Reset. A "high" on this input initializes the control register to 9BH
and all ports (A, B, C) are set to the input mode.

PA0-PA7 It is the 8-bit bi-directional I/O pins used to send the data to peripheral
or to receive the data from peripheral.
PB0-PB7 Similar to PA
PC0-PC7 This is also 8-bit bidirectional I/O pins. These lines are divided into
two groups.
PC0 to PC3 (Lower Group) and
PC4 to PC7 (Higher group)
MODES OF OPERATION OF 8255 PPI

There are two basic operational modes of 8255:

1. Bit set/reset Mode (BSR Mode).
2. Input/ Output Mode (I/O Mode).
The two modes are selected on the basis of the value present at the D7 bit of the
Control Word Register. When D7 = 1, 8255 operates in I/O mode and when D7 =
0, it operates in the BSR mode.
Bit Set Reset (BSR) mode
The Bit Set/Reset (BSR) mode is applicable to port C only. Each line of port C
(PC0 - PC7) can be set/reset by suitably loading the control word register.
BIT SET-RESET CONTROL WORD FOR 8255 PPI

D7 bit is always 0 for BSR mode.

Bits D6, D5 and D4 are don't care bits.
Bits D3, D2 and D1 are used to select the pin of Port C.
Bit D0 is used to set/reset the selected pin of Port C.
Selection of port C pin is determined as follows:

B3 B2 B1 Bit/pin of port C selected

0 0 0 PC0
0 0 1 PC1
0 1 0 PC2
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7

Input Output mode

This mode is selected when D7 bit of the Control Word Register is 1. There are
three I/O modes:
1. Mode 0 - Simple I/O
2. Mode 1 - Strobed I/O
3. Mode 2 - Strobed Bi-directional I/O
CONTROL WORD I/O MODE FOR 8255 PPI

D0, D1, D3, D4 are assigned for lower port C, port B, upper port C and port A
respectively. When these bits are 1,the corresponding port acts as an input port.
D2 is used for mode selection of Group B (port B and lower port C). When D2 = 0,
mode 0 is selected and when D2 = 1, mode 1 is selected.
D5& D6 are used for mode selection of Group A ( port A and upper port C). The
selection is done as follows:
D6 D5 Mode
0 0 Mode 0
0 1 Mode 1
1 X Mode 2

As it is I/O mode, D7 = 1

Mode 0 - Simple I/O

In this mode, the ports can be used for simple I/O operations without handshaking
signals. Port A, Port B provide simple I/O operation. The two halves of port C can
be either used together as an additional 8-bit port, or they can be used as individual
4-bit ports. Since the two halves of port C are independent, they may be used such
that one half is initialized as an input port while the other half is initialized as an
output port.
The input/output features in mode 0 are as follows:
1. Output ports are latched.
2. Input ports are buffered, not latched.
3. Ports do not have handshake or interrupt capability.
4. With 4 ports, 16 different combinations of I/O are possible.

Mode 0 – Input mode

In the input mode, the 8255 gets data from the external peripheral ports and the
CPU reads the received data via its data bus. The CPU first selects the 8255 chip
by making CS low. Then it selects the desired port using A0 and A1 lines. The
CPU then issues an RD signal to read the data from the external peripheral device
via the system data bus.

Mode 0 - Output mode

In the output mode, the CPU sends data to 8255 via system data bus and then the
external peripheral ports receive this data via 8255 port. CPU first selects the 8255
chip by making CS low. It then selects the desired port using A0 and A1 lines.
CPU then issues a WR signal to write data to the selected port via the system data
bus. This data is then received by the external peripheral device connected to the
selected port.
Mode 1
When we wish to use port A or port B for handshake (strobe) input or output
operation, we initialise that port in mode 1 (port A and port B can be initilalised to
operate in different modes, i.e., for e.g., port A can operate in mode 0 and port B in
mode 1). Some of the pins of port C function as handshake lines. For port B in this
mode (irrespective of whether is acting as an input port or output port), PC0, PC1
and PC2 pins function as handshake lines.
If port A is initialised as mode 1 input port, then, PC3, PC4 and PC5 function as
handshake signals. Pins PC6 and PC7 are available for use as input/output lines.
The mode 1 which supports handshaking has following features:
1. Two ports i.e. port A and B can be used as 8-bit I/O ports.
2. Each port uses three lines of port c as handshake signal and remaining two
signals can be used as I/O ports.
3. Interrupt logic is supported.
4. Input and Output data are latched.

Input Handshaking signals

1. IBF (Input Buffer Full) - It is an output indicating that the input latch contains
information.
2. STB (Strobe Input) - The strobe input loads data into the port latch, which
holds the information until it is input to the microprocessor via the IN
instruction.
3. INTR (Interrupt request) - It is an output that requests an interrupt. The INTR
pin becomes a logic 1 when the STB input returns to a logic 1, and is cleared
when the data are input from the port by the microprocessor.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed via the port PC4(port A) or PC2(port B) bit position.
Output Handshaking signals
1. OBF (Output Buffer Full) - It is an output that goes low whenever data are
output(OUT) to the port A or port B latch. This signal is set to a logic 1
whenever the ACK pulse returns from the external device.
2.ACK (Acknowledge)-It causes the OBF pin to return to a logic 1 level. The
ACK signal is a response from an external device, indicating that it has received
the data from the 82C55 port.
3.INTR (Interrupt request) - It is a signal that often interrupts the microprocessor
when the external device receives the data via the signal. this pin is qualified by
the internal INTE(interrupt enable) bit.
4. INTE (Interrupt enable) - It is neither an input nor an output; it is an internal bit
programmed to enable or disable the INTR pin. The INTE A bit is programmed
using the PC6 bit and INTE B is programmed using the PC2 bit.

Mode 2
Only group A can be initialized in this mode. Port A can be used for bidirectional
handshake data transfer. This means that data can be input or output on the same
eight lines (PA0 - PA7). Pins PC3 - PC7 are used as handshake lines for port A.
The remaining pins of port C (PC0 - PC2) can be used as input/output lines if
group B is initialized in mode 0 or as handshaking for port B if group B is
initialized in mode 1. In this mode, the 8255 may be used to extend the system bus
to a slave microprocessor or to transfer data bytes to and from a floppy disk
controller. Acknowledgement and handshaking signals are provided to maintain
proper data flow and synchronization between the data transmitter and receiver.
Q Write the control word for using 8255 PPI as Port A as input, Port B as output in
Mode 1.
Ans. Control word = 1 0110100 = B4H

Q Write the control words to set and reset PC7.

Ans. BSR control word to set = 0 000 1111 = 0FH
BSR control word to reset = 0 000 1110 = 0EH
8755 EPROM
8279 PROGRAMMABLE KEYBOARD/ DISPLAY INTERFACE (PKDC)
The INTEL 8279 is specially developed for interfacing keyboard and display devices to
8085/8086/8088 microprocessor based system. The important features of 8279 are
• Simultaneous keyboard and display operations.
• Scanned keyboard mode.
• Scanned sensor mode.
• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.
FUNCTIONAL BLOCK DIAGRAM OF 8279 PKDC
The four major sections of 8279 are keyboard, scan, display and CPU interface.
Keyboard section
• The keyboard section consists of eight return lines RL0 – RL7 that can be used to form the
columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The keys are automatically debounced.
• The two operating modes of keyboard section are 2-key lockout and N-key rollover.
• In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is
recognized.
• In the N-key rollover mode simultaneous keys are recognized and their codes are stored in
FIFO.
• The keyboard section also has an 8 x 8 FIFO (First In First Out) RAM.
• The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and
control key are also stored along with key code. The 8279 generate an interrupt signal when
there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is.
• In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO
RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to
interrupt the processor.
Display section
• The display section has eight output lines divided into two groups A0-A3 and B0-B3.
• The output lines can be used either as a single group of eight lines or as two groups of four
lines, in conjunction with the scan lines for a multiplexed display.
• The output lines are connected to the anodes through driver transistor in case of common
cathode 7- segment LEDs.
• The cathodes are connected to scan lines through driver transistors.
• The display can be blanked by BD (low) line.
• The display section consists of 16 x 8 display RAM. The CPU can read from or write into any
location of the display RAM.
Scan section
• The scan section has a scan counter and four scan lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines will be binary count, and so an external decoder
should be used to convert the binary count to decoded output.
• The scan lines are common for keyboard and display.
• The scan lines are used to form the rows of a matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.
CPU interface section
• The CPU interface section takes care of data transfer between 8279 and the processor.
• This section has eight bidirectional data lines DB0 to DB7 for data transfer between 8279 and
CPU.
• It requires two internal address A =0 for selecting data buffer and A = 1 for selecting control
register of8279.
• The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven data transfer with processor.
• The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the
input clock by an internal prescaler.
• The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard
modes.

I/O Control and Data Buffer

This unit controls the flow of data through the microprocessor. It is enabled only when D is low.
Its data buffer interfaces the external bus of the system with the internal bus of the
microprocessor. The pins A0, RD, and WR are used for command, status or data read/write
operations.

Control and Timing Register and Timing Control

This unit contains registers to store the keyboard, display modes, and other operations as
programmed by the CPU. The timing and control unit handles the timings for the operation of
the circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter
provides the binary count that is to be externally decoded to provide the scan lines for the
keyboard and display.
In the decoded scan mode, the counter internally decodes the least significant 2 bits and
provides a decoded 1 out of 4 scan on SL0-SL3.

Return Buffers, Keyboard Debounce, and Control

This unit first scans the key closure row-wise, if found then the keyboard debounce unit
debounces the key entry. In case, the same key is detected, then the code of that key is directly
transferred to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This unit acts as 8-byte first-in-first-out (FIFO) RAM where the key code of every pressed key
is entered into the RAM as per their sequence. The status logic generates an interrupt request
after each FIFO read operation till the FIFO gets empty.
In the scanned sensor matrix mode, this unit acts as sensor RAM where its each row is loaded
with the status of their corresponding row of sensors into the matrix. When the sensor changes
its state, the IRQ line changes to high and interrupts the CPU.

Display Address Registers and Display RAM

This unit consists of display address registers which holds the addresses of the word currently
read/written by the CPU to/from the display RAM.
PIN DIAGRAM OF 8279 PKDC
Data Bus Lines, DB0 - DB7 These are 8 bidirectional data bus lines used to transfer the
data to/from the CPU.

CLK The clock input is used to generate internal timings

required by the microprocessor.

RESET As the name suggests this pin is used to reset the

microprocessor.

CS Chip Select When this pin is set to low, it allows read/write operations,
else this pin should be set to high.

A0 This pin indicates the transfer of command/status

information. When it is low, it indicates the transfer of data.

RD, WR This Read/Write pin enables the data buffer to send/receive

data over the data bus.

IRQ This interrupt output line goes high when there is data in
the FIFO sensor RAM. The interrupt line goes low with
each FIFO RAM read operation. However, if the FIFO
RAM further contains any key-code entry to be read by the
CPU, this pin again goes high to generate an interrupt to the
CPU.

Vss, Vcc These are the ground and power supply lines of the
microprocessor.

SL0 − SL3 These are the scan lines used to scan the keyboard matrix
and display the digits. These lines can be programmed as
encoded or decoded, using the mode control register.

RL0 − RL7 These are the Return Lines which are connected to one
terminal of keys, while the other terminal of the keys is
connected to the decoded scan lines. These lines are set to 0
when any key is pressed.

SHIFT The Shift input line status is stored along with every key
code in FIFO in the scanned keyboard mode. Till it is
pulled low with a key closure, it is pulled up internally to
keep it high

CNTL/STB CONTROL/STROBED I/P Mode In the keyboard mode,

this line is used as a control input and stored in FIFO on a
key closure. The line is a strobe line that enters the data
into FIFO RAM, in the strobed input mode. It has an
internal pull up. The line is pulled down with a key closure.

BD It stands for blank display. It is used to blank the display

during digit switching.

OUTA0 – OUTA3 These are the output ports for two 16x4 or one 16x8
OUTB0 – OUTB3 internal display refresh registers. The data from these lines
is synchronized with the scan lines to scan the display and
the keyboard.

OPERATIONAL MODES OF 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

This mode deals with the input given by the keyboard and this mode is further classified into 3
modes.
 Scanned Keyboard Mode − In this mode, the key matrix can be interfaced using either
encoded or decoded scans. In the encoded scan, an 8×8 keyboard or in the decoded scan,
a 4×8 keyboard can be interfaced. The code of key pressed with SHIFT and CONTROL
status is stored into the FIFO RAM.
 Scanned Sensor Matrix − In this mode, a sensor array can be interfaced with the
processor using either encoder or decoder scans. In the encoder scan, 8×8 sensor matrix
or with decoder scan 4×8 sensor matrix can be interfaced.
 Strobed Input − In this mode, when the control line is set to 0, the data on the return
lines is stored in the FIFO byte by byte.

Output Mode

This mode deals with display-related operations. This mode is further classified into two output
modes.
 Display Scan − This mode allows 8/16 character multiplexed displays to be organized as
dual 4-bit/single 8-bit display units.
 Display Entry − This mode allows the data to be entered for display either from the
right side/left side.
8251A USART
(UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER)

 The 8251 USART (Universal Synchronous Asynchronous Receiver

Transmitter) is used for serial data communication.
 As a peripheral device of a microcomputer system, the 8251 receives
parallel data from the CPU and transmits serial data after conversion.
 This device also receives serial data from the outside and transmits parallel
data to the CPU after conversion.
Differences between Asynchronous and Synchronous Data Transfer
FUNCTIONAL BLOCK DIAGRAM OF 8251A USART

 Data Bus Buffer: This three-state bi-directional 8-bit buffer is used to

interface the 8255 to the system data bus. Data is transmitted or received by
the buffer upon execution of input or output instructions by the CPU.
Control words and status information are also transferred through the data
bus buffer.
 Read/Write and Control Logic: The function of this block is to manage all
of the internal and external transfers of both Data and Control or Status
words. It accepts inputs from the CPU Address and Control busses and in
turn, issues commands.
 Transmitter Section: The transmitter section consists of three blocks—
transmitter buffer register, output register and the transmitter control logic
block. The CPU deposits (when TXRDY = 1, meaning that the transmitter
buffer register is empty) data into the transmitter buffer register, which is
subsequently put into the output register (when TXE = 1, meaning that the
output buffer is empty). In the output register, the eight bit data is converted
into serial form and comes out via TXD pin. The serial data bits are
preceded by START bit and succeeded by STOP bit, which are known as
framing bits. But this happens only if transmitter is enabled and the CTS is
low. TXC signal is the transmitter clock signal which controls the bit rate on
the TXD line (output line). This clock frequency can be 1, 16 or 64 times the
baud.
 Receiver Section: The receiver section consists of three blocks — receiver
buffer register, input register and the receiver control logic block. Serial data
from outside world is delivered to the input register via RXD line, which is
subsequently put into parallel form and placed in the receiver buffer register.
When this register is full, the RXRDY (receiver ready) line becomes high.
This line is then used either to interrupt the MPU or to indicate its own
status. MPU then accepts the data from the register. RXC line stands for
receiver clock. This clock signal controls the rate at which bits are received
by the input register. The clock can be set to 1, 16 or 64 times the baud in
the asynchronous mode.
SCHEMATIC DIAGRAM OF 8251 USART

PIN DIAGRAM OF 8251 USART

D0 to D7 This is bidirectional data bus which receive control words and
transmits data from the CPU and sends status words and
received data to CPU.

RESET A "High" on this input forces the 8251 into "reset status." The
device waits for the writing of "mode instruction." The min.
reset width is six clock inputs during the operating status
of CLK.

CLK CLK signal is used to generate internal device timing. CLK

signal is independent of RXC or TXC. However, the frequency
of CLK must be greater than 30 times the RXC and TXC at
Synchronous mode and Asynchronous
WR’ This is the "active low" input terminal which receives a signal
for writing transmit data and control words from the CPU into
the 8251.

RD’ This is the "active low" input terminal which receives a signal
for reading receive data and status words from the 8251.

C/D’ This is an input terminal which receives a signal for selecting

data or command words and status words when the 8251 is
accessed by the CPU.
If C/D’ = low, data will be accessed.
If C/D’ = high, command word or status word will be accessed.

CS’ This is the "active low" input terminal which selects the 8251 at
low level when the CPU accesses. Note: The device won’t be in
"standby status"; only setting CS’ = High.

TXD This is an output terminal for transmitting data from which

serial-converted data is sent out. The device is in "mark status"
(high level) after resetting or during a status when transmit is
disabled. It is also possible to set the device in "break status"
(low level) by a command.

TXRDY This is an output terminal which indicates that the 8251is ready
to accept a transmitted data character. But the terminal is
always at low level if CTS = high or the device was set in "TX
disable status" by a command. Note: TXRDY status word
indicates that transmit data character is receivable, regardless of
CTS or command. If the CPU writes a data character, TXRDY
will be reset by the leading edge or WR signal.

TXEMPTY This is an output terminal which indicates that the 8251 has
transmitted all the characters and had no data character. In
"synchronous mode," the terminal is at high level, if transmit
data characters are no longer remaining and sync characters are
automatically transmitted. If the CPU writes a data character,
TXEMPTY will be reset by the leading edge of WR signal.
Note : As the transmitter is disabled by setting CTS "High" or
command, data written before disable will be sent out. Then
TXD and TXEMPTY will be "High". Even if a data is written
after disable, that data is not sent out and TXE will be
"High".After the transmitter is enabled, it sent out. (Refer to
Timing Chart of Transmitter Control and Flag Timing)

TXC This is a clock input signal which determines the transfer speed
of transmitted data. In "synchronous mode," the baud rate will
be the same as the frequency of TXC. In "asynchronous mode",
it is possible to select the baud rate factor by mode instruction.
It can be 1, 1/16 or 1/64 the TXC. The falling edge of TXC
shifts the serial data out of the 8251.

RXD This is a terminal which receives serial data.

RXRDY This is a terminal which indicates that the 8251 contains a c

character that is ready to READ. If the CPU reads a data
character, RXRDY will be reset by the leading edge of RD’
signal. Unless the CPU reads a data character before the next
one is received completely, the preceding data will be lost. In
such a case, an overrun error flag status word will be set.

RXC This is a clock input signal which determines the transfer speed
of received data. In "synchronous mode," the baud rate is the
same as the frequency of RXC. In "asynchronous mode," it is
possible to select the baud rate factor by mode instruction. It
can be 1, 1/16, 1/64 the RXC.

SYNDET/BD This is a terminal whose function changes according to mode.

In "internal synchronous mode." this terminal is at high level, if
sync characters are received and synchronized. If a status word
is read, the terminal will be reset. In "external synchronous
mode, "this is an input terminal. A "High" on this input forces
the 8251 to start receiving data characters.
In "asynchronous mode," this is an output terminal which
generates "high level" output upon the detection of a "break"
character if receiver data contains a "low-level" space
between the stop bits of two continuous characters. The
terminal will be reset, if RXD is at high level. After Reset is
active, the terminal will be output at low level.
DSR’ This is an input port for MODEM interface. The input status of
the terminal can be recognized by the CPU reading status
words.

DTR’ This is an output port for MODEM interface. It is possible to

set the status of DTR by a command.

CTS’ This is an input terminal for MODEM interface which is used

for controlling a transmit circuit. The terminal controls data
transmission if the device is set in "TX Enable" status by a
command. Data is transmitable if the terminal is at low level.

RTS’ This is an output port for MODEM interface. It is possible to

set the status RTS by a command.
CONTROL WORDS
There are two types of control words.
1. Mode Instruction Set word (setting of function)
2. Command Set word (setting of operation)

MODE INSTRUCTION SET WORD

Mode instruction is used for setting the function of the 8251. Mode instruction will
be in "wait for write" at either internal reset or external reset. That is, the writing of
a control word after resetting will be recognized as a "mode instruction."
Mode set word for Asynchronous mode
Mode set word for Synchronous mode
Q. Write a mode set word to use 8251 in asynchronous mode with 1 start/stop bits,
with 7 character length.

Ans. Mode set word = 01001001

Q. Write the command instruction word to use the transmitter section for forced
break detection and hunt mode.

Ans. Command Instruction word = 10001001

8253/8254 PROGRAMMABLE INTERVAL TIMER (PIT)

 The 8253 is a programmable interval timer/counter specifically designed for

use in real-time application for timing and counting function such as binary
counting, generation of accurate time delay, generation of square wave, rate
generation, hardware/software triggered strobe signal, one-shot signal of
desired width, etc.
 The generation of accurate time delay using software control or writing
instruction is possible. But instead of writing instructions for time delay
loop, the 8253 timer may be used for this.
 The 8253 operates in the frequency range of dc to 2.6 MHz while the 8253
use NMOS technology.
 The 8253 is compatible with all Intel and most other microprocessors.
 The 8254 programmable Interval timer consists of three independent 16-bit
presettable counters (timers).
 Each counter is capable of counting in binary or binary coded decimal.
 The maximum allowable frequency to any counter is 10MHz.
 Counter can be programmed in six different modes.
 This device is useful whenever the microprocessor must control real-time
events. The timer in a personal computer is an 8253.
 To operate a counter a 16-bit count is loaded in its register and on command,
it begins to decrement the count until it reaches 0.
 At the end of the count it generates a pulse, which interrupts the processor.
The count can count either in binary or BCD.
The 8254 is a superset of 8253. The functioning of these two ICs are almost similar
along with the pin configuration. Only the differences are:
8253 8254 Read on the fly
1. Operating frequency 0 - 2.6 MHz. 1. Operating frequency 0 - 10 MHz.
2. Uses N-MOS technology. 2. Uses H-MOS technology.
3. Read-Back command not available. 3. Read-Back command available.
4. Reads and writes of the same 4. Reads and writes of the same
counter cannot be interleaved. counter can be interleaved.

5. 8254 has powerful command called

READ BACK command which
allows the user to check the count
value, programmed mode and
current mode and current status of
the counter.
FUNCTIONAL BLOCK DIAGRAM OF 8253 PIT
It includes three counters, a data bus buffer, Read/Write control logic, and a
control register. Each counter has two input signals CLOCK and GATE and one
output signal OUT.

Data Bus Buffer: This tri-state, bi-directional, 8-bit buffer is used to interface the
8253/54 to the system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.

Read/Write Control Logic: The Read/Write logic has five signals : RD’, WR’,
CS’ and the address lines A0 and A1. In the peripheral I/O mode, the RD’ and
WR’ signals are connected to IOR and IOW, respectively. In memory-mapped I/O,
these are connected to MEMR and MEMW. Address lines A0 and A1 of the CPU
are usually connected to lines A0 and A1 of the 8253/54, and CS’ is tied to a
decoded address. The control word register and counters are selected according to
the signals on lines A0 and A1.

A1 A0 Selection
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Register
Control Word Register: This register is accessed when lines A0 and A1 are at
logic 1. It is used to write a command word which specifies the counter to be used
(binary or BCD), its mode, and either a read or write operation.

Counters : These three functional blocks are identical in operation. Each counter
consists of a single, 16 bit, pre-settable, down counter. The counter can operate in
either binary or BCD and its input, gate and output are configured by the selection
of modes stored in the control word register. The counters are fully independent.
The programmer can read the contents of any of the three counters without
disturbing the actual count in process.
PIN DIAGRAM OF 8253 PIT

D7-D0 The data bus buffer is connected to microprocessor using

D7 – D0 pins which are also bidirectional.

CS’ The chip select input is used to enable the communicate

between 8253 and the microprocessor by means of data bus. A
low an CS enables the data bus buffers, while a high disables
the buffer. The CS input does not have any affect on the
operation of three times once they have been initialized. The
normal configuration of a system employs an decode logic
which actives CS line, whenever a specific set of addresses
that correspond to 8253 appear on the address bus.
RD’ & WR’ The read (RD’) and write (WR’) pins central the direction of
data transfer on the 8-bit bus. When the input RD pin is low.
Then CPU is inputting data from 8253 in the form of counter
value. When WR’ pins is low, then CPU is sending data to 8253
in the form of mode information or loading counters. The RD’
& WR’ should not both be low simultaneously. When RD’ &
WR’ pins are HIGH, the data bus buffer is disabled.

A0 & A1 These two input lines allow the microprocessor to specify

which one of the internal register in the 8253 is going to be
used for the data transfer. These two lines are used to select
either the control word register or one of the 16-bit counters.
CONTROL WORD FOR 8253 PIT

STATUS WORD FOR 8254 PIT (ONLY FOR 8254)

MODES OF OPERATION OF 8253 PIT

8235 PIT can operate in six different modes of operation:

1. MODE 0 : Interrupt on Terminal Count

2. MODE 1 : Hardware Retriggerable One-shot/ Programmable Mono
Shot
3. MODE 2 : Rate Generator
4. MODE 3 : Square Wave Rate Generator
5. MODE 4 : Software Triggered Strobe
6. MODE 5 : Hardware Triggered Strobe
MODE 0 : Interrupt on Terminal Count

a) Normal Operation:
1) The output will be initially low after the mode set operation.
2) After the count is loaded into the selected count register the output will remain
low and the counter will count.
3) When the terminal count is reached the output will go high and remain high
until the selected count is reloaded.

b) Gate Disable
1) Gate = 1 enables counting.
2) Gate = 0 disables counting.
Note : Gate has no effect on OUT.

c) New Count
If a new count is written to the counter, it will be loaded on the next CLK pulse
and counting will continue from the new count

In case of two byte count:

1) Writing the first byte disables counting.
2) Writing the second byte loads the new count on the next CLK pulse and
counting will continue from the new count.
MODE 1 : Hardware Retriggerable One-shot/ Programmable Mono Shot

a) Normal operation
1) The output will be initially high
2) The output will go low on the CLK pulse following the rising edge at the gate
input.
3) The output will go high on the terminal count and remain high until the next
rising edge at the gate input.

b) Retriggering
The one shot is retriggerable, hence the output will remain low for the full count
after any rising edge of the gate input.

c) New count
If the counter is loaded during one shot pulse, the current one shot is not affected
unless the counter is retriggered. If retriggered, the counter is loaded with the new
count and the one-shot pulse continues until the new count expires.
MODE 2 : Rate generator
This mode functions like a divide by-N counter.

a) Normal Operation
1) The output will be initially high.
2) The output will go low for one clock pulse before the terminal count.
3) The output then goes high, the counter reloads the initial count and the process
is repeated.
4) The period from one output pulse to the next equals the number of input counts
in the count register.

b) Gate Disable
1) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).
2) If Gate goes low during an low output pulse, output is set immediately high.
A trigger reloads the count and the normal sequence is repeated.

c) New count The current counting sequence does not affect when the new count
is written. If a trigger is received after writing a new count but before the end of
the current period, the new count will be loaded with the new count on the next
CLK pulse and counting will continue from the new count. Otherwise, the new
count will be loaded at the end of the current counting cycle.
Note : In mode 2, a count of 1 is illegal.
MODE 3 : Square Wave Rate Generator

a) Normal operation
1) Initially output is high.
2) For even count, counter is decremented by 2 on the falling edge of each clock
pulse. When the counter reaches terminal count, the state of the output is changed
and the counter is reloaded with the full count and the whole process is repeated.
3) If the count is odd and the output is high the first clock pulse (after the count
is loaded) decrements the count by 1. Subsequent clock pulses decrement the clock
by 2. After timeout, the output goes low and the full count is reloaded. The first
clock pulse (following the reload) decrements the count by 3 and subsequent clock
pulse decrement the count by two. Then the whole process is repeated. In this way,
if the count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2
counts.

b) Gate Disable
If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while
output is low, output is set high immediately. After this, When Gate goes high, the
counter is loaded with the initial count on the next clock pulse and the sequence is
repeated.

c) New Count
The current counting sequence does not affect when the new count is written. If a
trigger is received after writing a new count but before the end of the current half-
cycle of the square wave, the counter will be loaded with the new count on the next
CLK pulse and counting will continue from the new count. Otherwise, the new
count will be loaded at end of the current half-cycle.
MODE 4 : Software Triggered Strobe.

a) Normal operation
1) The will be initially high
2) The output will go low for one CLK pulse after the terminal count (TC).

b) Gate Disable
If Gate is one the counting is enabled otherwise it is disabled. The Gate has no
effect on the output.

c) New count
If a new count is written during counting, it will be loaded on the next CLK pulse
and counting will continue from the new count. If the count is two byte then
1) Writing the first byte has no effect on counting.
2) Writing the second byte allows the new count to be loaded on the next CLK
pulse.
MODE 5 : Hardware Triggered Strobe (Retriggerable).

a) Normal operation
1) The output will be initially high.
2) The counting is triggered by the rising edge of the Gate.
3) The output will go low for one CLK pulse after the terminal count (TC).

b) Retriggering
If the triggering occurs on the Gate input during the counting, the initial count is
loaded on the next CLK pulse and the counting will be continued until the terminal
count is reached.

c) New count
If a new count is written during counting, the current counting sequence will not
be affected. If the trigger occurs after the new count is written but before the
terminal count, the counter will be loaded with the new count on the next CLK
pulse and counting will continue from there.
Q Write a control word to select counter 2 to operate in Mode 3 for binary
counting

Ans. Control word = 10 110110 = B6H