CAO UNIT-3

INPUT/OUTPUT INTERFACE

Interfaces
Interface is a shared boundary between two separate components of the computer system which can be used to
attach two or more components to the system for communication purposes.
There are two types of interface:

1. CPU Interface
2. I/O Interface

Input-Output Interface
Peripherals connected to a computer need special communication links for interfacing with CPU. In computer system,
there are special hardware components between the CPU and peripherals to control or manage the input-output
transfers. These components are called input-output interface units because they provide communication links
between processor bus and peripherals. They provide a method for transferring information between internal system
and input-output devices.

ASYNCHRONOUS DATA TRANSFER

Asynchronous input output is a form of input output processing that allows others devices to do processing before the transmission or
data transfer is done.
Problem faced in asynchronous input output synchronization –
It is not sure that the data on the data bus is fresh or not as their no time slot for sending or receiving data.
This problem is solved by following mechanism:
1. Strobe
2. Handshaking
Data is transferred from source to destination through data bus in between.
1. Strobe Mechanism:

1. Source initiated Strobe – When source initiates the process of data transfer. Strobe is just a signal.

(i) First, source puts data on the data bus and ON the strobe signal.
(ii) Destination on seeing the ON signal of strobe, read data from the data bus.
(iii) After reading data from the data bus by destination, strobe gets OFF.
Signals can be seen as:

It shows that first data is put on the data bus and then strobe signal gets active.
2. Destination initiated signal – When destination initiates the process of data transfer.

(i) First, the destination ON the strobe signal to ensure the source to put the fresh data on the data bus.
(ii) Source on seeing the ON signal puts fresh data on the data bus.
(iii) Destination reads the data from the data bus and strobe gets OFF signal.
Signals can be seen as:
It shows that first strobe signal gets active then data is put on the data bus.
Problems faced in Strobe based asynchronous input output –
1. In Source initiated Strobe, it is assumed that destination has read the data from the data bus but their is no surety.
2. In Destination initiated Strobe, it is assumed that source has put the data on the data bus but their is no surety.
This problem is overcome by Handshaking.
2. Handshaking Mechanism:
1. Source initiated Handshaking – When source initiates the data transfer process. It consists of signals:
DATA VALID: if ON tells data on the data bus is valid otherwise invalid.
DATA ACCEPTED: if ON tells data is accepted otherwise not accepted.
(i) Source places data on the data bus and enable Data valid signal.
(ii) Destination accepts data from the data bus and enable Data accepted signal.
(iii) After this, disable Data valid signal means data on data bus is invalid now.
(iv) Disable Data accepted signal and the process ends.
Now there is surety that destination has read the data from the data bus through data accepted signal.
Signals can be seen as:
It shows that first data is put on the data bus then data valid signal gets active and then data accepted signal gets active. After
accepting the data, first data valid signal gets off then data accepted signal gets off.
2. Destination initiated Handshaking – When destination initiates the process of data transfer.
REQUEST FOR DATA: if ON requests for putting data on the data bus.
DATA VALID: if ON tells data is valid on the data bus otherwise invalid data.
(i) When destination is ready to receive data, Request for Data signal gets activated.
(ii) source in response puts data on the data bus and enabled Data valid signal.
(iii) Destination then accepts data from the data bus and after accepting data, disabled Request for Data signal.
(iv) At last, Data valid signal gets disabled means data on the data bus is no more valid data.
Now there is surety that source has put the data on the data bus through data valid signal.
Signals can be seen as:

It shows that first Request for Data signal gets active then data is put on data bus then Data valid signal gets active. After
reading data, first Request for Data signal gets off then Data valid signal.

Difference between Synchronous and Asynchronous Transmission

Synchronous Transmission:
In Synchronous Transmission, data is sent in form of blocks or frames. This transmission is the full duplex type. Between sender and
receiver the synchronization is compulsory. In Synchronous transmission, There is no gap present between data. It is more efficient
and more reliable than asynchronous transmission to transfer the large amount of data.
Asynchronous Transmission:
In Asynchronous Transmission, data is sent in form of byte or character. This transmission is the half duplex type transmission. In
this transmission start bits and stop bits are added with data. It does not require synchronization.

Now, let’s see the difference between Synchronous and Asynchronous Transmission:

S.NO SYNCHRONOUS TRANSMISSION ASYNCHRONOUS TRANSMISSION

In Synchronous transmission,

Data is sent in form of blocks or In asynchronous transmission, Data is sent

1. frames. in form of byte or character.

2. Synchronous transmission is fast. Asynchronous transmission is slow.

Synchronous transmission is

3. costly. Asynchronous transmission is economical.

In Synchronous transmission,

time interval of transmission is In asynchronous transmission, time interval

4. constant. of transmission is not constant, it is random.

In Synchronous transmission,

There is no gap present between In asynchronous transmission, There is

5. data. present gap between data.

6. Efficient use of transmission line While in asynchronous transmission,

is done in synchronous transmission line remains empty during gap

transmission. in character transmission.

Asynchronous transmission have no need of

Synchronous transmission needs synchronized clocks as parity bit is used in

precisely synchronized clocks for this transmission for information of new

7. the information of new bytes. bytes.

Difference between Serial and Parallel Transmission

There are two methods are used for transferring data between computers which are given below: Serial Transmission, and Parallel
Transmission.
Serial Transmission:
In Serial Transmission, data-bit flows from one computer to another computer in bi-direction. In this transmission one bit flows at
one clock pulse. In Serial Transmission, 8 bits are transferred at a time having a start and stop bit.

Parallel Transmission:
In Parallel Transmission, many bits are flow together simultaneously from one computer to another computer. Parallel Transmission
is faster than serial transmission to transmit the bits. Parallel transmission is used for short distance.

Difference between Serial and Parallel Transmission:

S.NO SERIAL TRANSMISSION PARALLEL TRANSMISSION

In serial transmission, data(bit) flows In Parallel Transmission, data flows in

1. in bi-direction. multiple lines.

Parallel Transmission is not cost

2. Serial Transmission is cost efficient. efficient.

In serial transmission, one bit In Parallel Transmission, eight bits

3. transferred at one clock pulse. transferred at one clock pulse.

Serial Transmission is slow in Parallel Transmission is fast in

4. comparison of Parallel Transmission. comparison of Serial Transmission.

Generally, Serial Transmission is used Generally, Parallel Transmission is

5. for long distance. used for short distance.

The circuit used in Serial Transmission The circuit used in Parallel

6. is simple. Transmission is relatively complex.

MODES OF DATA TRANSFER

I/O Interface (Interrupt and DMA Mode)

The method that is used to transfer information between internal storage and external I/O devices is known as I/O interface. The CPU
is interfaced using special communication links by the peripherals connected to any computer system. These communication links
are used to resolve the differences between CPU and peripheral. There exists special hardware components between CPU and
peripherals to supervise and synchronize all the input and output transfers that are called interface units.

Mode of Transfer:

The binary information that is received from an external device is usually stored in the memory unit. The information that is
transferred from the CPU to the external device is originated from the memory unit. CPU merely processes the information but the
source and target is always the memory unit. Data transfer between CPU and the I/O devices may be done in different modes.
Data transfer to and from the peripherals may be done in any of the three possible ways
1. Programmed I/O.
2. Interrupt- initiated I/O.
3. Direct memory access( DMA).
Now let’s discuss each mode one by one.
1. Programmed I/O: It is due to the result of the I/O instructions that are written in the computer program. Each data item
transfer is initiated by an instruction in the program. Usually the transfer is from a CPU register and memory. In this case it
requires constant monitoring by the CPU of the peripheral devices.
Example of Programmed I/O: In this case, the I/O device does not have direct access to the memory unit. A transfer from I/O
device to memory requires the execution of several instructions by the CPU, including an input instruction to transfer the data
from device to the CPU and store instruction to transfer the data from CPU to memory. In programmed I/O, the CPU stays in
the program loop until the I/O unit indicates that it is ready for data transfer. This is a time consuming process since it
needlessly keeps the CPU busy. This situation can be avoided by using an interrupt facility. This is discussed below.

2. Interrupt- initiated I/O: Since in the above case we saw the CPU is kept busy unnecessarily. This situation can very well
be avoided by using an interrupt driven method for data transfer. By using interrupt facility and special commands to
inform the interface to issue an interrupt request signal whenever data is available from any device. In the meantime the
CPU can proceed for any other program execution. The interface meanwhile keeps monitoring the device. Whenever it is
determined that the device is ready for data transfer it initiates an interrupt request signal to the computer. Upon detection
of an external interrupt signal the CPU stops momentarily the task that it was already performing, branches to the service
program to process the I/O transfer, and then return to the task it was originally performing.

Note: Both the methods programmed I/O and Interrupt-driven I/O require the active intervention of the
processor to transfer data between memory and the I/O module, and any data transfer must transverse
a path through the processor. Thus both these forms of I/O suffer from two inherent drawbacks.
 The I/O transfer rate is limited by the speed with which the processor can test and service a
device.
 The processor is tied up in managing an I/O transfer; a number of instructions must be executed
for each I/O transfer.
3. Direct Memory Access: The data transfer between a fast storage media such as magnetic disk and memory unit is limited
by the speed of the CPU. Thus we can allow the peripherals directly communicate with each other using the memory buses,
removing the intervention of the CPU. This type of data transfer technique is known as DMA or direct memory access.
During DMA the CPU is idle and it has no control over the memory buses. The DMA controller takes over the buses to
manage the transfer directly between the I/O devices and the memory unit.

Bus Request : It is used by the DMA controller to request the CPU to relinquish the control of the buses.
Bus Grant : It is activated by the CPU to Inform the external DMA controller that the buses are in high impedance state and the
requesting DMA can take control of the buses. Once the DMA has taken the control of the buses it transfers the data. This transfer
can take place in many ways.
Types of DMA transfer using DMA controller:
Burst Transfer :
DMA returns the bus after complete data transfer. A register is used as a byte count,
being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will
release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data
transfer.
Steps involved are:
1. Bus grant request time.
2. Transfer the entire block of data at transfer rate of device because the device is usually slow than the
speed at which the data can be transferred to CPU.
3. Release the control of the bus back to CPU
So, total time taken to transfer the N bytes
= Bus grant request time + (N) * (memory transfer rate) + Bus release control time.
Where,
X µsec =data transfer time or preparation time (words/block)
Y µsec =memory cycle time or cycle time or transfer time (words/block)
% CPU idle (Blocked)=(Y/X+Y)*100
% CPU Busy=(X/X+Y)*100
Cyclic Stealing :
An alternative method in which DMA controller transfers one word at a time after which it must return the control of the buses to the
CPU. The CPU delays its operation only for one memory cycle to allow the direct memory I/O transfer to “steal” one memory cycle.
Steps Involved are:
4. Buffer the byte into the buffer
5. Inform the CPU that the device has 1 byte to transfer (i.e. bus grant request)
6. Transfer the byte (at system bus speed)
7. Release the control of the bus back to CPU.
Before moving on transfer next byte of data, device performs step 1 again so that bus isn’t tied up and
the transfer won’t depend upon the transfer rate of device.
So, for 1 byte of transfer of data, time taken by using cycle stealing mode (T).
= time required for bus grant + 1 bus cycle to transfer data + time required to release the bus, it will be
NxT

In cycle stealing mode we always follow pipelining concept that when one byte is getting
transferred then Device is parallel preparing the next byte. “The fraction of CPU time to the data
transfer time” if asked then cycle stealing mode is used.
Where,
X µsec =data transfer time or preparation time
(words/block)
Y µsec =memory cycle time or cycle time or transfer
time (words/block)
% CPU idle (Blocked) =(Y/X)*100
% CPU busy=(X/Y)*100
Interleaved mode: In this technique , the DMA controller takes over the system bus when the
microprocessor is not using it. An alternate half cycle i.e. half cycle DMA + half cycle processor.
CONTROL UNIT DESIGN METHODS (HARDWIRED&MICROPROGRAMMED)

CONTROL MEMORY

To execute an instruction, the control unit of the CPU must generate the required control signal in
the proper sequence. There are two approaches used for generating the control signals in proper
sequence as Hardwired Control unit and Micro-programmed control unit.
Hardwired Control Unit –
The control hardware can be viewed as a state machine that changes from one state to another in
every clock cycle, depending on the contents of the instruction register, the condition codes and the
external inputs. The outputs of the state machine are the control signals. The sequence of the
operation carried out by this machine is determined by the wiring of the logic elements and hence
named as “hardwired”.
 Fixed logic circuits that correspond directly to the Boolean expressions are used to generate
the control signals.
 Hardwired control is faster than micro-programmed control.
 A controller that uses this approach can operate at high speed.
 RISC architecture is based on hardwired control unit
Micro-programmed Control Unit –
 The control signals associated with operations are stored in special memory units
inaccessible by the programmer as Control Words.
 Control signals are generated by a program are similar to machine language programs.
 Micro-programmed control unit is slower in speed because of the time it takes to fetch
microinstructions from the control memory.
Some Important Terms –

Control Word: A control word is a word whose individual bits represent various control signals.
1. Micro-routine: A sequence of control words corresponding to the control sequence of a
machine instruction constitutes the micro-routine for that instruction.
2. Micro-instruction: Individual control words in this micro-routine are referred to as
microinstructions.
3. Micro-program: A sequence of micro-instructions is called a micro-program, which is
stored in a ROM or RAM called a Control Memory (CM).
4. Control Store: the micro-routines for all instructions in the instruction set of a computer are
stored in a special memory called the Control Store.
Types of Micro-programmed Control Unit – Based on the type of Control Word stored in the
Control Memory (CM), it is classified into two types:
1. Horizontal Micro-programmed control Unit:
The control signals are represented in the decoded binary format that is 1 bit/CS. Example: If 53
Control signals are present in the processor than 53 bits are required. More than 1 control signal
can be enabled at a time.
 It supports longer control word.
 It is used in parallel processing applications.
 It allows higher degree of parallelism. If degree is n, n CS are enabled at a time.
 It requires no additional hardware(decoders). It means it is faster than Vertical Micro-
programmed.
 It is more flexible than vertical micro-programmed
2. Vertical Micro-programmed Control Unit:
The control signals represented in the encoded binary format. For N control signals- Log2(N) bits
are required.
 It supports shorter control words.
 It supports easy implementation of new control signals therefore it is more flexible.
 It allows low degree of parallelism i.e., degree of parallelism is either 0 or 1.
 Requires an additional hardware (decoders) to generate control signals, it implies it is slower
than horizontal micro-programmed.
 It is less flexible than horizontal but more flexible than that of hardwired control unit.