0% found this document useful (0 votes)
160 viewsSinclair QL Service Manual
Service and schematics for Sinclair QL computer
Uploaded by
carlton_mickCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
0% found this document useful (0 votes)
160 viewsSinclair QL Service Manual
Service and schematics for Sinclair QL computer
Uploaded by
carlton_mickCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 59
na HFT FR FEB FE SE 2 =
el
Manual Title:
MANUAL
ISSUE
QL SERVICE MANUAL
HISTORY SHEET
CIRCUIT/LAYOUT
DIAGRANS
REMARKS
JANUARY 1985
UNE 1985
Minor changes made to pages 1.5
3.6,4.1,8.3,4.4,4.15,8.17, and 5.7.SAFETY MEASURES
This instruction manya? contains certain
WARNING and CAUTION
totices which MUST be foliowed by the user to
ensure SAFE operation and to retain the
equipment in a SAFE condition,
AI] users of the equipment described in thi
manual MUST have received adequate training
in its use and application in order to ensure
SAFE AND PROPER USE.
Any adjustment, maintenance and repair of the
opened apparatus under voltage shall be
carried out only by a skilled persun who is
AWARE OF THE HAZARD INVOLVEDQL SERVICE MANUAL
List of Contents
SECTION 1 SYSTEM DESCRIPTION
SECTION 2 DISASSEMBLY /ASSEMBLY
SECTION 3 SYSTEM TEST
SECTION 4 FAULT DIAGNOSIS AND REPAIR
SECTION 5 PARTS LISTS
—_—__———_—_——— List of illustrations ———________,
Fig No.
RS 232 Link Ld
Keyboard Matrix Interconnections 2
QL Block Diagram 1.3
QL Circuit Diagram (Issue 5) 1.4
QL Circuit Diagram (Issue 6) 1.5
Motor Location Jig 4d
Keyboard Format 4.2
Head Chassis 4.3
Printed Circuit Board (Issue 5) Component Layout 5.1
Printed Circuit Board (Issue 6) Component Layout 5.2
Prepared by THORN (EMI) DATATECH 11D
“for SINCLAIR RESEARCH LTD TT
JUNE 1985,
C Sinclair Research Ltd,SECTION 1
SYSTEM DESCRIPTION
Sub-Section LIST OF CONTENTS Page No.
1 Introduction
2 Architecture
3 mc 68008 CPU
4 catel 8049 Intelligent Peripheral Controller ({PC)
5 “emory Organisation
6 Peripheral Control (7X8301, 248302 and 1C24)
7 Microdrive
8 Power Supplies
a Test
R5232 Link
Keyboard Matrix Interconnections
QL Block Diagram
QL Circuit Diagram (Issue 5)
QL Circuit Diagram (Issue 6)
im INTRODUCTION
1.1 The QL computer can be regarded in hardware terms as a combination of
an exhanced Spectrum microcomputer, an Interface lL, an Interface 2 and
two HMicrodrives within the same case. In practice the resemblance to
the Spectrum is small, since the QL requires two microprocessors to
accommodate powerful new software and is provided with 128k bytes of
inbuiit DRAM. A block diagram of the Sinclair QL is given in
Figure 1.3.
1.2 Two main versions of the QL are in circulation. A certain number of
boards to build standards up to Issue 5 were issued in either 0M or
EPROM versions with another ROM mounted pickaback in IC33 position.
The second, volume production, version of the board to build standard
Issue 6, and subsequent, features 48k of on-board ROM realised in two
memory devices. In the following description the two versions are
referred to as the pre-Issue 6 and the post-lssue 6 versions. The
main differences between the two versions, as far as the circuit
description is concerned, are that IC17 and [C27 nave been deleted and
1C38 added in the post-lssue 6 version.
Ll2.
21
2.2
2.3
3.1
3.2
3.3
ARCHITECTURE
The architecture of the QL shown in Figure 1.3 incorporates much that
is typical of microcomputer systems, but certain innovations make it
atypical. Two microprocessors, an Inte? 8049 and a Motorola 68008 are
used, and the availability of 123k of DRAM plus a minimum of 200k on
the two microdrives provides unusual storage facilities, The 8049 is
designated the [ntelligent Peripheral Controller (IPC) and the 68008
is the CPU, Two additional semi-custom ICs ZX8301 and 2X8302 contro?
defined areas of the system, under the supervision of the CPU.
The microcomputer electronics are housed on a single printed circuit
board which also houses a regulated power supply fed from an external
power unit. The keyboard forms part of the upper case assembly and is
connected to the p-c.board via Jll and J12. the microdrive headboards
and microdrive chassis, including the microdrives and the motors, form
two complete sub-assembl ies which plug in to the main p.c.board.
To the rear and side of the case are plug assemblies which accommodate
the following:
(a) main expansion connector, Jl
(b) ROM cartridge, J2
(c) Joystick, J3, v4
(4) 8232, 05, 36
(e) extra microdrives, EC!
Mc 68008 CPU
The Motorola MC 68008 is a 32-bit microprocessor with an B-bit date
bus and is responsible for the overall timing and control of the QL.
The firmware, which is outside the scope of this manual, resides in
either a ROM or an EPRON depending on the version, The 68008 has an
external clock, generated by the 7ZX8301 and has the usual bus
input/output arrangement, viz. data bus, address bus and contro! bus.
It operates semi-synchronously in this configuration.
Data Bus. 00-07 forms an 8-bit bi-directional data bus with active
high, tri-state ovtputs. It is used for data exchanges with the
memory, with the ZXB302 and ZX8301 and with the peripherals.
Address Bus. Twenty bits A0-A19 are available for select and address
purposes. AO-A15 form a 15-bit address bus with active high. The
address bus provides the address for memory (up to 128k aytes) data
exchanges and for data exchanges with the QL and microdrive. Three
bits AO, Al and AS are used for this latter purpose, Bits Al6-A19 are
used for device selection.
1.23.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
Control Bus. The control bus is a collection of individual signals
which supervise the flow of data on the address and data busses. The
block diagram shows most of these signals but reference to the circuit
diagram shows other control signals available at the expansion port.
Control lines are sunmarised below.
Interrupt Control (TPLB/2,IPL1). These inputs indicate the encoded
priority level of the device requesting an interrupt, and are fed by
124 (pins 23,24) and 1C23 (pin 26). A satisfactory interrupt
condition must exist for two successive clocks before triggering an
internal interrupt request. An interrupt acknowledge sequence is
indicated by the function codes, FCO and FC1. In this configuration
FCO and FC1 are MANDed together at 1C27,6 and the output routed to the
valid peripheral address (VPA) input to the CPU. This input indicates
that the processor should use automatic vectoring for an interrupt.
The IPL signals and VPA may also be input from an external device via
Jl, the main expansion connector.
A16 and Al7, These two address bits select 7X8301 and are decoded by
jt to assert the relevant CASA and CASI signal and ROMOEH and PCENL
for the 7X8302 chip enable. For this purpose their states are either
jow and high, or high and low respectively. When ROM is being
addressed both are in the low state.
CLK Input. The CLK input denoted CLKCPU is the 7.5 NHz system clock
from 2X8301. It is also fed to 1C23 and IC24 and to the expansion
port connector.
Asynchronous data transfers are handled using the following control
signals; DTACK, 8/W, DS and AS. These signals are explained in the
following paragraphs.
DIACK (Oata Transfer Acknowledge). This input indicates that the data
transfer is completed, and is sent by the ZX8301 ar through the
expansion connector. when the processor recognises DTACK during a
read cycle, data is latched and the bus cycle is terminated. When
DIACK is recognised during a write cycle, the bus cycle is terminated.
R/H. This tri-state signal defines the data bus transfer as a read or
write cycle. The R/W signal also works in conjunction with the data
strobe as explained in the following paragraph.
DS (Data Strobe). This tri-state signal controls the flow of data on
the data bus as shown in the table betow. When the R/W line is_high,
the processor reads from the data bus as indicated. When the R/W line
is low the processor writes to the data bus as shown.
1.33.12
3.13
3.14
3.15
3.16
1 - No valid data
0 1 Valid Data Bits 0-7 (Read Cycle)
0 0 Valid Data Bits 0-7 (Write Cycle)
If the CPU is addressing an external device with one of address bits
Al8 and AIS set, emitter follower TRB is switched on by the signal
XILLB from 1C38, This sets the DSMCL (Data Strobe Master Chip -
Active Low}; the ‘Master Chip' is the ZX@301) line permanently high
thus disabling IC23 and IC22, The toca] DS signal is still enabled to
Jl, the expansion port, to control R/W operations from an external
device. In the pre-Issue 6 version TR8 is switched from IC18,
FS (Address Strobe). This tri-state signal indicates that there is a
valid address on the address bus.
Four other groups of control signals are used by the CPU. These four
groups are routed to Jl only and are associated with Bus Arbitration
Control, Peripheral Control, Processor Status and System Control in
respect of external devices.
Bus Arbitration Control. An explanation of this function is included
for information only. It is not used by the QL but could be used by
peripherals. The 68008 contains a Simple 2-~wire arbitration circuit
designed to work with daisy-chained networks, priority encoded
networks, or a combinatian of these techniques. This circuit is used
in determining which device will be the bus master device. The BR
(Bus Request} input is wire ORed with all other devices that could be
bus masters. This device indicates to the processor that some other
device desires to become the bus master, Bus requests may be used at,
any time in a cycle or even #f no cycle is being performed. The BG
(Bus Grant} output signal indicates to all other potential bus master
devices that the processor will release bus control at the end of the
current bus cycle.
M6800-compatible Peripheral Control is exercised through the VPA and E
output lines. WPA is derived from two processor status signals FCI
and FCO as described above though this is only used for auto
vectoring. £ (Enable) 5 the standard enable signal common to all
M6800 type peripheral devices. The period for this output is 10
NC68008 clock periods (six clocks low, four clocks high).
Processor Status (FEO, FCI and FC2) are function code outputs which
indicate the state (user or supervisor} atd the cycle type currently
being executed, as shown in the table below. The information
indicated by the function code outputs is valid whenever address
strobe (MS) is active. -
143.17
3.18
3.19
4.2
4.3
4.4
Function Codé Output
FC2 FCL FCO Cycle Type
Low Low Low (Undefined, Reserved)
Low LOW HIGH User Data
Low aIGH LOW User Program
LOW HIGH HIGH (Undefined. Reserved)
HIGH LOW LOW (Undefined, Reserved)
HIGH LOW HIGH Supervisor Data
HIG © HIGH = LOW Supervisor Program
HIGH HIGH = ‘HIGK Interrupt Acknowledge
System Controt inputs are used to either reset or halt the processor
and to indicate to the processor that_bus errors have occurred. There
are three system control signals, BERR, HALT and RESET.
BERR (Bus Error). Not used on the QL.
RESET and HALT. The bidirectional RESET signal line acts to reset
(start a system initialisation sequence) the processor in response to
an external RESET signal. An internally generated reset (result of a
reset instruction) causes all external devices to be reset and the
internal state of the processor is not affected. A total system reset
(processor and external devices) is the result_of external HALT and
RESET signals applied at the same time. HALT and RESET are tied
together on the Qk-
INTEL 8049 INTELLIGENT PERIPHERAL CONTROLLER (IPC)
The 8049, IC24, is a totally self-sufficient 8-bit single chip
microcomputer containing 2 k bytes of pragram memory and 128 bytes of
RAM. It is clocked internally at 11 MHz from crystal x4.
In this application the function of the 8049 is to:
(a) receive RS232 interface signals,
(b) monitor the keyboard,
(c) control the loudspeaker,
(d) control the joystick.
The IPC utilises a data bus, two 8-bit 1/0 ports and some control
lines to control these functions.
Data Bus. 080-087 constitutes an 8-bit bi-directional data bus with
active high tri-state input/outputs. It is used only as input for
scanning the keyboard and joysticks.
Control Bus. Control is exercised by a number Qf discrete signals
which organise the direction and flow of data between the $049 and the
248302, and also communicate with, and monitor, other areas of the Qu.
Ls4.5
4.6
4.7
4.8
4.9
Control Lines. The role of each control line is as follows:
(a) Tl. Timer/Counter Input, 4 times the baud rate set by the user,
controled by a ZX8302 register.
(b) WR. Output strobe, active Tow, used as a read or write strobe to
enable keyboard, joystick or 85232 data to IC23 over the P27 link
Vine.
(c) P10-P17, Output lines used to scan the keyboard and joysticks in
conjunction with D&2-0B7.
(4) P26. Mot used on QL.
(e) 21. Loudspeaker output.
(¥) P27, Serial link transmitting data to 1¢23.
(g) P24,P25. RS232 handshake Vines.
(h) RESET. Input from 123 used to initialise the 8049.
(J) CLKCPU, Clock input from 248301.
(k) P23, P22 (IPLI,IPL2). Interrupt request lines to 68008 CPL.
(m) TNT, P20. Interrupt input. THT initiates an interrupt on
reception of 25232 first transitien, 20 is used to read the
data on the RS232 receive Vines.
RS232 Link. 1C24 is responsible for the receive side of the 85232
serial data link only, and [C23 the transmit side. Since the R5232
Vink is best understood as an entity both aspects are discussed here.
J5 and J6 are two RS232 connectors. J6 is connected so that the
device connected to it may act as the Data Terminal Equipment (OTE)
which originates the Data Terminal Ready (OTR) signal. J5 connects to
the Data Communications Equipment (OCE} i.e. the locat Ql assumes DIE
status. Figure 1.1 illustrates this schematically.
The RS232 interface uses an Il-bit ASCII data frame, viz. one start
bit, eight data bits and two stop bits comprise one character. Two
stop bits are always sent but the interface receives compatibly with
one except at 9600 baud, where one and a half stop bits are required.
Data is transmitted asynchronously in the full duplex mode.
Consider the QL as the OTE. Both OTE and OCE are switched on and have
their DIR signals asserted. CTS and DIR (Clear to Send, Data Terminal
Ready) do not form a handshake pair but are similar signals going in
opposite directions. Serial data is transmitted by 1C23 via driver
1025/6 and received by line receiver 1C26/Il. From IC26/11 data is
fed to WAND gate 1C27/9, pin 10 of which is set to the high state by
the program, and input to C24 pins 6 and 21 via IC27/11.
1.6ZEEE EEHEE ESSERE KEKE KE REE BS ES
FIGURE 1.1 S232 LINK
Qn receipt of a start bit, IC24 is interrupted, and a subroutine
clocks in the data bits, synchronised by the baud rate generator. The
data, up to about 20 bytes per RS232 channel, is then buffered in
1C24. At the same time, [C24 receives cormands (and sends reports)
via the serial link with IC18 which is contro’ ed by 1623. When 1C24
receives a cormand from IC18 to empty one of its buffers, it does so,
down the serial link via I¢23.
With the QL acting as the DCE data and control is managed in a similar
way utilising different I¢25 and iC26 receivers/drivers.
Keyboard Monitor. Under program contro? the 8049 systematically scans
the keyboard, recording which keys have been pressed. “igure 1.2
shows the way the keyboard is connected. {t consists of an 8 x 8
matrix with one key, the shift key, connected to three input lines.
The intersection of each row and column is bridged by a normally open
contact. Pressing the key closes this switch, The row ‘outputs’ and
column ‘inputs' are shown connected to separate connectors J11 and
J12, one to the port 1 outputs of [C24 and the other to the data bus
inputs. Pull-down resistors R17 to R24 ensure that when none of the
key-switches are closed row inputs KBO™ to KBO7 remain low.
174.13
Sal
SLL
5.1.2
5.1.3
5.2
5.2.1
When the keyboard scanning routines are entered (KBOn is output, KBIn
is input) the 8049 performs successive 1/9 read cycles setting each
KBOP to KBO7 Tine low in turn, At the same time the I/0 port 1 inputs
are scanned.
There are a totel of eleven diodes used for isolation. Fight of
these, D4 through D1 are isolation diodes which isolate the different
rows from each other. Three of the diodes D1 to 03 provide individual
isolation for the Shift Control and Alt keys so that these keys have
diodes in series with them in both directions of the matrix. They are
thus fully isolated.
Joystick. Connectors J3 and J4 provide a FIRE input and the four
switch inputs for each of twa joysticks. One line is not used. J3
and J4 are connected in parallel with keyboard connectors Jll and J12.
Loudspeaker Operation. During the execution of a BEEP instruction the
IPC writes to port 2, "21 thus switching on transistor TR1 and driving
the loudspeaker. The loudspeaker is damped by resistor R104 (post-
Issue 6 onty).
MEMORY ORGANISATION
Introduction
The pre-Issue 6 version was supplied in both EPROM and ROM forms with
on-board straps enabling the selection of ROM. Both versions have 4&k
of ROM and in both versions there are 128 bytes of RAM memory.
Figure 1.3 shows how the menory is organised. ¢
The lower 48k bytes (addresses 0000-8FFF) are implemented fn one 32k
and one 16k byte ROH, IC33 and IC34 respectively which hold the
monitor program. This program is a complex 68008 machine code program
divided broadly into two parts; the operating systen and the BASIC
interpreter. Details of the program content are outside the scope of
this manual.
32k bytes of memory (addresses COO0-FFFF] have been left assigned to
the ROM cartridge while 128 bytes of RAM (addresses 20000-3FFFF) are
implemented on sixteen 64-bit dynamic RAMS, IC1-IC16.
Read/Write Operations
The following description should be read in conjunction with the
circuit diagrams given in Figures 1.4 (pre-Issue 6) and 1.5 (post~
Issue 6).
Read Only Memory. The CPU addresses the ROM/EPROM directly during
memory read cycies using the address bus A15-AQ. In the pre-Issue 6
version, depending on the ROM/EPROM fit, the enabling and selection
pins on’ 1C33 and IC34 are set by link selection on ICi7. Links JU1 to
U6 via gate circuit ICL7 are used to provide the correct signals; the
Vink fit requirements for different ROM/EPRO! versions is listed on
the circuit diagram, Figure 1.4, In the post-Issue 6 version the
ROMs are enabled directly by the signal ROMOEH from ZX6301.
1.85.2.2
5.2.3
5.2.4
5.2.5
5.2.6
6.1
RAM Memory (IC1-IC16). The sixteen RAM ICs making up the 16k x 64 bit
RAM memory are organised as two matrices of 256 rows x 256 columns
ive. IC1-8 and 19-16. Thus, separate 8-bit row and column addresses
are required to access any one of the 64k locations in each section.
These addresses are supplied by the CPU (68008) on address bus AP to
AS via tri-state address multiplexers IC19 and 1C20. These
multiplexers decode from sixteen to eight lines and outputs enabled by
the row address select line (RASL) signal from the 2X830]. The valid
data address (VDA) selects the address from the CPU (via multiplexers
IC19,1C20) or from the ZX8301. ROWL from the ZX8301 selects the
row/column address. The R/W signal from the CPU informs the 2%8301 to
expect either 2 read or a write cycle. For a write cycle the ZX8301
enables the write enable (WEL) line to the memory.
The eight bits each of column and row address are routed to both 64k
sections of the RAM but the signals ‘column address select 0° (CASOL)
and ‘column address select 1' (CASIL) from the 2%8301 ensure that only
the required half of the memory is active. Address bits Al6 and Al?
from the CPU are decoded by the ZX8301 to enable the relevant CAS
signal. The row address select line (RASL) signal from the ZX8301 is
enabled during all read and write cycles from RAM,
The ZX8301 has priority when accessing memory since it must access the
memary mapped display area in the RAM at set intervals in order to
build up the video for the TV display. When the ZX8301 requires to
access memory, it asserts the VDA signal to CPU address multiplexers
IC19, {C20 and addresses RAM directly via its own address bus on pins
13,17,18, 20, 22,28, 27 and 28.
Isolation between the two, data busses D9-D7 and 089-087 is
accomplished using bus transceiver ICZl. During ZX8301 memory cycles
IC21 is disabled by negating the signal OEL from Hard Array Logic
(HAL) [C38. This signal is controlled by ZX8301 signal TXOEL. In the
pre-issue 6 version, which does not incorporate the HAL, TXOEL is fed
directly to IC2l.
Refresh for the DRAM memory is accomplished during normal read cycles
j.e. most rows are refreshed each time the 2X8301 accesses the memory
mapped display area during picture compilation, the remaining rows are
refreshed as a result of other read cycles also known to occur at
regular intervals within the refresh period.
PERIPHERAL CONTROL (ZX8301, 7X8302, [C38 and IC28)
2x8301, 1C22. The 7X8301 carries out the following functions:
TV picture generation
master clock generation
system address decode
DRAM refresh
control of the bus transceiver.
1.96.1.1
6.1.2
5.1.3
6.1.5
6.1.6
6.1.7
6.2
The TV picture generatian section of §C22 operates in conjunction with
the memory mapped picture display area to produce five colour TV
signals suitable for driving a colour monitor. These signals, red,
green and blue (RGB), CSYNCL (composite sync) and SYNCH (vertical
Sync) are routed to connector J7, The RG and CSYNCL signals are also
input to 1C28 which produces composite PAL to drive a domestic TV
receiver, ‘The same signals are mixed in transistor TR9 to produce a
composite video signal to drive a standard monochrome monitor. YSYNCH
js also routed to 1C23 where it is used to provide an interrupt at the
frane rate. This is used to give a time reference to the job
Scheduling supervisor in the operating system.
Using the 15 MHz crystal clock, XL, IC22 derives line and field timing
compatible with the external receiver. Video is derived by accessing
the memory mapped display area in the RAM in a set sequence at set
times throughout the picture frame. The addresses are necessarily
independent of the CPU and appear on I€22 address lines DA@ through
DAT.
The net result is the five video signals output from I£22 on pins
32,31,30,12 and 11.
The RGB signals are fed to level-setting resistor divider metwork R48-
R53 and ayc. coupled to RGB-to-PAL converter IC28 on pins 3,4 and 5.
The composite syne signal CSYNC is input on pin 2. External
components of the circuit provide a number of clamp circuits; the
luminance and chrominance signals are fed out, filtered and fed back
in; the chrominance 4.43 crystal oscillator is connected; and @ CR
jead/lag network introduces a 90°phase shift. The crystal has a very
high tolerance and does not need trimming.
The composite PAL signal fs output on pin 9, divided down and applied
to an encapsulated UHF modulator Ml,
Master clock is divided by two in IC22 from the externally connected
15 Hllz crystal Xl and distributed via output pin 7 to various
destinations on the board, and to Jl the main expansion connector.
The system address decode signal PCENL, routed to peripheral
contro? ler 2X8302 pin 10, is derived differently on the two board
versions. On the pre-Issue 6 board it is output from Z%8301 pin 39
and is derived from 2 combination of one of the decodes from address
lines A16 and Al7, and Ald (via DA6). In the post-Issue 6 version it
is output from HAL pin 17 and is derived in a similar way from a
decode of address lines 416, A17 and Ab.
2x8302, IC23, The ZX@302 is termed the peripheral chip since it
controls all signals to and from the peripheral devices. Signals
to/from the following are supervised:6.2.1
6.2.2
6.2.3
6.2.4
6.2.5
6.2.6
6.2.7
(a) Keyboard
Speaker by serial link to IPC
Joystick
RS232 (half)
{b) S232 (half)
(c) Net
(4) Microdrive
(e] Real-Time clock
(Ff) Interrupt control
123, in common with IC2#, works autonomously and is polled by the
cel, It has its own 32 kHz crystal clock K2 and has an external
interrupt input on pin 2 from Jl, the expansion connector. Switch $3
connected to pin 21 resets the device when operated. Pin 28 output
resets the CPU and IPC.
Address lines AP, Al and AS from the CPU select the specific device
requiring service viz: one of (a) to (e) in paragraph 5.2 above. The
VSYNCH and PCERL signals input an pins 10 and 32 have been discussed
in paragraph 6.1.1 and 6.1.7 respectively. The DSMCL signal is
discussed in paragraph 3.11.
Serial data from the various devices is converted to parallel data in
1C23 and autput to the data bus as 0BP-DB?, Parallel data from the
bus is converted to serial data and routed to the relevant device for
transmission.
The RS232 serial link, the keyboard and the joystick operation have
already been discussed in the 8049,C (1C24) section.
The two Net jack plugs J9 and J10 are connected in the same way as in
the Spectrum Interface 1 circuit, The network is common emitter in
that all stations on the network can either source current into the
net or be turned off, i.e, be set in tri-state. Jack plugs are used
such that those sockets which are unused serve to terminate the
network.
When a jack is inserted in the socket it opens up a connection to a
330a resistor, R15 or R16, disconnecting it from the circuit. With a
network set up, the two end stations would be the only ones with the
330@ resistors in circuit. There is therefore their combined
resistance, giving a pull-down impedance of about 1659 to the circuit.
1023 containg the interface and control circuitry for the network.
The real-time clock is run from the 32 kHz crystal X2 on pins 31 and
30. Date and time are resettable under software control. n pre-
issue 6 Qls, a trimming capacitor TCL enabled trimming of the
oscillator frequency. On the post-Issue 6 the trimming capacitor has
been replaced by a fixed capacitor.
Lu6.2.8
I
Tel
Rad
7.12
7.1.3
22
7.2.1
7.2.2
7.2.3
The remaining lines Gut from 1C23 are the micredrive control and data
Vines on pins 3,1,19,21,33 and 34. These inputs and outputs are
discussed 1n Section 7, NICRODRIVE.
MICRODRIVE
Introduction
Hicrodrive organisation and contro! in the Ql is similar to that found
in the Spectrum, bearing in mind that the two QL microdrives are
integrated into the system and that Interface 1 functions are a}?
executed by 1C23; also the frequency is different and write protect is
different.
Additional microdrives may be connected to the system via connector
ECL.
Only one microdrive may be in use at any instant. The required
microdrive and the type of operation, read or write, is selected under
software control. Ouring a read operation data is read from the
selected microdrive tape, During a write operation the microdrive
tape is erased before being written, The erase head is displaced from
the write head and is timed by 123 to sink current before the write
head is enabled.
Microdrive Selection
Microdrives are selected using the MOSELOH and MDSELCKN signals from
1C23. Each microdrive control chip, {¢29 and 1C30, contain one stage
of a shift register, realised by a flip-flop. MOSELCKN is connected
to each nicrodrive and MDSELDH is routed to pin 22 (COMMS IN) of IC29,
which is the input to the shift register. The shift register output
on pin 20 (COMMS OUT) is routed to COMMS IN in IC30, COMMS OUT on
1C30 pin 20 is routed to microdrive expansion connector ECl. The
selected microdrive has 2 '1' on its COMMS OUT pin. Thus the required
microdrive is selected by shifting the 'l* accordingly.
COMMS OUT not only feeds the next microdrive; it is used to select its
oun chip internal functions and to select the LED, the motor, and the
erase current for the selected microdrive. Therefore while this
signal is low the motor is disabled, the LED is off, no current can
flow through the microdrive switch (SI or S2), and no erase current
can flow.
Consider the motor drive circuit for number 1 motor. A high on pin 20
of 1C29 turns on TR4. This pulls the base of TR6 low, turning it on
and switching power to motor 1. Capacitor C21 and resistor R28 time
constant ensures that the motor does not cut out too quickly and
damage the tape. The red LEO 020 is switched on at the same time.
With TR6 turned on and write protect switch S1 closed the erase head
current circuit is enabled via pin 6 of headboard 1 connector. When
the erase output is enabled on pin 1 of 1C23, transistor TR3 switches
on and current flows in the selected microdrive erase head. Diodes1.2.8
73
7d
7.3.2
7.3.3
7.3.4
7.35
D18 and D16 provide protection against reverse currents. Diodes 012
across the erase head and D15 perform similar funct‘ons. The amount
of current flowing in the erase head is limited by R25.
Mrite protection is achieved by the action of the microswitch on the
microdrive chassis. The switch is operated by the write protect tab
on the microdrive cartridge. When the tab is present the select
supply line is connected to the erase coil, enabling the QL to write
normally. When the tab is absent, the supply to the erase head is
disconnected, and the MOROML line is held high {read mode) via
R100/101 and 022/23 (see Section 5, para 3.1). This line is clamped
to 5 volts maximum by diode 029. The purpose of 022/23 is to prevent
unselected microdrives with no cartridge inserted (or with write-
protected cartridge inserted) from loading the MDRDIL | ine.
Read/Write Operations
The MORDWL signal on 1¢23 pin 3 places the selected micradrive in
either the read or the write mode, and enables the read or the write
amplifiers.
Data is recorded on two tracks using a standard stereo cassette head
arrangement and is written in bytes, one byte to one track and the
next byte to the other track. it is recovered in the same way. The
tape itself is one continuous loop. Since hardware takes care of
switching between tracks the software sees the tape as one double-
length single track.
Power to the microdrive circuits has to be filtered and 1C31 and
capacitors C9 and Cll are used to accomplish this. IC31 is the
regulator.
Read Cycle. Consider £29 and headboard 1. in the read mode the
signals appearing in the two read coils inside the heads are
differentially amplified through two amplifier chains within i¢29,
The signals are then converted to digital form to enable logic
processing. The outputs from the two amplifiers, in digital form are
enabled into the DATA 1 and DATA 2 outputs from 1C29 on pins 24 and
19, These signals are routed to the interface within C23 via RAW
(Read and Write) 1 and 2, pins 21 and 19.
The signal recorded on magnetic tape is at the greatest when the rate
of change of the signal imposing it is at its fastest. Therefore when
a squarewave has been written, the greatest recovered voltage is
obtained on the edge of the pulse. Since the object of the exercise
is to produce a waveform which changes at the peaks of the recovered
signal, C29 contains amplifiers to bring the signal up to the
required level, and a peak detect circuit which changes state wher the
input reaches its greatest level. The peak detector is fo’’owed by a
hysteresis circuit which ensures that the output does not change on
spurious signals.1,3.6
1.37
8.1
8.2
8.3
8.4
9%.
a
9.2
The gain of the circuit should not need to be changed, as only one
type of high quality video tape is used. The reproduced signal levels
may be read across capacitors C15 and C17 and are typically in the
order of 400 to 500 mV and 250 to 350 mV for the low frequency and
high frequency signals respectively. In the record mode the modulator
in IC23 converts the ones and zeros in the data into FM (frequency
modulation) where there is always a transition at the beginning of the
bit cell. If the data is a one there is a transition at the beginning
and in the middie of the bit cell, which means essentially that the
frequency doubles if the data contains ones. Hence high and low
frequencies at C15 and C17.
Write Cycle. When the MDROWL signal from 1C23 goes ‘ow the selected
microdrive is placed in the write mode. This has the effect of
changing DATA I and DATA 2 on IC29 from outputs to inputs. These
inputs are used to drive current sources for track 1 and track 2.
When DATA 1 is high for example, current is pulled in one direction
through the head, when it 4s low current is pulled in the other
direction.
POWER SUPPLIES
A custom-built power pack, external to the main board, supplies 9
volts d.c. at 2 amps and 44 volts peak-to-peak a-c. to the board input
on connector J8. The power pack uses a thyristor to limit peak
voltages on the d.c., but is otherwise unregulated and has significant
ripple.
The a.c. input is applied to two rectifiers IC3? and 1C36 to produce
+12 volts at 80 milliamps and -12 volts at 50 millianps, respectively.
The d.c. input is regulated down to +5 volts by regulator 1¢35.
All three supplies are completely protected in that the regulators are
equipped with thermal and short circuit shutdown.
TEST
A good simple test of the equipment may be carried aut by connecting a
Joopdack cable to the RS232 interface connectors J§ and J6 and
instructing then to talk to each other. The technique for receiving
RS232 involves the data passing through the IPC, through 7X8302 and
back onto the processor data bus. If this functions correctly it is
close to a guarantee that the whole system is functional.
A test tape is available which exercises most of the functions of the
QL_and is a useful {initial diagnastic tool. See Section 3 for
details.ve
sae
wva
ny
eos
Lyos
canaina
SNOJLO3NNOOIINT XIYLWW CYVOSATY
et aunold
$
