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121 views63 pagesDLCD Akash Sem3
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/ 63
STEP TOWARDS SUCCESS
AKASH’S
Guru Gobind Singh Indra Prastha University Series
SOLVED PAPERS, |
(PREVIOUS VEAR SSTION PAPERS)
[B.Tech]
THIRD SEMESTER
Digital Logic and Computer
Design (ECC-207)SYLLABUS
DIGITAL LOGIC AND COMPUTER DESIGN
PAPER CODE : ECC-207
Instructions for paper setter:
1. There should be 9 questions in the tert
2. The first (1st) question should be com)
question should be objective, single line answers o)
total 15 marks.
3. Apart from question 1 which is compulsory, rest of the paper shall consist of 4 units
{ as per the syllabus. Every unit shall have two questions covering the corresponding
weit of the syllabus. However, the student shall be asked to attempt only one of
the two questions in the unit. Individual questions may contain upto sub-parts /
Sub-questions. Each Unit shall have a marks weightage of 15
UNIT-1I
Boolean Algebra and Combinational Logic: Review of number systems »
signed, unsigned, fixed point, floating point numbers, Binary Codes, Boolean algebra —
basic postulates, theorems, Simplification of Boolean function using ‘Karnaugh map and
Quine-MeCluskey method ~ Implementations of combinational logic functions using
gates, Adders, Subtractors, Magnitude comparator, encoder and decoders, multiplexers,
ease converters, parity generator/checker, implementation of combinational circuits
using multiplexers.
1m end examinations question paper.
pulsory and cover the entire syllabus. This
1r short answer type question of
UNIT-II
Sequential Circuits: General model of sequential circuits, Flip-flops, latches, level
triggering, edge triggering, master slave configuration, concept of state diagram, state
taife, state reduction procedures, Design of synchronous sequential circuits, up/down
wea modulus counters, shift registers, Ring counter, Johnson counter, timing diagram,
aeval adder, sequence detector, Programmable Logic Array (PLA), Programmable
‘Array Logic (PAL), Memory Unit, Random Access Memory
UNIT - II
Basic Computer organization: Stored Program, Organization, Computer
| registers, bus system, instruction set completeness, instruction cycle, Register
Transfer Language, Arithmetic, Logic and Shift Micro-operations, Instruction Codes,
Design of a simple computer, Design of Arithmetic Logic unit, shifter, Design of a
simple hardwired control unit, Programming the basic computer, Machine language
instructions, assembly language, Microprogrammed control, Horizontal and Vertical
Microprogramming, Central Processing Unit, instruction sets and formats, addressing
‘modes, data paths, RISC and CISC characteristics.
UNIT -IV
Computer Arithmetic, addition, subtraction, multiplication and division algorithms,
put Organization, Modes of data transfer, Interrupt cycle, direct memory
Input-Output processor, Memory Organization, Memory Hierarchy, Associative
| Cache Memory, Internal and external Memory, Virtual Memory.FROM ACADEMIC SESSION [2022-23]
THIRD SEMESTER [B.TECH]
DIGITAL LOGIC AND COMPUTER DESIGN (ECC-207)
UNIT-I
| Q.1. Explain the simplification of switching functions using Karnaugh
Map and Quine Mc-Clusky Methods.
‘Ans. Karnaugh Map Simplifications: The karnaugh map is a gra
‘manipula!
representation that provides systematic method for simplifying and
Boolean expressions, This technique isthe mort erenivel edn fs Smeaton
lean functions. Fig. shows the 2 variable, 3 variable and 4 variable K maps.
| For an variable K-map 2° cells are required. Each cells corresponds to one of
the combination of minterms (or) maxterms of n
combinations for n variables. For a 2 variable map, four (2) 4 cells are required.
Similarly for 3 variables, (2) 8 cclls are required ta construct the 3 variable map, Gray
code is used to identify the cells, the direct binary combinations of 2 variables is 00,
01, 10, 11. As a result of the coding, cells which have « common
the combinations that differ by the value of just a
(00, O1, 11, 10) to
LP. University-[B.Tech|~Akash Books 2021
is difficulty, we use Quine-Me Cluskey method.
viable for problema where the number of variables exceeds four. he
ication of Boolean function by using Tabulation
‘This method is
following steps are followed for simpli
‘method.
‘Step 1- List all minterms in equivalent binary form
‘Step 2. Arrange the minterms based on the number of 1's
Stap 3. Compare each binary number from one group to other and if they difer by
nly oe bit povition put-(dash mark) and copy the remaining term, Place tick (3) mark
after each comparison,
prea a Apply ike mas proeace deecrbed in etop 3 for the renubtant column apd
continue these eyoles wntil a single pass through cycle yields no further elimination
itterals,
‘Step 6. List the unticked prime implicant and form t
Each prime implicant is represented in a row and euch minterm in a column. “he
rose mark (n)are placed in each row to show the comparison of minterms that make
the prime implicant from this chart we can simply the expression.
" (@ Search for single x column and select the prime implicant corresponding to that
he prime implicant chart
“dot by putting the star mark in front of it.
Gp Search for multiple dot columns une by one. Ifthe corresponding mintsrm,
in the final expression ignoring the minterms and go to next multi dot
‘otherwise include the corresponding prime implicant in the final expression
(2014)
‘Ans, DeMorgan's Theorem: DeMorgas's theorem are very important part of
an ‘DeMorgan suggested two theorems
{L The complement of a product is equal to the sum of the complements.
‘truth table for Demorgan's theorem 1
[AB = A+ 6)
“Table. Truth table for Demorgan’s theorem 1.
Alelas|4.BlA+8
ofojitay ) ft
ofifijoy 1 | 1
ajojojij 1 | 4
ijijojo| o | o
to any number of variables or combinations of variables.
AsBs
‘AB +CD + EFG+...
p ‘of a sum is equal to the product of the complements.
for Demorgan's second theorem
fAvB- A.B4-20: i
21 ‘Third Semester, Digital Logic and Computer Design.
‘Table: Truth table for Demorgan’s second theorem
4|8 428 [48
eee 1a
lo — © -|e!
are |
This
law can be extended to any number of variables or combinations of variables.
For example.
AeB+C+De. =
‘ABsCD+EFG>.. = AB CD.EFG-..
Q.3. Draw the logic diagram of 3-bit parity generator and respective truth
table. . (2014)
it of a ‘0’ or a‘I’is attached to the data bits such that total no. of I's
bit can be attached to the
A.B.C.D.
LP. Universtiy-{B Tech]-Akash Books 2021-5
Q.6.(a) Implement using 8:1 multiplexer: (2015)
F(AB,C,D) = Em (24,5,7,1014)
5, 7, 10, 14) we have to implement
that F (A, B,C, D) = Em (2, 4
‘Ans. Given,
wt A te ued as an input and B,C,D are as selection lines, then
using 8 x 1 MUX.
imptementation table is
we ee eeage:
io 1 @3 ©@
A @ 1 2 3 4%
ee a a
eet
i
“ Beco
Q7. Find ‘essential prime implicant in the given equation:
F (WXYZ) = Em (0,2,4,5,6,7,8,10,13,15)
‘Aus. Given that F (W, X, Y, Z)= 5m (0, 2, 4, 5,6, 7, 8, 10, 13, 15)
Bait 92 yz yz
7
a
T Yel
7a]
(2015)
encoder is a combinational logic circuit It is reverse of @
Tnput lines and‘n’ output lines. An encoder accepts an active
imaV/octal digit and converts
‘representing a digit such as « deci62021
‘Third Semester,
» Digital Logic and Computer Design
LP. University-(B Tech|-Akash Berks wm
A= MAMA,
B= BRAD.
aA
Hhennt digits arn ecqual ie A
‘The 2 numbers are equal if all pairs of
1h, A, = Band A, = By
‘The equality function of each pair of bits can
‘equivalence function
be exprenead logically with an
n= AB ASB,
i = 01,2,5
Where x, = 1 only if the pair of bits i pom
are 0's.
For ths equality condition to exist, all x, variables mur
‘an AND operation of all variables
(A=B) = 334
equal to 1 only if oll pais of digits of the oo members
(ioe i we orpual ie. if both ae
oo eo bitho
Te
convert it into octal smb, pouring ears re ght o left inthe form of
insect the relation magpsitacien sf
M the we Saget
(A>B) = AB +248 +A 8) ee
(AB) = AB
(A=B) = AB+AB=A08
AB) = AB
A s
a8
ass
D—*:12-2021 reise
co hird Semester, Digital Logic and Computer Design
@.25. Add - 10 with -10 using 8-bit arithmetic 2's complement method? ra:
Ans, (10),. -» (00001010), oon . 7 ; : ae
- amen, 1 f : 7 ‘ °
5 2 o °
(10, ——e @) 1111 0110 4 ° 1 . 7
‘ ° 1 °
11101100 . es 0 1
6 o 1 Fs
Carry be ignored 1 o 1 1 1 }
(11101100), -+ 2's complement of addition of ~ 10 and —10 in 2's complement form, 8 : p be ;
Q.26. F(A, B,C, D) =5(0, 1,2, 5, 7,849, 10, 14, 15). Find all the pri 1 o ° 1 °
) + 2,5, 7s! prime implican\ 2
‘essential prime implicants and minimal SOP expression. ich 10 1 o 1 - 4
Ans. FIA,B,C,D) = 30,1, 2,5, 78,9, 10, 14,15) un 1 ° : . ;
1 1
1 1
1 1
1 1
ists of XX, and Y consists of
2017)
tqo bit umber X and Y. X consi
‘with three outputs Z,, Z, and Z, such that:
(ii) Z, = Lwhen X=¥ (iii) Z, = 1 when X>Y14-2021 ‘Third Semester, Digital Logic and Computer Design
‘Ans. Truth : it
table for 2 - Bit Magnitude comparator. LP. University-1B Tech|-Akash Books 2021-15
@.30. Why is the ASCII code a 7 bit code? 2010
sndard code or Information Inter change (ASCID pronounced
basically a 7-bit code. Since the
‘Ans. The American stat
tas ASKEE' is a widely used ulpha numeric code. This is
hat can be created with T-bits is 2" = 128, the ASCII
oo000
0001 0 { 4 number of different bit patterns t
0010 ° : ° mer ot to encode both the lowercase and upper ease charactrs of the alphabet
of oo . : 3 can tol) and ome special synbls ax well, adtin to the 10 decimal dita
o1o4 3 A 1 (oa oad exiensively for printers and terminals that interface with small computer
orto ° fr ° systems.
Saface 2 1 2 {Q5. What are the two basic form of the Boolean expression name them?
too B o : aan)
o o
eto : : 3 Po is caean egrenin oe
+400 ° a 9 (Sum Of Product (SOP) Gi) Product Of Sum (POS)
tito 9 ° 1 52, Realize EX.OR gate using minimum number of NAND gate only.
raiie ° io 2017)
yaad : ° ;
Ans.
35. Simplity the given Boolean expression and implement it with NOR
‘gor
gate circuit only F = AB + ABD + ABD + ACD + ABC
10}
P= a+BC+ACD
the essential prime implicants?
jor rectangle made up of the bunch of adjacent minterms
Hof these subcubes is called a prime implicants (PI). The Pl which
“which cannot be covered by any other PI is called an essential
2017)
‘the following function using K-map
2, 6, 8,9, 10)
5, 7,9, 12) + 400, 1.6)LP. University (B Techi-Akash Books
6-201 tl Logie and Computer Design
Awe F (4) Fy S248, 7,8, 120+ 10, 1,6 —
oo aes
=~ oo = ce
~ a
| a) Tha
nhakat
F,= AcD + BCD + ABD F,= AB + BCD + AD + BCD
Q.35. Obtain the decimal equivalent of the given hexadecimal number
(2017)
3x 16! + 10.» 16" + 2x 16 + 15» 16"
= 48-1062. 2% - 58+ 0.125 + 0.058 = (68.183
48109 5 oy Os (58.183),
ed
weds
abe
ebede he
Cond
‘he truth table for BCD to 7 segment decoder
fer common cathede T-segment display If Tserment
Nariver output must be active LOW to giow the
type T-segment display. the segment driver must
“Table shows the truth table for BCD to 7-segment2021-19
LP. University-1B Tech|-Akash Books
‘Third Semester, Digital Logic and Computer Design
18-2021
‘Table truth table common cathode 7-segment display.
vs Ht
= 8 pRae om 4
=... ome ts ica x fT
aie - “otal 8
d
Logic diagram: Fig. shows the logic diagram of BCD to 7-segment display decoder/
condition for these corresponding cells,
Kemap Simplification
Fors
e=A+ C+ 80+ 80
co
A8\_ co.20-2021 ‘Third Semester, Digital Logic and Computer Design.
Q.38, Realize the half adder circuit usin,
ae minimum number of NAND pu,
el (e017,
S=A@B, crap
938. Add (97),, + (34), using BCD codes,
Ans. (97),, + (34),,
201s)
BCD representation (97),, + 1001 0111
(34),, > 0011 0100
1001 om
+0011 ono
TET TTOIT — Wo. erate 80D cose
‘To make it valid BCD code add (0110),
100 1011
+010 _on10
‘Too oor
(0004 0011 0001}seo
Q.40. Realize F =
ates,
Ans. Pe
‘Take bar on above expression,
XY" +XZ+ YZ’ using minimum number of two input NOR
201s)
AY + Ra eve
1-21
University-{B.Tech|-Akash Books -
= X¥+ zs vz
= XV+%Z2+2
= (X+¥)(x+2)(F +z)
Q41. The minimal sum of product is given by Seon
F = AC +AD+BD
Pind canonical §.0.P and canonical P.0.S
‘Ans, F = AC’ + A'D + BD, Minimal sum of product form
o 1 1 _w
00] 113
offs |
st a2] aa
a
Canonical SOP form = ABCD + ABCD + ABCD + ABCD + ABCD +
ABCD + ABCD + ABCD + ABCD + ABCD
Canonical POS form = (A + B+C+D).(A+B+C+D).(A+B+G+D).
(A+ B+ Gs d)(A+B+ E+ d).(A+B+C+d)
Q.42. Simplify F(A, B, C) = 5 m (0, 1, 2, 5,6, 7) using QM method. (2018)
Ans FIA, B,C) = £m (0,1, 2,5, 6, 7) Using QM. method22-2021 puter Design
=a TOTS e TT
Pp
op te te
Thee St ast
fer [ua 2 [ae | RE er te
Fig. ‘
Q.43. Draw and exp!
subtractor. 2018)
Ans. Here the addition and subtraction operations are combined into one circuit
with one common binary adder 3s done by including an X-OR gate with each full
adder. The mode input M controls the operation. When M = 0, the circuit is an adder
and when M = 1, the circuit becomes a substractor. Each X-OR gate receives input M
and one of the inputs of B. when M = 0, we have B @ 0 = B. The full adder receives the
value of B, the input carry is O and the circuit performs A +B. when M = 1, we have
B@ 1= and, = 1. The B inputs are complemented and a 1 is added through the input
carry. The circuit performs the operation A plus the 2's eomplement of B,
Logic diagram of a 3-bit Binary Adder/Subtractor
‘in the circuit diagram of 3-bit 1's compliment adder-
Q.44, Implement three input XOR gate using 2:1 MUX and basic gate
Ans. Truth Table for 3-input XOR gate
F = A@BOC eS
Trpats [Output
A B ¢ F ca}
0 0 0] °
0 ° 1 eS:
9 H 0 1 F
o 1 1 0 ¥
(2018)
2021-23
=
oy: uaiersty-stecnt-Akeh BOO
ea el
3 i 5
: 0 1 0 + Fs
4 1 oO ° er
: 1
7 thete inputs as a peloct lines saat 2-FSEST
a]
t
I ae
Neen
oe
T il
ue} za Ss
nee saat
45, Using Kemap simplify expression, Y= f(A, B, C,D) = x(0, 1,2, 4,5; 8:9,
1» (2018)
Ans. Y = flA,B,C,D) = (0, 1, 2, 4,5, 8,9, 15)
input B?
he (2018)24-2021 ‘Third Semester, Digital Logic and Computer Design
00-05
LP. University-{B.Tech|-Akash Books
oT yoy rae
feos lean er [et] —
fico (aca ee ce]
fiona one ae oo]
eae ‘
Pet
Deo
Cpe toy
poetry
Coo
Doty
247. Design and important a Binary to Gray Converter,
Ans. Binary code to ray code converter: This code converter combinational
linory, Tas con, 2 Severt binary ta Gray code, Ths logus code of nde nna
tunary. The output code of cade converter is Grey ane
‘Truth Table
(2015),(2018)
“>
6,06 +DE=cod o
+r of Binary of Bit
We get the simplified boolean expression for the code converter of Binary of Binary
to Gray code
G, = BA+BA=B@A
G, = CB+CB-coB
G, = pé+Bc-ceD
=D
he ey epeiin we cn cnt ha inary a ry code converter
B «yg the above
as fol: «we Fig)
. 8 ‘he Binary code,
5 ae G, Bey code
Logie circuit for binary to gray code converter
ose. ngheas tas ngs agra MUX, F = im (1, 3, 5,
: P = tm(1,3,5,7) anteThird Semes
; ee a LP. University-1B:Tech!-Akash Books 2021-27
UNIT-I
1. Fxplain various types of sift registe or)
| ce ienitt Register: Aragstas ind ae. LF weed is Bare ied data. In shift
if ree pre are connected gether such Ut ata may babies 0 ‘and shifted out
Sc vaamx [eee | efttam cal a sit register This siting ‘cay bein serial form or parallel form.
P, ‘There are four basi types of shift register.
1. Serial ~ in serial out
2. Serial ~ in parallel out
3, Parallel in serial out
rao
+
ee ox ae:
i guserator civeul. oul ow f| Tse [+H
ori =
a (f are ore als m |
ee 2) oe os
pL o} tote * rm
T
Z ALE
Dy ate
[G4 7 qa. taplsin the process of state reduction and stare
cae ee
ey synchronous sequential cireuits. 2014)
‘Ans. State Reduction
eee eee te, ‘wo states are said to be redundant
Error in the data can be detected using Xi or equivalent, if every possible set of inputs
Reeae nines elecoae > Tae ey cate many be carrey generate exactly the same outputs and
the same next states, When two states are
This data c
ee ae an mcrae ie Bec nie sen of oa equivalent one of them can be removed
ob the rae pire t is important to detect such errors. Detection of such without altering input output relationship.
ee cag aa ng tional bit called ‘Parity bit’ that is to be added before Letus consider the state diagram as shown in
iecpaplareon ariginal dat. At the receiving sie, the parity bit will be used coal Fig. The states are denoted by letter symbols
tional bit will be truncated before oe the instead of their binary values because in
Q.50. Perform the following operations: state reduction technique internal states are
(@) BCS, -ASB,, (ii) 2018) importar mut input out sequences are
) BCS, ASB, , (ii) 23,+45, (iii) 10110,*1101,, sated ne a ee Fig. Example state diagram
Ans. () (BC Shy
em m @% cc 10110 ‘Step 1: Finding the state table for the given state diagram.
~038), a hg =1104
a ” sit First the given state diagram is converted intoa state table. Fig, shows the example
ata 7 0000 of state diagram,
101 10%«
Present state26-2021 ‘Third Semester, Digital Logic and Computer Design
‘Step 2: Finding equivalent states. The two present states go to the same next state
land have the same output for both the input combinations. We can easily find this from
the state table, states ¢ and e are equivalent. This is because both c and ¢ states go to
states c and d outputs of 0 and 1 for x = 0,x = 1 respectively. Therefore, the state # can
'be removed and replaced by ¢. The final reduced table and state diagram are given in
the table and Fig. The second row have e state for the input x = 1, it is replaced by €
because the states ¢ und ¢ are equivalent.
Table: Reduced State Tal
Next state T
Present state
x=0 “x=l x-0 xt |
Nha
%
Fig. Reduced state diagram.
Q3. Explain the working of serial adder. Draw the block diagram? (2014)
‘Ane. Serial Adder: The serial adder method uses only one full adder circuit and 8
storage device (flip-flop) to hold the generated output carry. Let A= A,_, A, A,and
B.-B._,B,_. .. B, be two unsigned numbers that have to be added to produce sum
8, The two number A and B are stored in the register A and register B
respotiively. The pair of bits in A, and B, (which are stored in right shift register) ere
{ranaferred serially, one ata time, through the single full adder to produce a sum and
carry and this earry is stored in the fip flop. The stored output carry from one pair of
bits 1 used as an input earry for the next pair of bits as shown in Fig. The addition of
two n-bit numbers starts from the least significant bits and progresses step by step 1@
the moet signifeant bits in different time sequences. Initially the D fip-Sop is cleared
thy Ae
oar “
Posie Ee wigig Neqaive Ege Tageing
Fig. (4) Logic symbol of positive and negative edge triggered of D flip flop.
When D = 0, and the edge detector senses a positive edge at the CLK input, the
output of the lower AND gate steers a low going pulse to the RESET input of flip flop,
thus storing a 0 at Q. When D = 1, the upper AND gate is enabled. The edge detector
sends a high going pulse to the upper steering gate, which transmits a low going SET
pulse to the output of flip flop. The action stores a 1 at Q.
‘Table 1: Truth table of edge positive triggered D flip flop
CLK D &
° 0
1 1
Q6. Compare the design features of synchronous and Asynchronous
Counters. Give an illustration for each. 201)
‘Ans. Asynchronous Counter: To design an asynchronous counter, the number
of flip-flops required depends on the number of states. The maximum number of state
of a counter is 2%, where n is the number of flip-flops in the counter. If we have two fip-
flops, the maximum possible number of output states of the counter is z* ie., 4. In this
case, all the flip-flops are not clocked simultaneously. Example of 3-bit asynchronous
up counter is shown below.
to alana? &
| Ym &
Synchronous Counter Desi
(i) Find the number of flip-flops required.
we in the tabular form,
(ii) Write the eount seque
) Determine the flip-flop inputs which must be present for the desired next state
from the present state using the excitation table of the flip-flops.
(iv) Prepare k-map for each fip-lop input in terms of fip-Mop outputs as the input
variables
LP. University-1BTech|-Akash Books 2021-81
{in the minimized expressions.
(y) Simplify the k-maps and obtai
flipflops and other gates corresponding to the
(vi) Connect the circuit using
minimized expressions
mchronous counter is shown below.
aati
ap a, (488)
1 Ol {roe
ee
cu:
Q.7.A sequential circuit with two D flip-flops A to and B, two inputs and
me output zis specified by the following next state and output equations:
Atte) = xy ed
Bit+1) = xB+xA
2=B
(i) Draw the logic diagram of the circuit. 2
(di) Derive the state table. @
i) Derive the state diagram. 2s)
‘The next state and output equation are as follows: oid)
Ae) = xy 4x0
Bit+}) = xBexA
2=B
‘Ans. (i) The logic diagram is as follows:32-2021 ‘Third Semester, Digital Logic and Computer Design
Gi) The state table is as follows:
LP. University-{B.Techt-Alcash Books
Deion ht arachronens cote satel
4-bit asynchronous counter, counts 0000
MOD-16 coumtar. ter, counts 0000 to 1111, .¢. 16 states; it is also called
‘The simplest possible shift register i
‘The G output of the given flip-flop is connec
Bach clock pulse shifts the contents of
serial input determines what goes in to the lef
Gutput is taken from the output of the right most fip-Alop prior
pulse. Although this register shift
own. We find that the register shi
register can function either as a shifl-right or as shifl-left register
seg_s_f a
\aeea
to 2a as
Q.10, Explain SR Flip flop sing diagram and truth table.
‘Ans. SR flip-flop using NAND gate
(2015)
of the flip
reso [tapas Next State ‘Output
x ® = y ‘ [ap
eo Flop and explain how it works using truth table.
lop can be converted to D Flip Flop. Geta
‘Aus SR fip-op using NAND gate ap
D gates 3 and 4
ind 4 stay at CLK—
the “no” change” condition
023 Design
‘Show how an R Pi
The output of NANI
oxic level This
othe basic ip op
u
1. When clock pulse = 1 a
The § or R
“ ‘input is allowed to re : ane
plain Using truth table a eh the output. Now the effect of SR flip for
ux s
c : R Qu,
1 o , a
1 ° ‘ °
1
| 4 0
1 1
1 not used
LP. University-1B:Techl-Aash Books oat
Conversion of SR into D
° a
xb Sty
[aes ts
(2017)
Q.24, Discuss types of shift registers.
Ans. Classification of Shift Registers
La
1. Shift left register
sification based on the direction of data movement
2. Shif right register 3. Bidirection shift register
IL Classification based on the mode of input and output
0
2. Serial in parallel out shift register (SIPO)
3. Parallel in serial out shift register (PISO)
4. Parallel in parallel out shift register (PIPO)
5, Universal shift register
125. What is PAL and PLA? Explain.
1. Serial in serial out shift register (SIS
(2014),(2015),(2016),(2017)42-2021
PLA
Both AND and OR arrays are programmable
Costliest and more complex than PALs and
PROMs,
AND array can be programmed to get desired
minterms.
Any Boolean function in SOP from van be
implemented using PLA.
‘Third Semester, Digital Logic and Computer Design
PAL
p——___FAL
OR array is fixed and AND array &
programmable.
Cheaper and simpler
AND array can be programmed to get
desired minterms
‘Any Boolean function in SOP from ean
bbe implemented using PAL.
——______ ae
4
cn ¢
L 1
| Proqramemnacie
‘AND yates
peo) per
pe
BA
rogrammwbe
AND gates
PAL circuits (Programmable Array Logic)
Q.26. Design a Delay Flip-Flop using S-R flip flop.
Ans. Step. Given flip flop is RS ip flop
Required flip flop is D flip op
Block diagram
LP. University-{B.Tech!-Akash Books
Excitation table of RS flip flop
2021-43
‘Next state
‘Step 4: K-map simplification
Flip fop inputs
3 for K-map
‘The required flip flop inputs and present state are considered
simplification,h Books
LP. University-1B-TechI-Akas!
44-2021 Third Semester, Digital Logic and Computer Design oe
Example. Convert the RS flip flop to T flip flop. on
‘Step 1: Given flip flop is RS flip flop
Required fp op is Bop
Fe
state
Step 2: Truth table of T flip flop 2s. a sequential icon has re peel _ one ae ton
Flip flop input | Present state] Now vinle SS a ee a
T Q Qu
0 1 =i 1
7 7 d
27, Design « MOD-8 down asynchronous counter. 2016)
‘Ans. Mod-8 down asynchronous counter
PS. NS Gy ©)
+
001 000 @)
fig | at
ee @)
fae ee
10 101 (aye
1
ana‘Third Semester, Digital Log c and Computer Design
(i) Design using D-Gip flop: For the design of circuit using D flip flop (or any flip
flop), we need the excitation table. Table (b) shows the excitation table of Dflip flop from
which we can develop excitation table for the required circuit as shown in Table (c)
‘Table (b) Excitation table table for D-fip flop
[Preventstte | Neststaie@, | Flip FepinpwiD |
| Oa o
The fip-Hop input function and the circuit output functions are obtained by using
K-map simplification ms
Input equation (or) function for flip flop A(Z,) | © \\_oo__ox__1
DA = ABx+ ABz + ABE + ABx oT fa
= A(Bx+ Bz)+ A(Bz + Bx)
Considering 2 = B+ Be, then Bz+Br=7
‘Simplify the above equation
D, = Aes az
A@z
Substitute z= Bx+ By = B@ in the above equation
(D,= Ae Be:
input equation lore top B (Dy)
LP. University-{B.Tech|-Akash Books 2021-47
‘The input equation for flip Nop and output equation are summarized us follows
D-A@BOx —Dy= ABs ABs y= A+ ABs
‘A vequential circuit using D flip-lop is obtained by using above equations as shown
in Fig. (b).
y
Fig, (b) Sequentia! logic diagram using D Mip-feo
Q.29. Explain JK flip-flop with the help of truth table, characteristic
‘equation and waveform. ‘ 2017)
"Ans. JK flip Flop: It is used to remove the invalid condition of S-R Flip-Flop. The
logic diagram and truth table is shown below.
ax] [eyen
’ - oTeey
1 folol ae
ox 1 Joli] o
Le fe ttel a
5 : riihs
Q.30, Design a synchronous BCD counter with JK flip-flop.
‘Ans. ABCD counter is nothing but « mod-10 counter It has 10 states
(0000 to 1001 } It requires n = 4 ip Bop
Ps
20,0, 0,
:2017)
ooo
00
00
00
on
on
o1
ot
100
10042021-49
verity 1B. Tecl-Akash Book
48-2021 Third Semester, Digital Logic and Computer Design Lp. Us
= 9, Ans.
"| ae on 9»
Fig. Logic Diagram for synchronous BCD counter using JK Flip-Flop
Q31. How ring counter will be converted in to Johnson's counter. (20!
sal input the resulting cites
aut
‘cuit is defined by the function F, « Sanit, 6 Th
wit
jrowit with «PLAee a
ta} Logic and Computer Design
'
Master Slave J K flip flop and al
Tow is it different from the aig]
(2017)
the state of an S-R FLIP-FLOP wag
ro je can be eliminated by converting it intend]
ar ed which are ANDed with @ and Q, respecting |
‘Third Semester, Dist
circuit diagram of ©
fhe help of truth table,
FLIP-FLOP The data puts
to obtain Sand R inputs i.e,
8-4
R=KQ @
AA FLIP-FLOP ths obtained is shown in Figure 1. Its truth tablet ge
ein ih nredacd to Table 2 or convenience, Table 1 as been prepared fra
Ta Ln einatins oJ and K input, and french combination both th a
ith orpat have ben considered
Pp
5-0 cd
i
ae | 8
é Bo FF
Fig I: An $-R FLIP-FLOP Converted into J-K FLIP-FLOP
Table 1: Truth Table for Fig. 1
|
SERS
2021-61
LP. University-{B Tech|-Akash Books
‘Table 2: Truth table of J-K FLIP-FLOP
F Lage Spm of
Ask rute-roe Una Goer rarer
‘The Race-Around Condition: The difficulty of both inputs 1(8 = = 1) being
ot allowed in an S-R FLIP-FLOP is eliminated in a J-K FLIP- FLOP by using the
feedback connection from outputs to the inputs of the gates G, and G, figure 2, Table 1
dnd 2 assumes that the inputs do not change during the clock pulse (CK = 1), which is
tot true because ofthe feedback connections. Consider for example, that the inputs are
wT and Q=0,and a pulse as shown in Figure 218 applied at the clock input. After
‘time interval at equal to the propagation delay through two NAND gates in series,
the output will change to Q = 1 see fourth row of Table 2. Now we have J= K = 1 and
Qu land after another time interval of St the output will change back to Q = 0. Hence,
we conclude that for the duration t, of the lock pulse, the output will oscillate back and
forth between 0 and 1. At the end of the clock pulse, the value of Q is uncertain. This
situation is referred to as the race-around condition.
ES] Trilling (oom)
t
aS =
—
‘Leading (positive)
edge
°
Fig. 2: A Clock Pulse
‘The race-around covditinn can be avoided if, |
ae
of
cee
’
When CK = 1, the first FLIP-FLOP is
5 rable 1. we obtain may
enabled and the outputs Q, and Qy, respond Ree Tah 4J, and K, are shown in Figure 1. From the K-maps the
btisleranticl Rasa ae ee The Knap for dy Ky J 28
this time, the second FLI P-FLOP is inhibited a ree ia @.0
FL ’ ia a Jn= Ky = QQo + MA
because its clock is LOW (GK = 0). When CK ae Sin = oll 2 SoM ties the above expressions
fees LOW (CK = 1), the first FLIP-FLOP CK ——ap> 4K ‘The counter circuit can be drawn using
is inhibited and the second FLIP-FLOP is x 0 SMe: uw
oo
enabled, because now its clock is HIGH (GK aS
= 1). Therefore, the outputs Q and @ follow esl LE]
the outputs Q, and Gy , respectively (second alfa
sand third rows of Table 2), Since the second i
FLIP-FLOP simply follows the first one, it Fig. 4, A Master-Slave J-K fig uff
is referred to as the slave and the first one Slop logic aymbol :
as the master. Hence, this configuration is -
referred to as master-slave (M-S) FLIP-FLOP.
In this circuit the inputs tothe gates Gy, and Gy, do not change during the cod
ulse, therefore the race-around condition does not exits. The sta ¢ of the master-slave ee ai
FLIP-FLOP changes at the negative transition (trailing edge) of the clock pulse. The i
lomic symbol of« M-8 FLIP-FLOP is given in Figure 4, At the lock input trcainal til
symbol > is used to illustrate that the output changes when the clock makes a transiti#®
‘and the accompanying bubble signifies negative transition (change in CK from 1 10 0)
Q.36. Design a 3 bit binary UP/Down synchronous counter with direction olf
control signal M when M = 0 for up counting and M
Ann. The count sequence is given in Table 1 For M= 0,
for M = 1as a DOWN counter ‘The number of FLIP-FLOPS
the FLIP-FLOP
tare determined in a similar m
eae ai hae as
tsasanU
= 1 for down counting.
2017)
unter and
equired 18 8. The inputs of54-2021 Third Semester, Digital Logic and Computer De. :
et Design
.37-Replain the working ofsril in an serial out shift equ
diagram and wave form. i mi
Ans. Shift Register: A 5-bit shift “
register using five master-slave $-R (or J =
FLIP-FLOPS is shown in Figure 1. This circuit can be used in any ofthe four
operation of this circuit is ex
‘plained by assuming the 5-bit a
S-bit data, the operation will be similar to the one pial 10010. Fe any otal
Panel outputs
read Se |
‘mpus’ AMS] D5 TD, JD,
Preset
cable +
Clear
Chock
Fig. 1: A 5-bit Shift Register (7496)
sea apt
ate RaMESiO eae _ serial form is applied at the serial input after
serene FPR Ratan ndsagaes re
ut and output waveform are illustrated Fig?
LP. University-{B:Tech}-Akash Books 2021-55
‘The process of entering the digital word starts with the data input corresponding
tothe leeptaipnicant bit (0) at the serial input and frst clock pulse, Atthe falling edge
(CD of the frst clock pulse the output of FF4 (Q) will be 0 and the outputs ofall other
FLIP-FLOP» are 0 since their inputs are 0. Next, the input corresponding to next bit is
tpplied and at the falling edge (T,) of the second clock pulse, the FLIP-FLOP outputs
will be
ora
Q, = Q2=Qi=Qo=0
Similarly, the input corresponding to each bit is applied til the MSB and the bits
0 on shifting from left to right at the falling edge of each clock pulse as illustrated in
Fig 2 At the end of fifth clock pulse, the outputs of FLIP-FLOPs are which is the same
as the number to be stored. The number of lock pulse required for entering the data,
is the same as the number of bits. ‘The process of entering the data is also referred to as
‘writing into the register.
qer
Q=0
qe1
at
=0
‘The data stored can be retrieved (also referred to as reading) in two ways: serial-
‘out and parallel-out. The data in the serial form is obtained at Q, when clock pulses are
applied. The number of clock pulses required will be same as the number of bits (five
in this ease.
In the parallel form, the data is available at Q, Q, Q, @, Q and clock is not required
for reading, In the ease of serial output, after the nth clock pulse, for an n-bit word,
each FLIP-FLOP output is 0. This means that once the data is retrieved the register is,
empty. On the other hand, in the ease of parallel output, the contents of the register can.
be read any number of times until new data is stored in the register.
The clock rate may be different for the input data and the output data in ease of
4 serial-in, serial-out shift register. Hence, this method ean be used for changing the
spacing in timeof a binary code which is referred to as buffering.
Parallel Input: Data can be entered in the parallel form making use of the preset
inputs. After clearing the FLIP-FLOPs if the data lines are connected to the parallel
inputs (D,,. D,, D,,, D,, and D,) and a 1 is applied at the preset input, the data are
‘written into the register. This is referred to as asynchronous loading,
‘The stored word may be read in the serial form at Q, by applying five clock pulses
or in the parallel form at Q outputs.
‘The data can also be entered in parallel form by using D-type FLIP-FLOPS connected
485 shown, The data is loaded when a clock pulse is applied and hence, it is referred to
4s synchronous loading.
Q38. An a synchronous sequential circuit is described by excitation
Y= X,X, + (X,X,)¥ and output function Z = ¥_
(i) Draw the logic diagram of the circuit. (ii) Derive the
and output (iii) Obtain the two state flow tables.
Ans, Y = X,%)+O,k¥
Ze¥56-202
21 Third Semester, Digital Logic and Computer Design
tae} —
ys
vez
Fig. Logic Diagram
Table: Transition Table an
corresponding output
Stable state
2. Memory
3. Slower than combination circuit
44. Designer has more flexibility.
9, No need of memory element
3.Faster is speed.
@:40, Design a MOD - 6, synchronous counter to count
‘Use T flip-flops.
"ans. This counter has only six stable states, but it reqs
2021-57
iversity-[B.Tech-Akash Books
Ans.
Output is depends only on pres
Sequential C
resent input and
the sequence 0, 5,
(2018)
jires three FFs.
Y 00 on "
' | G4 ontie suse
K-Map from Transition Table (uncircled)
Circle shows stable state. And the rest (uncircled) is unstable state.
ey
Se 00. aN ace
o] o o °
Output is mapped for all stable states, for unstable states output is mapped
unspecified.
Q.39. Differentiate between combinational logic circuit and sequential
logic circuit. (2015),(2018)
ecounoo Oly
eorco #
Required Excitations
Em oh
feet
tread
oe ocean
doo
ha mop
(Wee Cg!
$9
Fo or nw
°
1
Te= Q,Q5 + @,Q,‘Third Semester, Digital Logic and Computer Design
LP. University-IB Tech-Akash Books 2021-569
Ans.
‘SRAM DRAM,
"The memory cell is essential a latch | Memory cell that stores data in the form of|
can store data indefinitely, as long as | charge on a capacitor.
the DC power is supplied
Duration of retaining data islong, | Cannot retain data long
a Higher in spced to perform operation | Leas speed as compare to SRAM
Tess storage capacity as compare to| More storage capacity
- DRAM
a PROM EPROM
Chip is one time prograramable Chip i reprogrammable
Tnexpensive Costly as compared to PROM.
Storage high Low storage
141. What is Johnson counter? ;
1 eccauee aoe iy nig) 7 Q.43. Design a Mod-5 asynchronous counter using T-FF.
‘Ans. Johnson Counter: It isa variation ofa shift register counter. n this counter, ‘Ans. MOD-5 Asynchronous counter using'T-FF: A mod-5 counter has fve stable
the complement of the output ofthe last flip-flop is connected back to the input of the | states 000, 001, 010, 011, 100. when the fity pulse is applied the counter temporily goes
first fip-op. This counter have basic counting cycles of length 2N, where Nis the 1 101 state, but immediately resets to 000 because of the feedback provided.
numberof fip-lop. The logic circuit of 4-bt Johnson counter is shown below. R= for 000 to 100, R-1 for 101, and 110 and R'=X for 111
a, z R= QQ, + QQ, + Qi QQ + = (SA +)
ss ‘After State R
s 2, a .
a Oy Pulses @ Q Q
° 0 0 0 °
a} J ene [aso ao |
TableofR [2 ° rl ° °
ux 3 ° om a oo
ne + i ° °
ith Table 5 3 =
1 z °
ri 1
Ieee aoa ap
QA2, Distinguit
between (i) SRAM and DRAM (ii) PROM and EPROM.
2018)
|a a
60-2021 ‘third Semester, Digital Logic and Computer Design
QUA, Design a 2-input output synchronous sequential ei i *
produces an output 2 = 1, whenever any input sequence ~1100, 1010 Which LP. University-IB:Tech]-Akash Books 2021-61
erode tthe circuit resets to the intial state after output reaches 1," 1% [Present State Q,@,@, |_Next State Q°Q°Q," cama
A 2014), |
‘Ans. (i) The following state diagram can be obtained for the required fungi eae ene
ruired funetin, 000 000 °
oo 010 °
o10 100 °
ou 0
1
0
o
Exciting Table
PS. NS. Flip-Flop inputs
a0 =o Fo
[2.0 [0°05 gare ee ee |
000 | 000 or [0 Xp0 Xk oak aa
oor | 010 on |o.X anxaxedg eee eee
“oor 100 101 1 £34.02 Pee
on no on. |. x x 0x10 = eter
100 | 000 oo |x 1-0 X 0 x X a0) eae
ror_| 000 on |x 270) xox Se
‘After solving k-maps we get
+ Q)Q K= E+ QWs
= (e+ HI k= E+ QQ
(Q,+Qx = F
n6 this, fllowing state table can be obtained62-2021 ‘Third Semester, Digital Logic and Computer Design
UNIT-IL }
‘point in the IEEE standard format for the given _
(2015)
Q.1. Represent the floating,
number 1.00010100 x 2-7
Ans. The IEEE 754 single precision representation is given by
1 00010100, 10000000000
1 bit 8 bits 23 bits
8 E M
Q.2. Represent the following conditional statement by two register transfer
‘statements with control functions. (2015)
If (P = 1) then (Ri -> R2) else if (Q=1) then (RI — R3)
Ans. P: R1« R2; If(P = 1) then (Ri « R2)
PQ: RI « RB; else if(Q= 1) the (RI « RS)
Q3. Starting from an i value of R = 11011101, determine the
sequence of binary values in R after # logical shift left, followed by «
circular shift right, followed by a logical shift Right and a circular shift left.
(2015),(2016),(2018),(2019)
Ans. Starting from an initial value of R = 11011101, determine the sequence
of binary values in R after each operation in the sequence: (1) a logical shiftleR, (2)
followed by an arithmetic shift-right, (3) followed by another arithmetic shift-right, and
(4) followed, finally, by « circular shift-left. Show all your work
Loft shift (11011101) leads to 10111010
Arithmetic Shift Right (10111010) leads to 11011101
Arithmetic Shift Right (01011101) leads to 11101110
Circular Shift Left (00101110) leads to 11011101
Q4. Explain what operation will take place when the following instructions
are executed LX1 rp, data; LDA addr, LHILD addr & STA addr 2015)
‘Ans. LXI rp, data (Load register pair immediate) Lrp]
Bifecive address would therefore be in R1 = 200
(@) Indexed addressing with Ri as index register: There are several possible
indexed addressing modes but in this case (there is an address field) it is co called
“indexed absolute” addressing.
In indexed absolute addressing the effective address is calculated by taking the
contents of the address field and adding the contents ofthe index register.
Effective address would therefore be 400 + R1 = 400 + 200 = 600.
Q.15. What is an instruction format? Explain different types of instruction
format? (2016),(2016),(2017)
‘Ans. [tis the function of the control unit within the CPU to interpret each instruction
‘ade and provide the necessary control functions needed to process the instruction The
bits ofthe instruction are divided into group called fies. The most common fields found
found in instruction formats are:-
1. An operation code field that specifies the operation to be performed.
2. An address field that designated a memory address or a processor register.
3. A mode field that specifies the way the operand or the effective address is
Pea
Opts [Wade [nase]
Computers may have instructions of several different lengths containing varying
umber of addresses. The number of address field in the instruction format of a computer
depends on the internal organization of its registers. Most computers fall into one of
three types of CPU organization,
() Single Accumulator organization ADD X AC @AC + M [x]
(2) General Register Organization ADD R1, R2, R3 R® R2 + RB
(3) Stack Organization PUSH X
‘Three address Instruction: Computer with three addresses instruction format
‘an use each address field to specify either processor register are memory operand.
ADD R1,A,B AL@M [A] + M(B]
ADD R2,C,D R2®M(C}+MIB]_X=(A+B)*(C+A)
MULX, R1,R2_ M IX] R1* R2
whet Advantage of the three address formats is that it results in short program
evaluating arithmetic expression. The disadvantage is that the binary-coded
ns require too many bits to specify three addresses,
that the address fieldOO O—=—|-—“‘_—O_U
emg As
68-2021 Third Semester, Digital Logic and Computer Design
‘Two Address Instruction: Most common in commercial computers. Each a
field can specify either a processes register on a memory word. LP. University-1B.Tech|-Akash Books 2021-69
MOV R1A RI®MIAl Example: D,T,: PC _s—sW#—s(a_eee
70-2021 ‘Third Semester, Digital Logic and Computer Design
Modern computer systems often have multiple general purpose registers that
‘operate as accumulators, and the term is no longer as common as it once was. However,
‘a number of special-purpose processors still use a single ‘accumulator for their work, in
‘order to simplify their design
Q.19. What is the role of implied mode in addressing mode? (2015),(2018)
‘Ans. Implied mode: In this mode the operands are specified imply ae
definition of the instruction. For example, the instruction “complement accumulat 4
an implied mode instruction because the operand in the: accumulator register is. implied
Q.20. What is the transfer rate of an Strack magnetic tape whose a ie
Wht a 100 bene a
Ln a Mente einen mc Toion i
AW nana ack = 100 iach
Rotation Time = 120 inches/sec.
: eonses
‘Therefore, Transfer rate = 1600 « 120 = 19: ie
en Tn acto imprves wig pening? 0
ia eon
‘Ans. Pipelining is a technique used to improve the execution throughput |
a tcae
pan ting einen fet
- ‘The basic idea is to split the processor instructions intoa series of small independest
stages. Bach stage is designed to perform @ ‘certain part of the instruction. At a very
basic level, these stages ‘can be broken down into: |
+ Fetch Unit Fetch ‘an instruction from memory
« Decode Unit Decode the instruction be executed |
‘+ Execute Unit Execute the instruction
ea eee ee |
airal_| |
On a non-pipelined CPU, when a instruction is being processed at ® patty
stage, the other stages are at an idle state - which is very inefficient. If Yo
ii
LP. University-{B Tech]-Akash Books 2021-71
diagram, when the Ist instruction is being decoded, the Fetch, Execute and Write Unit
Gf the CPU are not being used and it takes 8 clock cycles to execute the 2 instructions,
‘On the other hand, on a pipelined CPU, all the stages work in parallel. When
the ist instruction is being decoded by the Decoder Unit, the 2nd instruction is being
fetched by the Fetch Unit. It only takes 5 clock cycles to execute 2 instructions on a
pipelined CPU. Increasing the number of stages in the pipeline will not always result
in an increase of the execution throughput.
Q.22. Represent floating point in IEEE standard format for given No.
1,001010...0x2"" and explain difference in Single precision and double
precision numbers?
(2015),(2019)
Ans.
ae = “—————
‘Sign of number 8 signed zoe
O signifi + in
nin —ransaa lon
representation
Value represented = 1. 2€'-127
(2) Single precision
(000101000001010
Value represented = 1.001010...2%7
(0) Example of a single-precision number
64 bits
ae ™
‘11-bit oxcass-1023 s2.bit
‘exponent smantigsa fraction
‘Value represented = = 1.M 2 1023,
‘Single Precision: The IEEE single precision floating point standard representation
requires a 32 bit word, which may be represented as numbered from 0 to 31, left to right.
* The first bit is the sign bit, S,
+ the next eight bits are the exponent its, E", and
* the final 23 bits are the fraction ‘F’
SEEEBEEEE FFFFFFFFFFFFFFFFFFFPFFF
o1 89 31
‘The value V represented by the word may be determined as follows:
‘+ IfE=256 and F is nonzero, then V=NaN (“Not a number")
+ 1fB=255 and F is zero and S is 1, then V=-Infinity
+ IfB=255 and F is zero and S is 0, then V=Infinity
* If 08255 then V=(-1)"*S * 2 ** (E-127) * (LF) where “LF” is intended to
‘epresent the binary number ereated by prefixing F with an implicit leading 1 and a
binary point.
* If EO and F is nonzero, then V=(-1)"*S * 2 ** (-126) * (OF). These are
lized” valuesa
72-2021 ‘Third Semester, Digital Logic and Computer Design
LP. University-{B Tech}-Akash Books 2021-78
+ If E=0 and F is zero and S is 1, then V=-0 i a
2 iii E mace ond Aston Yo Q24. Register A holds the S-bit binary value 11011001, Determine the B
Pry 5 i ‘and the logic micro-operation to be performed in order to change the
1990000000 00000000000000000000000 = 0 ee cinta ae
1.96000000 00000000000000000000000 = -0 om
bounitior
5 01 7
0 11111111 99000000000000000000000 a ee aa
111111111 90000000000000000000000, gee bape:
XOR oR
6.111111 0000010000000000000000 10110100, anor
111111111 00100010001001010101010 onion THnnOr
{6 10000000 60000000000000000000000 = +1 * 2°*(128-127) * 1.0 Q.25. What are the features of 8085 microprocessor? Explain addressing
{010000001 19199000000000000000000
o1t2
a
mode of 8085. (2015), (2017)
‘Aus. (1) 8085 microprocessor is an 8 bit microprocessor. i. it can accept or provide
Sbit data simultaneously,
(2) 8085 microprocessor is a single chip, NMOS device implemented with 6206
transistors.
1 10900001 10100000000000000000000
16 00000001 00000000000000000000000 = +1
2°%(1-127) #10
1 0000000 10000000000000000000000 = +1
2°%(-126) * 0.1 = 2
10 60000000 00000000000000000000001 = +1 * 2°*(-126) * (3) 8085 microprocessor requires a single +5V DC power supply.
1600000000000000000000001 = (4) 8085 microprocessor provides on chip clock generator, therefore there is no need
2°*(-149) (Smallest positive value) cfexternal clock generator, but it requires external tuned circuit like LC, RC or crystal
(5) 8085 microprocessor requires two phase, 60% duty cyele, TTL clock. These clock
Double Pre ‘The IEEE double precision floating point standard
signals are generated by an internal clock generator.
representation requires a G4 bit word, which maj (6) The maximum clock frequency of 8085 microprocessor is 3MHz where as
yy be represented as numbered from 0
to 63, eft to right
| minimum clock frequency is 600 KHz
+ The first bit is the sign bit, S, 1. Immediate Addressing Mode: - An immediate is transferred directly to the
* the next eleven bits are the exponent bits, ‘F", and register
+ the final 52 bits are the fraction ‘F’ Eg: MVIA, 30H (30H is copied into the register A)
S REBEBEREEEE MVI B,40H(40H is copied into the register B)
FPF F RFF ERY EFF FEF FPF PFF PPFF PYF PEEP PF FPP PEPE EP PEEP
2, Register Addressing Mode: - Data is copied from one register to another
o1 mie register
a: = MOV B, A (the content of Ais coped into the register 1)
V represented by the word may be determined as follows MOV A. C (the content of © is copied into the register A
2041 und ¥ i nonzero, then VeNaN (Not a number”) 3. Direct Addressing Mode: - Data is directly copied from the given address to
2047 and ¥ in zer0 and 8 Ws 1, then V=-Infinity pe reslatae
Eg: - LDA 3000H (The content at the location 3000H is copied to the register A).
2HA1 nod ¥ in vero and 8 in 0, then Volnfin et creas plated
aE ent whine LF cies, Linden Arcee ea is Caine
ae ~ inary number created by prefixing F with an implicit leading 1 and & Weg - MOV A. M (data is transferred from ro vory location pointed by the
: rosie to eect
sant ta and ¥ is nonar, dan Vot= Wee #2 #6 (= ED * CP) ‘There are ‘Sitaplied Addressing Mode: - This mode docen't require any operand. The data
tennarmalina extoes seeciaod by opeda iad
9 If BeoO and F in zero and 8 i6 1, then V =~ 0 "ne AL :
© 11400 and F in aero and in then V 20
cmP A
Q23, An # bit register contains binary value 10011100, What is resisi#f | @.26, Derive the control gates associated with the programm counter
value after arithmetic shift right? Starting from initial no. 10011100 determing in Ube an
Jc computer.
‘ister value afler an arithmetic shift left und state whether this is overBow ‘Ans. (Assume that ZDR = LifDR= 0; ZAC = 1, AC = 0)
(2015),(2017) INR (PC) » RT, + RT, + DT ZDK + PBYFGD + PBLFGO) + rBYAC,F 1
‘Ams. He» 10011100, + ABZAC + eB EY
Arithmetic shift right. 11001110 -D (PC) = D.T, + DT,
rithmatie a ged CLR WC)
sn Fnac stuf et O11 1000 vertow Yncause w negative number «hs | (HC) « ie
Bi.— eee” =—3seeesése
a a
74-2021 ‘Third Semester, Digital Logic and Computer Design
7. An output program resides memory starting from address 2300. It is
eat one the computer recognizes an interrupt when FGO becomes as
1 (while IEN=1).
(a) What instruction must be placed at address 1?
(b) What must be the last two instructions of the output program? (2015)
‘Ans. (a) 0 BUN (2300)10
() ION
1 BUN 0 (Branch indirect with address 0)
Q.28. Write a program loop, using a pointer and a counter, that clears to @
the contents of hexadecimal locations 500 through SFF.
‘Ans, LDA NBR ‘Anitialize counter with
CMA ‘2's compl. of NBR
INC
STA CTR /eave -NBR to counter
LDA ADR (Save start address to
STAPTR PTR
LOP,CLA Wlear AC
STAPTRI Meset memory word
ISZPTR ‘Ancrement pointer
ISZCTR increment counter
BUN LOP PBranch to LOP (CTR
