DIGITAL VLSI DESIGN

(18EC54)
(Theory and Practice)
CIE Marks: 100+50
Theory & Practice
Credits: 04 SEE Marks: 100+50
Why ICs ?
• Integration improves the design
– Higher speed

– Lower power consumption

– Smaller size

• Integration reduces manufacturing cost -

(almost) no manual assembly
IC Applications
• VLSI is an implementation technology for electronic circuitry -
digital or analogue

• Microprocessors

– personal computers

– microcontrollers

• Memory - DRAM / SRAM

• Special Purpose Processors - ASICS (CD players, DSP

applications)
Till 1950 s the electronic active device technology
was dominated by Vacuum tubes
Now the present day electronics is the result of the
invention of transistor in 1947
The first IC emerged at the beginning of 1960
 Semiconductor devices are available in one of the
two forms:
1. Discrete units Ex: Diode(BY127) , Transistor(SL100), etc

2. Integrated Circuits (ICs) Ex: 7400, 7408, 8086 etc.

The First Transistor The First Integrated Circuit

Source: Richard Spencer

Fabricated at Bell Labs on This is the first IC made by Jack

December 16, 1947. The inventors Kilby of Texas Instruments. It
won the Nobel prize in physics in
was built in 1958.
1956 for the invention.
Classification of ICs
Based on the device count ICs are classified
into:
SSI - Small Scale Integration
MSI - Medium Scale Integration
LSI - Large Scale Integration
VLSI- Very Large Scale Integration
ULSI- Ultra Large Scale Integration
GSI - Giant Scale Integration
Levels of Transistors/chip Gates/chip Applications
integration
SSI 1-100 <12 Logic gates, Op-amps
MSI 100-1000 12-99 Registers , Filters
LSI 1000-20k 1000 8 bit processor, A/D converter

VLSI 20k-1000k 10k 16 bit, 32 bit processor,

256KB memory
ULSI 1000k-10000k 100k 64 bit processor, 8 MB memory
Image processor
GSI >10000k 1M 64 MB memory, multiprocessor,
etc.
UNIT – I
VLSI Design Flow: Specification, Design entry, Functional simulation, planning
placement and routing, timing simulation.
MOS Transistor: Introduction, Ideal I-V characteristics, C-V Characteristics,
Simple MOS Capacitance Models, Detailed MOS Gate Capacitance Model, Non-
ideal I-V Effects, Mobility Degradation and Velocity Saturation, Channel Length
Modulation, Threshold Voltage Effects, Junction Leakage, Body effect, Tunneling.
DC Transfer Characteristics: Static CMOS Inverter DC Characteristics, Beta
Ratio Effect, Noise Margin.
Combinational Circuit Design: CMOS Logic, Inverter, NAND Gate, NOR Gate,
Combinational Logic, Compound Gates, Pass Transistors and Transmission Gates,
Tristates, Multiplexers.
Unit – II
Delay: Transient response, RC delay model, linear delay model
Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch
Logic, Dynamic Circuits, Complementary Pass-Transistor Logic Circuits.:
Datapath Subsystem: Single-Bit Addition, Ripple Carry Adder, Manchester
Carry chain adder, Carry Skip adder, Carry Select Adder, Braun, Baugh-wooley
and Array multipliers.
UNIT – III
Sequential MOS Logic Circuitry: Behavioral of Bistable element, SR Latch
Circuitry, Clocked latch and Flip Flop Circuitry, C-MOS D-Latch and Edge
Triggered Flip-Flop.
Sequencing Static Circuits: Sequencing Methods, Max-Delay Constraints,
Min-Delay Constraints Time Borrowing, Clock Skew
UNIT – IV
Array Sub system SRAM: Memory cell Read/Write operation, Decoder, Bit-line
conditioning and column circuitry and Column Circuitry, Multi-Ported SRAM.
DRAM Subarray Architectures, Column Circuitry
Read-Only Memory Programmable ROMs, NAND ROMs.
Content-Addressable Memory, PLA
UNIT – V
CMOS Processing Technology: CMOS Technologies, Wafer Formation,
Photolithography, Well and Channel Formation, Silicon Dioxide (SiO2), Isolation,
Gate Oxide, Gate and Source/Drain Formations, Contacts and Metallization,
Passivation, Metrology.
Layout Design Rules-stick diagrams and Gate layouts,
Transistor Scaling
Introduction to finFET: Brief History, Construction, Advantages and
Disadvantages, Applications.
Scheme of Continuous Internal Evaluation (CIE) for Theory
CIE will consist of THREE Tests, THREE Quizzes and Experiential Learning (EL). each test
will be conducted for 50 marks and the quiz for 10 marks each. The Experiential Learning
(EL). will be for 20 marks. The total marks for CIE (Theory) will be 100 marks.
Total CIE is 50 (T) +30 (Q) +20 (EL) = 100 Marks.

Reference Books

1. CMOS VLSI Design, Neil H.E. Weste, David Harris, Ayan Banerjee, 3rd Edition, 2006,
Pearson Education, ISBN: 0321149017.
2. CMOS Digital Integrated Circuits, Sung MO Kang, Yousf Leblebici, 3rd Edition, Tata Mc
GrawHill, ISBN: 0-7923-7246-8.
3. Basic VLSI Design, Douglas.A.Pucknell, Kamaran Eshraghian, 3rd Edition 2010 ,PHI,
ISBN: 0321-26977-2.
4. Fundamentals of Ultra-Thin-Body MOSFETs and FinFETs, Jerry G. Fossum , Vishal P.
Trivedi , 1St Edition 2013, Cambridge University Press, ISBN-13: 978-1107030411.
5. Jan M.Rabaey, Anantha Chadrakasan, Borivoje Nikolic, “Digital Integrated Circuits: A
Design Perspective”, (2/e), Pearson 2016.
Practical’s:
1.a Realization of CMOS Logic-universal gates.
.b Practice question: Realize CMOS XOR/XNOR gates
2.a Realization of CMOS - adder circuits
.b Practice question: Realize 4-bit adder/subtractor
3.a MOS device Characterization
.b Practice question: Plot gm vs Vgs for NMOS/PMOS
4.a CMOS Inverter Static Characteristics
.b Practice question: Plot the Voltage Transfer Characteristic graph of CMOS inverter and
calculate the switching voltage for the given specification
5.a Sequential Circuit Design using Master-Slave configuration
.b Practice question: Realize 4-bit Ring counter/Johnson counter
6.a CMOS Inverter layout and post simulation
.b Practice question: NOR/NAND gates layout and post simulation
7.a Inverter design using FinFET
.b Practice question: NOR/NAND gates using FinFET
8.a Analysis of Common source and differential amplifiers
.b Practice question: Realize of Op-amp using CS and differential amplifiers
9.a Synthesis of Serial Adder
.b Practice question: Perform PnR for Serial Adder.

Case study: ASIC design flow using Innovas. (Students should learn the concept and
produce the relevant document)
ADDC course is Prerequisites for this DVD course

Few VLSI Companies in India

1. Intel 19. Microchip
2. Qualcomm 20. Ansys
3. Analog Devices 21. Synaptics
4. Texas Instruments 22. Samsunng Electronics
5. Western Digital 23. Mentor Graphics
6. NXP 24. Cadence Design Systems
7. Cypress Semiconductor 25. Maxim Integrated
8. Mediatek 26. Rambus
9. Global Foundry 27. Micron
10. Synopsys 28. Renesas Electronics
11. Nvidia 29. Google
12. Juniper Networks 30. Marvell Semiconductor
13. Cisco 31. AMD
14. IBM 32. National Instruments
15. ROHM Semiconductor 33. MaxLiner
16. Xilinix 34. ON Semiconductor
17. Infineon 35. Analog Devices
18. ST Microelectronics 36. ARM
Issues in Digital Integrated Circuit Design
Integration density and performance of integrated circuits have
increased greater extent in the last couple of decades.
Gordon Moore: Co-founder of Intel, Predicted that the number
of transistors per chip would grow exponentially (double every
18 months)
This can be illustrated with a set of graphs.

Figure below plots the integration density of both logic IC’s

and memory as a function of time. As can be observed,
integration complexity doubles approximately every 1 to 2
years. As a result, memory density has increased by more than
a thousand fold since 1970.
Fig a: Trends in logic IC complexity
Fig b: Trends in memory complexity
The million-transistor/chip barrier was crossed in the late
eighties. Clock frequencies double every three years and have
reached into the GHz range.
Power Dissipation

Microprocessors power
continues to increase
The power optimization can be done at different levels of
design hierarchy, which includes:

 Technology, Devices,
Circuits, Logic,
Architecture (Structure),
Algorithm (Behavior) and
 System Levels,
The steps involved in the design of VLSI chip are shown in the
above flowchart.
MOS Transistor

The Metal-Oxide-Semiconductor Field-Effect Transistor

(MOSFET) is mainly used in digital design.
It performs very well as a switch
Introduces little parasitic effects.
Its high integration density
Simple manufacturing process, which make it possible to
produce large and complex circuits in an economical way.
MOS Transistor:
MOS Transistor Types
Two transistor types
–NMOS: p-type substrate, n+source/drain, electrons are charge carriers
–PMOS: n-type substrate, p+source/drain, holes are charge carriers
MOS Transistor Symbols

The MOSFET is a four terminal

device. The voltage applied to the
gate terminal determines
how much current flows between the
source and the drain ports.
The body represents the fourth
terminal of the transistor. Its
function is to modulate the device
characteristics and parameters.

•All symbols appear in literature

–Symbols with arrows are conventional in analog papers
–PMOS with a bubble on the gate is conventional in digital circuits papers
•Sometimes bulk terminal is ignored –implicitly connected to supply:
•Unlike physical bipolar devices, source and drain are usually symmetric
MOS Transistor Structure

Important transistor physical

characteristics
–Channel length L = LD–2xd
–Channel width W
–Thickness of oxide tox
MOS structure demonstrating
(a) accumulation, (b) depletion, and (c) inversion
Ideal I-V Characteristics

MOS transistors have three regions of operation:

* Cutoff or subthreshold region
* Linear or nonsaturation region
* Saturation region

Fig: Average gate to channel voltage

MOS Transistor Regions of Operation
Three main regions of operation
•Cutoff: VGS< VT
No inversion layer formed, drain and source are
isolated by depleted channel. IDS ≈0
•Linear (Triode, Ohmic): VGS> VT, VDS< VGS-VT
Inversion layer connects drain and source.
Current is almost linear with VDS(like a resistor)
•Saturation: VGS > VT, VDS ≥VGS-VT
Channel is “pinched-off”. Current saturates
(becomes independent of VDS, to first order).
Linear Region
•When VGS>VT, an inversion layer forms between drain and source
•Current IDS flows from drain to source (electrons travel from source to drain)
•Depth of channel depends on V between gate and channel
–Drain end narrower due to larger drain voltage
–Drain end depth reduces as VDS is increased
Linear Region I/V Equation

W    W
 n  K ‘  ins 0 n
L D L
Saturation Region
•When VDS= VGS-VT:–No longer voltage drop of VT from gate
to substrate at drain
–Channel is “pinched off”
•If VDS is further increased, no increase in current IDS
–As VDS increased, pinch-off point moves closer to source
–Channel between that point and drain is depleted
–High electric field in depleted region accelerates electrons
towards drain
Saturation I/V Equation

• As drain voltage increases, channel remains pinched off

–Channel voltage remains constant
–Current saturates (no increase with increasing VDS)
• To get saturation current, use linear equation with VDS= VGS-VT

( V gs  V t ) 2
I ds   n [(V gs  V t )(V gs  V t )  2 ]

( V gs  V t ) 2
I ds ( Sat )   n [ 2 ]
Current-Voltage Relations
ID versus VDS ID versus VGS
-4
x 10 -4
6 x 10
VGS= 2.5 V 6

5
5
Resistive Saturation
4 4
VGS= 2.0 V

I D (A)
ID (A)

3 3
VDS = VGS - VT
2
2 VGS= 1.5 V

1
1
VGS= 1.0 V
0
0 0.5 1 1.5 2 2.5
0 VGS(V)
0 0.5 1 1.5 2 2.5
VDS (V)
PMOS Transistor

-4
x 10
0

-0.2

-0.4
ID (A)

-0.6

-0.8

-1
-2.5 -2 -1.5 -1 -0.5 0
VDS (V)
positive voltage negative voltage (rel.
(Vdd) to body) (GND)

NMOS/NFET PMOS/PFET
+++ ---

--- +++
current current

channel
body/bulk shorter length,
body/bulk
faster transistor
GROUND (dist. for HIGH
electrons)

(S/D to body is
reverse-biased)
N-FET and P-FET Devices as Switches
oxide • NFET Device:
gate – Positive voltage (“1” or high) on gate
N+ relative to source turns device ON and
allows positive current to flow from
N N+ gate drain to source (switch closed)
P substrate drain
source – zero volts on gate (“0” or low) turns
N channel device source drain device OFF (open circuit)
substrate
– Drain must be more positive w.r.t
N-FET device schematic Source
• PFET Device:
oxide
– Negative voltage (“0” or low) on gate
relative to source turns device ON and
gate
allows (negative) current to flow from
drain to source (closes switch)
P+ P+ – positive voltage (“1” or high) on gate
source
drain
turns device OFF (open circuit)
N well
gate – Source must be more positive w.r.t
P channel device Drain
source drain
substrate

P-FET device schematic

Relationship between Vgs and Ids, for a fixed Vds:

Graph of Vgs vs Ids

The Threshold Voltage(Vt)
+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

The Threshold Voltage(Vt) is the minimum gate to source

voltage required to construct the channel between drain
and source.
The Threshold Voltage(Vt)
may be expressed as
Q B  Q ss
V t   ms   2 fn
Co
Where QB is the charge per unit area in the depletion layer beneath
the oxide (Coulombs/m2)

QSS is the Charge density at Si:Sio2 interface (Coulombs/m2)

Co is the Capacitance per unit gate area

øms is the Work function difference between gate and Silicon

(Volts)
(For the polysilicon gate and Silicon substrate, the value of ø ms is
negative and negligible).

øfn (Φs)is the Potential between inverted surface and bulk silicon
(Volts)
To evaluate threshold Voltage(Vt) each term is determined as follows

QB  2  o  Si QN ( 2 fn  V SB ) Coulombs/m2

KT N
 fn  ln
Q ni

Qss  (1.5  8)1018 Coulombs/m2

Where
VSB is the substrate bias voltage (Volts)
Q  1 . 6 X 10  19 Coulomb
N is the Impurity concentration in substrate
ε Si relative permittivity of Silicon=11.7
ni is the intrinsic Electron concentration
n i  1 . 6 X 10  10 / Cm 3 at 300 0 k
K is the Boltzmann’s constant

K  1 . 4 X 10  23 Joules / 0 k
ε is the permittivity of free space,
o  o  8 . 854 X 10  14 F / cm

In general threshold (Vt) is a function of number of parameters

 Gate material
 Gate Insulation thickness
 Impurities at Si:Sio2 interface
 Voltage between the source and substrate(VSB)

Also the absolute value of Vt decreases with increasing temperature

C-V Characteristics
Each terminal of an MOS transistor has capacitance to the
other terminals. In general, these capacitances are nonlinear
and voltage dependent (C-V).

Simple MOS Capacitance Models

The gate of an MOS transistor is a good capacitor. Its capacitance

is necessary to attract charge to invert the channel, so high gate
capacitance is required to obtain high Ids.
• The capacitance is

Cgs = ᵋ
oxWL/tox = CoxLW = CpermicronW

• Most of the transistors used are of minimum Manufacturable

length, this results in greatest speed and lowest power
consumption. Thus taking this minimum L as a constant for a
particular process, Cgs = CpermicronW

• Cpermicron is typically about 2 fF/mm

In addition to the gate, the source and drain also have
capacitances.
These capacitances are not fundamental to operation of the
devices, but do impact circuit performance(Undesirable) and
hence are called parasitic capacitors.
They arise from the reverse-biased p-n junctions between the
source or drain diffusion and the body and hence are also called
diffusion capacitance Csb and Cdb.
Capacitance depends on area and perimeter.
Detailed MOS Gate Capacitance Model
The MOS gate sits above the channel and may partially overlap the source and
drain diffusion areas.
Therefore, the gate capacitance has two components:
Intrinsic capacitance (over the channel) and
Overlap capacitances (to the source, drain, and body).
The intrinsic capacitance was approximated as a simple parallel plate. This
capacitance is: CoxWLeff,

– Gate electrode overlaps source and drain regions

– xd is overlap length on each side of channel
–Leff= Ldrawn–2xd (effective channel length)
–Overlap capacitance:

Assume xd equal on both sides

The bottom plate of the capacitor depends on the mode of
operation of the transistor.

1. Cutoff: When the transistor is OFF (Vgs = 0), the channel is

not inverted and charge on the gate is matched with
opposite charge from the body. This is called Cgb, the gate-
to-body capacitance.
As Vgs increases but remains below a threshold(Vgs<Vt), a
depletion region forms at the surface. This effectively moves
the bottom plate downward from the oxide, reducing the
capacitance.
Total Gate Capacitance CG =C0= CoxWLeff+2CoxWXd = CoxWL
2. Linear: When Vgs > Vt, the channel inverts and again serves as
a good conductive bottom plate.
The channel is connected to the source and drain, rather than the
body.
At low values of Vds, the channel charge is roughly shared
between source and drain, so Cgs = Cgd = C0/2.
As Vds increases, the region near the drain becomes less inverted,
so a greater fraction of the capacitance is attributed to the source
and a smaller fraction to the drain.
3. Saturation: At Vds > Vgs – Vt, the transistor saturates and the
channel pinches off.
At this point, all the intrinsic capacitance is towards the source.
Because of pinchoff, the capacitance in saturation reduces to
Cgs = 2/3 C0 for an ideal transistor.
The behavior in these three regions are shown in below table:
The gate overlaps the source and drain by a small amount in a
real device. This leads to additional overlap capacitances, as
shown in Figure. These capacitances are proportional to the
width of the transistor. Typical values are Cgsol = Cgdol =
0.2-0.4 fF/µm.

Fig: Overlap capacitance

The effective gate capacitance varies with the switching activity
of the source and drain. Figure shows the effective gate
capacitance in a 0.35 µm process for seven different combinations
of source and drain behavior .

Fig: Data-dependent
Gate capacitance
Figure : CV characteristics of MOSFET

The total gate-channel capacitance and its distribution over the three
components is best understood with the help of a number of charts. The
first plot (Figure a) captures the evolution of the capacitance as a function
of Vgs for Vds=0, the transistor is off, no channel is present and the total
capacitance, equal to CoxWL, appears between gate and body. When
increasing Vgs, a depletion region forms under the gate.
This causes the thickness of the gate dielectric to increase, which means a
reduction in capacitance. Once the transistor turns on (Vgs=Vt), a channel is
formed and drops to 0. With Vds=0, the device operates in the resistive mode
and the capacitance divides equally between source and drain, or
Cgs=Cgd=CoxWL/2. Once the transistor is on, the distribution of its gate
capacitance depends upon the degree of saturation, measured by the Vds/(Vgs-
Vt) ratio as shown in figure b.
Cgcd gradually drops to 0(due to increase in depletion region near the drain
end) for increasing levels of saturation, while Cgcs increases to 2/3 CoxWL. This
also means that the total gate capacitance is getting smaller with an increased
level of saturation.
From the above, it becomes clear that the gate-capacitance components are
nonlinear and varying with the operating voltages.
Detailed MOS Diffusion Capacitance Model (Junction Capacitance)
A final capacitive component is contributed by the reverse-biased
source-Sub and drain sub pn-junctions.
Junction capacitance occurs for source and Drain diffusions
Consider Source Junction capacitance
Figure shows that the junction consists of two components:

Bottom-plate junction, which is formed

by the source region and the substrate.
The total depletion region capacitance
for this
component equals Cbottom = C’jW LS,

Fig: Detailed view of source junction.

xj, the junction depth of source/Drain

For a P-N junction Cj can be calculated by:

If V=0, Cap/Area =

General form:

m = grading coefficient (0.5 for abrupt junctions) (0.3 for graded junctions)

Abrupt junction: where the transition from n to p material is instantaneous(Immediate

Graded junction: transition from n to p material can be gradual.

The side-wall junction, formed by the source region

Perimeter(P) = 2LS+ W

Area = P * Xj Note: xj, the junction depth of source/Drain

Its capacitance value equals Csw = Csw’(W + 2Ls) xj.

Notice that no side-wall capacitance is counted for the fourth side of the
source region, as this represents the conductive channel.

Cdiff = Cbottom + Csw = Cj’ AREA + Cjsw’ PERIMETER*depth

= C’j LS W + Cjsw’(2LS + W) xj

Where Cj ‘and Cjsw’ are junction capacitance/unit area of bottom plate and side
walls respectively

The drain diffusion has a similar parasitic capacitance dependent

Nonideal I-V Effects

Fig2: Ideal I-V characteristics

of nMOS transistor

Fig1: Simulated I-V characteristics

The ideal I-V model of drain to source current (Ids) neglects
many effects that are important to modern devices.
The above Figure1 shows the simulated I-V characteristics of a
unit nMOS transistor in a 180 nm process.

Compare the characteristics in the linear and saturation regions

(Figure 1(a)) to those of the ideal device in Figure2.
The saturation current less increases with increasing Vgs, This is
caused by two effects:
Velocity saturation and
Mobility degradation.
There are several sources of leakage resulting in current flow in
nominally OFF transistors.
Observe in Figure1(b) that at Vgs < Vt, the current drops off
exponentially rather than abruptly becoming zero. This is called
subthreshold conduction.
The threshold voltage itself is influenced by the voltage
difference between the source and body; this is called the body
effect. The source and drain diffusions are reverse-biased diodes
and also experience junction leakage into the substrate or well.
Channel Length Modulation
•In saturation, pinch-off point moves
–As VDS is increased, pinch-off point moves closer to source
–Effective channel length becomes shorter
–Current increases due to shorter channel
(The effective length of the conductive channel is actually modulated
by the applied VDS: increasing VDS causes the depletion region at
the drain junction to grow, reducing the length of the effective
channel. The current increases when the length factor L is decreased.)

λ= channel length modulation coefficient

I/V curve for non-ideal NMOS device
Velocity Saturation
The behavior of transistors with very short channel lengths deviates
considerably from long channel devices.
The lateral electric field EY along the channel increases, as the effective
V ds
channel length is decreased. E ds 
L Velocity(v) = µnEds
The velocity of the carriers is proportional
to the electrical field
When the electrical field along the channel reaches a critical value ξC,
the velocity of the carriers tends to saturate due to scattering effects
(collisions suffered by the carriers)
as shown in Figure.

Fig: Velocity-saturation effect

This effect has a impact on the operation of the transistor. The
velocity as a function of the electrical field

k is a measure of the degree of velocity saturation,

Given by (where V is Vds)
since VDS/L can be interpreted as the average field in the channel. In case
of long-channel devices (large values of L) or small values of VDS, k
approaches 1 and Eq. (x1) simplifies to the traditional current equation
for the resistive operation mode. For short-channel devices, k is smaller
than 1, which means that the delivered current is smaller than what would
be normally expected.

--------------x1
For a short-channel device and for large enough values of VGT, k(VGT) is
substantially smaller than 1, hence VDSAT < VGT.

The device enters saturation before VDS reaches VGS - VT.

Short-channel devices therefore experience an extended saturation region, and tend
to operate more often in saturation conditions than their long-channel counterparts,
as is illustrated in Figure
Note: VGT is a shorthand notation for VGS - VT.
The saturation current IDSAT displays a linear dependence with
respect to the gate source voltage VGS, which is in contrast with the
squared dependence in the long channel device.
-4
x 10 x 10
-4
6 2.5

5
2

4 linear
quadratic 1.5
ID (A)

ID (A)
3

1
2

0.5
1

0 0
0 0.5 1 1.5 2 2.5 0 0.5 1 1.5 2 2.5
VGS(V) VGS(V)

Long Channel Short Channel

Subthreshold Conduction
The ideal transistor I-V model assumes current only flows from
source to drain when Vgs > Vt.
In real transistors, current does not abruptly cut off below
threshold, but rather drops off exponentially as given in
equation

where IS and n are empirical parameters,

The value of n is determined by the intrinsic
device topology and structure.
Fig: ID current versus VGS exponential
characteristic at subthreshold region.
This conduction is also known as leakage and often results in
undesired current when a transistor is nominally OFF.
Body Effect (Substrate bias effect)
Up to here we have considered a transistor to be a three-
terminal device with gate, source, and drain.
However, the body is an implicit fourth terminal. The potential
difference between the source and body Vsb affects the threshold
voltage.
The threshold voltage can be modeled as

where VT0 is the threshold voltage when the source is at the body
potential(i.e source & substrate are shorted),
ϕF is the Potential between inverted surface and bulk silicon
(Volts) KT N
f  ln
Q ni
γ is the body effect coefficient, typically in the range 0.4 to 1

Thus, the variation of threshold voltage due to source to substrate

voltage is called body effect.
Threshold Voltage Summary
Example2

Solution: Given oxide thickness tox=40A

KT N
f  ln
Q ni
Junction Leakage
The p-n junctions between diffusion and the substrate or well
form diodes, as shown in Figure.

Fig: Reverse-biased diodes in CMOS circuits

The well-to-substrate junction is another diode. The substrate

and well are tied to GND or VDD to ensure these diodes remain
reverse-biased.
However, reverse- biased diodes still conduct a small amount of
current ID.

where Is depends on doping levels and on the area and

perimeter of the diffusion region and
Vd is the diode voltage (e.g., Vsb or Vdb).
When a junction is reverse biased by significantly more than
the thermal voltage, the leakage is just -Is, generally in the 0.1-
0.01 fA/ u,m2 range.
Tunneling
According to quantum mechanics, there is a probability that carriers will
tunnel through the gate oxide.
This results in gate leakage current flowing into the gate.
The probability of tunneling drops off exponentially with oxide thickness, and
so was negligible for thick gate oxide .

Over the last decades, the device dimensions have been scaled down
continuously, while the power supply and the operating voltages were kept
V
constant. E ds  ds Velocity(v) = µnEds
L
The resulting increase in the electrical field strength causes an increasing
velocity of the electrons, which can leave the silicon and tunnel into the gate
oxide upon reaching a high-enough energy level. Electrons trapped in the oxide
change the threshold voltage,
Figure shows plot of gate leakage current density JG against voltage for
various oxide thicknesses.

Fig: Gate leakage current

Large tunneling currents impacts on quiescent power consumption and

thus may limit oxide thicknesses tox to not less than about 8 Angstroms.
The tunneling phenomenon can lead to a long-term reliability problem,
where a circuit might degrade or fail after being in use.
Complementary CMOS Inverter DC Characteristics

PMOS transistor pull-up (CMOS)

CMOS Inverter
Vdd • The simplest complementary MOS (CMOS) circuit is
Inverter the inverter:
PFET
Schematic source – NFET & PFET gates are connected together as the input
– NFET & PFET drains are connected together as the
P-FET output
PFET drain – NFET & PFET sources are connected to Gnd and Vdd,
respectively.
Vout
Vin – NFET substrate is normally connected to Gnd for all
NFET drain NFET devices in the circuit
N-FET – PFET well is normally connected to Vdd (most positive
voltage in circuit) for all PFET devices
NFET source • Operation:
– If Vin is down (0 volts), NFET is OFF and PFET is ON
Gnd pulling Vout to Vdd (high = 1)
– If Vin is up (at Vdd), NFET is ON and PFET is OFF
pulling Vout low to Gnd (“0”)
– With Vin at 0 or Vdd, no dc current flows in inverter
Inverter Symbol
CMOS Inverter Transfer characteristics
Vdd
PMOS
CMOS inverter has PMOS enhancement
in out
pull-up device and NMOS
enhancement pull-down device NMOS
CMOS inverter has five distinct regions of
operations
Fig: Circuit
In region 1: 0<Vin<Vtn, P-transistor is ON
and n-transistor is OFF, no current
flows through the inverter.
the out voltage is high ( Logic 1)
In region 5: (Vdd-|Vtp|) <Vin<Vdd, n-
transistor is ON and p-transistor is
OFF, no current flows through the
inverter.
the out voltage is low ( Logic 0)
In region 2: Vtn<Vin<Vdd/2, n-transistor is conducting and is working in
saturation region, p-transistor is also conducting, but only small
voltage across drain and source, therefore it is working in linear region.

A small current flows through the inverter from Vdd to Vss

In region 4: Vdd/2<Vin< (Vdd-|Vtp|), Region 4 is similar to region 2 but the

roles of p and n devices are reversed. p-transistor is conducting and is
working in saturation region, n-transistor is also conducting, but only
small voltage across drain and source, therefore it is working in linear
region.

A small current flows through the inverter from Vdd to Vss

In region 3: Vin=Vdd/2, in which both transistors are in saturation, due to
this large current flows in region 3

since the transistors are in series, the currents in each device must be
the same

Idsp = - Idsn (due to electrons of NMOS and holes of PMOS)

Midpoint voltage (VM)
 n
I n  n Vin  Vtn 2 VDD  Vtp  Vtn
2 p
Vin 
Current through p-channel pull-up transistor n
1
p
p
Ip   Vin  VDD   Vtp 2
2
If n = p and Vtp = –Vtn
p
Ip     Vin  VDD  Vtp 2
2
V
At logic threshold, In = -Ip Vin  DD
2

n   pW p  W
Vin  Vtn 2  [( p  2  Vin  VDD  Vtp 2 )]  n n
2 2 Lp Ln
n p
Vin  Vtn    Vin  VDD  Vtp 
2 2
n
Vin  Vtn   Vin  VDD  Vtp Mobilities are unequal : µn = 2.5 µp
p
  n  n
Vin 1   Vtn  VDD  Vtp
   p
 p 
Problem 3) VDD = 5 V
VTP = -0.7 V
 
VTn = 0.6 V  p  1.8A / V 2
 VDD  / VTP /  VTn x  n   2.1 

VM  
 p   5  0.7  0.6 1.8 

 n  2.1A / V 2
n 2.1   2.378V
 1   1 
    1 . 8 
 p 

Beta Ratio Effects

 Kn/Kp ratio decreses

 Kn/Kp ratio Increases

Fig: inverter switching threshold versus
PMOS/NMOS ratio

Fig: Changing the inverter threshold can

improve the circuit reliability.
Inverters with different beta ratios βn/βp are called skewed
inverters.
If βn/βp<1 inverter is Hi-skewed.
If βn/βp>1 the inverter is LO-skewed.
If βn/βp = 1, the inverter has normal skew or is unskewed.

Problem 4) Given Data:

VDD = 3.3 V
VTP = -0.8 V
VTn = 0.65 V
p = 2.2n

  n   n 
 V DD  / V TP /  V Tn  3 . 3  0 . 8  0 . 65 
 p   2 .2  n 
VM   
    1 . 755 V
 n   n 
1 1 
 p   2 .2  n 
   
Graphical Representation
The nature and the form of the voltage-transfer characteristic (VTC)
can be graphically deduced by superimposing the current
characteristics of the NMOS and the PMOS devices. Such a graphical
construction is traditionally called a load-line plot. It requires that the I-V
curves of the NMOS and PMOS devices are transformed onto a common
coordinate set.
The PMOS I-V relations can be translated into this variable space by
the following relations.

IDSp = –IDSn
VGSn = Vin ; VGSp = Vin – VDD
VDSn = Vout ; VDSp = Vout – VDD
The subsequent steps to adjust the original PMOS I-V curves to the
common coordinate set Vin, Vout and IDn are illustrated.

Fig: Transforming PMOS I-V characteristic to a common coordinate set

Fig: Load curves for NMOS and PMOS transistors of the static CMOS inverter

The resulting load lines are plotted in Figure. For a dc operating points
to be valid, the currents through the NMOS and PMOS devices must
be equal. Graphically, this means that the dc points must be located at
the intersection of corresponding load lines.
A number of those points (for Vin = 0, 0.5, 1, 1.5, 2, and 2.5 V) are marked on
the graph. As can be observed, all operating points are located either at the
high or low output levels. These operating points are plotted on Vout v/s. Vin
axes to show the inverter DC transfer characteristics.
This results from the high gain during the switching transient, when both
NMOS and PMOS are simultaneously on, and in saturation. In that operation
region, a small change in the input voltage results in a large output variation
as shown in figure.

Fig: VTC of static CMOS inverter,

Noise Margin (noise immunity)
Noise margin is the amount of noise that the circuit can withstand without
compromising the operation of circuit.
Noise margin is closely related to the DC voltage characteristics. This allows
to determine the allowable noise voltage on the input of a gate so that the
output will not be corrupted.
The specification most commonly used to describe noise margin (or noise
immunity) uses two parameters:
 LOW noise margin, (NML)
 HIGH noise margin, (NMH).
With reference to below Figure, NML is defined as the difference in
maximum LOW input voltage recognized by the receiving gate and the
maximum LOW output voltage produced by the driving gate.
The value of NMH is the difference between the minimum HIGH output
voltage of the driving gate and the minimum HIGH input voltage
recognized by the receiving gate.

Fig: Noise margin definitions:

For the purpose of calculating noise margins, the transfer
characteristic of the inverter and the definition of voltage levels
VIL, VOL, VIH, VOH are shown in Figure. Logic levels are
defined at the unity gain point where the slope is -1.

In CMOS inverter
VOL=0V
VOH=VDD

VIL & VIH are found by

determining unity gain point in the
inverter transfer characteristics.
In CMOS inverter
Fig: CMOS inverter noise margins VIL=2.3V
VIH=3.3V
NML=VIL-VOL=2.3-0=2.3V
NMH=VOH-VIH=5-3.3=1.7V
CMOS Logic
The Inverter :

Fig: Inverter schematic and symbol

The NAND Gate

Fig: 3-inputNAND gate schematic

Fig: 2-input NAND gate and symbol

Fig: Connection and behavior of series and parallel transistors
The NOR Gate

Fig: 2-input NOR gate schematic and symbol

Fig: 3-input NOR gate schematic

Combinational Logic

Fig: General logic gate using pull-up and pull-down networks

Fig: CMOS compound gate for

function Y= (A+ B + C) •D
Pass Transistor DC Characteristics

Pass transistor passes signal between drain

and source under the control of gate.
nMOS transistors pass '0's well but 1’s poorly.

The source is initially at Vs = 0. Vgs > Vtn, so

the transistor is ON and current flows. If the
voltage on the source rises to Vs = VDD - Vtn,
Vgs falls to Vtn and the transistor cuts itself
OFF.
Therefore, nMOS transistors attempting to
pass a '1' never pull the source above VDD -
Vtn.

Fig: Pass transistor threshold drops

Pass Transistors and Transmission Gates

Fig:Pass transistor strong and degraded outputs

Similarly, pMOS transistors pass 1’s well but ‘0's poorly. If the
pMOS source drops below |Vtp|, the transistor cuts off. Hence,
pMOS transistors only pull down to within a threshold above
GND, as shown in Figure(b)

As the source can rise to within a threshold voltage of the gate,

the output of several transistors in series is no more degraded
than that of a single transistor (Figure (c)).
However, if a degraded output drives the gate of another
transistor, the second transistor can produce an even further
degraded output as shown in fig(d).
Noninverting buffer not recommended

Fig: Bad noninverting buffer

Here both the nMOS and pMOS transistors produce

degraded outputs, so the technique should be avoided.
Transmission Gate
Transmission gate consists of an nMOS transistor and a pMOS
transistor in parallel with gates controlled by complementary
signals.

When the transmission gate is ON, at least one of the two

transistors is ON for any output voltage and hence the
transmission gate passes both ‘0's and 'l's well.
It finds use as a multiplexing element, a logic structure, a latch
element, and an analog switch. The transmission gate acts as a
voltage-controlled resistor connecting the input and the output.
By combining an nMOS and a pMOS transistor in parallel this is
called transmission gate or pass gate.

Fig: Transmission gate

Thus the nMOS transistors only need to pass O's and the pMOS
only pass l's, so the output is always strongly driven and the levels
are never degraded. This is called a fully restored logic gate.
Figure shows the plot of transmission gate ON resistance as the input voltage is
swept from GND to VDD.
In region A, the nMOS transistor is operating linearly and the pMOS is cut
off.
In region B, both transistors are linear.
In region C, the nMOS transistor is cut off and the pMOS is linear.
If both transistors are of equal size, the characteristics are slightly asymmetric
because of the better mobility of the nMOS transistor.
The effective ON resistance is the parallel combination of the two resistances
and is relatively constant across the full range of input voltages.

Fig: Resistance of a transmission

gate as a function of input voltage
Tristates

Fig:Tristate buffer symbol

Fig: Transmission gate

When the enable input EN is '1,' the output Y equals the inputs, just as in an
ordinary buffer. When the enable is '0,' Y is left floating (a 'Z' value).
Sometimes both true and complementary enable signals EN and EN are
drawn explicitly, while sometimes only EN is shown.
Tristate Inverter
By cascading a transmission gate with an inverter, the tristate inverter shown
in Figure (a) is constructed. When EN = 0 and ENb = 1, the output of the
inverter is in a tristate condition.
When EN= 1 and ENb = 0, the Y output is equal to the complement of A.
The connection between the n- and p-driver transistors can be omitted and the
operation remains substantially the same.

For the same size n- and p-devices, this tristate inverter is approximately half
the speed of a complementary CMOS inverter.
The tristate inverter forms the basis for various types of clocked logic, latches,
bus drivers, multiplexers, and I/O structures.
Multiplexers
Multiplexers are key components in CMOS memory elements and
data manipulation structures.
A multiplexer chooses the output to be one of several inputs based
on a select signal. A two-input, or 2:1 multiplexer, chooses input
D0 when the select is '0' and input D1 when the select is 1.
The logic function is Y= S • D0+S • D1.

Fig: Transmission gate multiplexer

Two transmission gates can be tied together to form a compact 2-
input multiplexer, The select and its complement enable exactly
one of the two transmission gates at any given time.

We can realize inverting multiplexer out of gates in several

ways. One is the compound gate as shown in fig below.
The tristate approach is slightly more compact and faster because
it requires less internal wire. Again, if the complementary select is
generated within the cell, it is omitted from the symbol.
Fig: Inverting multiplexer

Larger multiplexers can be built from multiple 2-input multiplexers or by

directly ganging together several tristates. The latter approach requires
decoded select signals for each tristate. 4-input (4:1) multiplexers using each of
these approaches are shown in figure.
Fig: 4:1 multiplexer(Tri-state inverter based)

Fig: 4:1multiplexer(TG based)

Circuit Families

Static CMOS circuits with complementary nMOS pull-down and

pMOS pull-up networks are used for the vast majority of logic
gates in integrated circuits.

They have good noise margins, and are fast, low power,
insensitive to device variations, easy to design, widely supported
by CAD tools, and readily available in standard cell libraries.
Static CMOS
Designers accustomed to AND and OR functions must learn to
think in terms of NAND and NOR to take advantage of static
CMOS.
In manual circuit design, this is often done through bubble
pushing. Compound gates are particularly useful to perform
complex functions with relatively low logical efforts.

Bubble Pushing

CMOS stages are inherently inverting, so AND and OR

functions must be built from NAND and NOR gates.
DeMorgan's Law helps with this conversion:
Fig: Bubble pushing with DeMorgan's law

These relations are illustrated graphically in Figure.

A NAND gate is equivalent to an OR of inverted inputs. A NOR
gate is equivalent to an AND of inverted inputs.
The same relationship applies to gates with more inputs.
Switching between these representations is easy to do on a
whiteboard and is often called bubble pushing.
Compound Gates This function is sometimes called
AND-OR- INVERT-22, or AOI22
because it performs the NOR of a
pair of 2-input ANDs.

Fig: inefficient discrete gate

implementation of AOI22
indicating transistor counts

compound gate can built with two AND

gates, an OR gate, and an inverter. The
AND and OR gates in turn could be
Fig: CMOS compound gate for constructed from NAND/NOR gates and
function Y = (A • B) + (C • D) inverters, a total of 20 transistors are
required, as compared to 8 .
Compound Gates
Static CMOS also efficiently handles compound gates computing
various inverting combinations of AND/OR functions in a single
stage. The function F = AB + CD can be computed with an AND-
OR-INVERT-22 (AOI22) gate and an inverter, as shown in Figure

Fig: Logic using AOI22 gate

Design a circuit to compute F = AB+ CD using NANDs and NORs.

By inspection, the circuit consists of two ANDs and an OR,

shown in Figure 6.3(a). In Figure 6.3(b), the ANDs and ORs are
converted to basic CMOS stages. In Figure 6.3(c and d), bubble
pushing is used to simplify the logic to three NANDs.

Fig: Bubble pushing to convert ANDs and ORs to NANDs and NORs
Threshold Variations

Up to here WKT the threshold voltage is only a function of the

manufacturing technology and the applied body bias VSB. i.e.

The threshold can therefore be considered as a constant over all

NMOS (PMOS) transistors in a design.
As the device dimensions are reduced, this model becomes
inaccurate, and the threshold potential becomes a function of L,
W, and VDS.
In the traditional derivation of the VTO, it is assumed that the channel
depletion region is due to the applied gate voltage. This ignores the
depletion regions of the source and reverse-biased drain junction,
which become relatively more important with shrinking channel
lengths.

Since a part of the region below the gate is already depleted (by the source
and drain fields), a smaller threshold voltage is sufficient to cause strong
inversion.
In other words, VT0 decreases with L for short-channel devices (Figure a).
A similar effect can be obtained by raising the drain-source (bulk) voltage, as
this increases the width of the drain-junction depletion region. Consequently,
the threshold decreases with increasing VDS. This effect, called the drain-
induced barrier lowering (DIBL), causes the threshold potential to be a function
of the operating voltages (Figure b).

(a) Threshold as a function of the length (b) Drain-induced barrier lowering (for low L)
Fig: Threshold variations.

For high values of the drain voltage, the source and drain regions can even be shorted
together, and normal transistor operation ceases to exist. The sharp increase in current
that results from this effect is called punch-through, may cause permanent damage to the
device and should be avoided.
Prob1: Find the mode of operation (cutoff, linear, or saturation)
and drain current ID for each of the applied biases given below
with VSB= 0V. Assume for the NMOS that VT0 = 0.7V, W/L = 4/1,
γ= 0.35V, λ= 0.05 V-1, µCox = 350 µA /V2, and -2ΦF = 0.6 V.
1. NMOS: VGS = 1.8V, VDS = 1.8V
2. NMOS: VGS = 0.9V, VDS = 1.8V
3. NMOS: VGS = 1.5V, VDS = 0.4V
Solution:1) VGS=1.8V, VDS=1.8V , VSB=0,  VT=VT0 + 0=0.7+0=0.7V
VGS-VT=1.1V,  VDS> VGS-VT
Therefore the Transistor is working in Saturation

I ds ( Sat )  923 . 23 uA

2) VGS=0.9V, VDS=1.8V Saturation

I ds ( Sat )  30.5uA

3) VGS=1.5V, VDS=0.4V Triode/Linear

I ds  336 uA
Prob2. Find the mode of operation (cutoff, linear, or saturation) and drain
current ID for each of the applied biases given below with VSB= 0V. Assume for
the NMOS that VT0 = 0.7V, W/L = 4/1, γ= 0.35V, λ= 0.05 V-1, µCox = 350
µA/V2, and -2ΦF = 0.6 V.
1. NMOS: VGS = 1.5V, VDS = 1.5V
2. NMOS: VGS = 0.9V, VDS = 1.8V
Soln:
VGS-VT=0.8V,  VDS> VGS-VT
Therefore the Transistor is working in Saturation

I ds ( Sat )  481 .6uA

3) VGS=0.9V, VDS=1.8V  the Transistor is working in Saturation

I ds ( Sat )  30 . 52 uA