BACS1024

INTRODUCTION TO
COMPUTER SYSTEMS

Chapter 5: I/o facilities

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Chapter Outline
5.1 Characteristic of I/O Devices
5.2 I/O Modules
5.3 I/O Handling Techniques
5.3.1 Programmed I/O (PIO)
5.3.2 Interrupt I/O
5.3.3 Direct Memory Access (DMA)
5.4 I/O Architecture
5.4.1 Bus Architecture
5.4.2 Channel Architecture

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5.1 Characteristic of I/O Devices

5.1.1 I/O devices

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5.1 Characteristic of I/O Devices

5.1.1 I/O devices

5.1.1.1 Keyboard
 It is a character-based device where a character is captured at each
time.
 Keyboard has slow transfer rate because it is dependent on the speed
of typing and the thought process of a user.
 Therefore, the computer spends most of its time waiting for input from
the keyboard.
 Keyboard input:
 Requesting input: An input that is expected by the program in
response to a READ statement. E.g.: Login screen, Word Document.
 Interrupt: An input that interrupt the computer's current operation.
E.g.: CTRL+C, CTRL+ALT+DEL

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5.1 Characteristic of I/O Devices

5.1.1 I/O devices

5.1.1.2 Printer
 Printer operate over a wide range of data rates.
 PC inkjet printer: 100 characters per second.
 Laser printer: 1200 characters per second.
 Mainframe line printer: Few thousand characters per
second.
 Output to a printer consisting only of an occasional page or
text will certainly not require a high data rate.

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5.1 Characteristic of I/O Devices
5.1.1 I/O devices
5.1.1.3 Graphic Output
 Object images
 Described by geometrical information.
 E.g.: Text instructions, lines and curves.
 The amount of data involved is small.

 Bitmap images
 Data for each pixel is to be produced.
 E.g.: photograph picture.
 The amount of data involved is huge.
 High speed data transfer is essential.

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5.1 Characteristic of I/O Devices
5.1.1 I/O devices
5.1.1.4 Disk
 Disk is used to store programs and
data
 Disk data is always transferred in
blocks, never as individual bytes
or words.
 Data may operate at transfer
rates of more than a million
bytes per second.
 Capable of both input and
output.

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5.1 Characteristic of I/O Devices

5.1.2 Requirement for Efficient I/O handling

1. Individually addressing different peripheral devices
2. Peripheral devices can initiate communication with the CPU
3. Suitable I/O processing technique for different devices
4. Handling devices with extremely different control requirements

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5.1 Characteristic of I/O Devices
5.1 I/O devices
5.1.3 Sample I/O Configurations
(1) Simple I/O Configuration

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5.1 Characteristic of I/O Devices
5.1 I/O devices
5.1.3 Sample I/O Configurations
(2) Complex I/O Configuration

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5.2 I/O Modules
5.2 I/O Modules
 Serves as an interface between the CPU and specific device, accepting
commands from CPU and controlling device.

 Functions
 Recognizes message addressed to it and accepts commands from
the CPU.
 Provides a buffer where the data from memory can be held until it
can be transferred to the disk.
 Provides the necessary registers and controls to perform a direct
memory transfer.
 Interrupt capability, to notify CPU when the operation is
completed.

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5.2 I/O Modules
5.2 I/O Modules
 CPU interface: Performs CPU interfacing tasks.
 Accept I/O commands from the CPU.
 Sending interrupts and status information to CPU.
 Device interface: supplier control of the device.
 Moving the head to the correct track in a disk drive and rewinding
tape.

CPU interface Device Interface

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5.2 I/O Modules
5.2 I/O Modules
 Simple CPU I/O instruction can be used to control complex operations
 Simplify the task f interfacing peripheral devices to a CPU. This off
load a considerable amount of work from the CPU
 Make it possible to control I/O to a peripheral with a few simple I/O
commands
 Support Direct Memory Access (DMA)  CPU is free to perform other
tasks
 Provides the specialized circuitry to interface different types of
peripherals.

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5.3 I/O Handling Techniques
5.3 I/O Handling Techniques
 Data transfer between the CPU and I/O devices can be handled in three
types of models:
1. Programmed I/O  CPU controlled I/O.
2. Interrupt-driven I/O  External input control.
3. Direct Memory Access (DMA)  Data transfer by bypassing CPU.

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5.3 I/O Handling Techniques
5.3 I/O Handling Techniques
5.3.1 Programmed I/O (PIO)
 The simplest method performing I/O.
 An I/O module is connected to a pair of I/O registers in the CPU via a
bus.
 Each instruction produces a single input / output.
 Address information must be sent with the I/O devices individually.
 Full instruction cycle for each I/O data word (very slow).
 Primary use: Keyboard

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5.3 I/O Handling Techniques
5.3 I/O Handling Techniques
5.3.1 Programmed I/O (PIO)

Input data from peripheral Output data to peripheral

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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.1 Interrupt
 Signal that causes the CPU to alter its normal flow on instruction execution.
 Free CPU from waiting for events.
 Provides control for external input.
 E.g.:
 An unexpected user input.
 Illegal instructions.
 Multitasking, multiprocessing.
 An abnormal situation.

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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.2 Uses of Interrupt
1. An unexpected / 2. An a completion 3. Multitasking, 4. An abnormal
external user signal multiprocessing situation
input
 Notifying the CPU  Controls the flow of  Allocating CPU time  Usage is similar to
of external events data to the output to different external input
 Free CPU from devices. programs that are events, but in this
polling.  Notify the computer sharing the CPU. case, the events
 To control the of the completion are directed at the
computer from of an action. problems within the
input device. computer system
itself.
E.g.: Keyboard Input, E.g.: printer to control E.g.: Time sharing. E.g.: Power failure,
Real-time or time the flow of Illegal instruction,
sensitive system. characters to the Hardware error.
printer in an
efficient way.
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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.3 Servicing Interrupt - Single interrupt
1. Suspend program in 2. Save context, 3. Branches to 4. CPU resumes
progress including last interrupt handler control to the
instruction program (interrupt interrupt program
executed & data routine)
values in registers,
in Process Control
Block (PCB)
When the interrupt
routine is complete,
the registers are
restored, including the
program counter and
original program
resumes exactly where
it left off.

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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.3 Servicing Interrupt - Multiple interrupts
 Multiple interrupts could be handled by assigning priorities to each

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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.4 Identifying devices that initiate interrupt
 2 methods to identify devices that initiate interrupt:
 Vectored interrupt
 The address of the interrupting device is included as part of the
interrupt.
 Polled interrupt
 Uses the general interrupt that shared by all devices. CPU polls
each device to identify the interrupt source.

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5.3 I/O Handling Techniques
5.3.2 Interrupt I/O
5.3.2.4 Identifying devices that initiate interrupt

Vectored Interrupt Polled interrupt

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5.3 I/O Handling Techniques
5.3.3 Direct Memory Access (DMA)
 DMA is a method of transferring data between peripherals & memory
without using CPU.
 Transferring large block of data.
 Direct transfer, CPU not actively involved itself.
 There are 4 pieces of data required to initiate the DMA transfer:
1. The location of data on I/O device.
2. The start location of the data block in memory.
3. The size of data to be transferred.
4. The direction of transfer (READ / WRITE).

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5.3 I/O Handling Techniques
5.3.3 Direct Memory Access (DMA)
 For DMA to take place, 3 primary conditions must met:
1. There must be a method of connect together the I/O interface &
memory.
2. The I/O modules must be capable of reading and writing to
memory.
3. There must be a mean to avoid conflict between the CPU & I/O
modules.

 E.g.: Consider a program that sorts a block of numbers.

 The entire block of umbers are transferred from HDD to memory.
 Then sorting is perform via memory.
 The sorted data is transferred back to HDD.

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5.3 I/O Handling Techniques
5.3.3 Direct Memory Access (DMA)
 Since the CPU is not actively involved during the transfer, the CPU can
be used to perform other tasks during the time when I/O transfers are
taking place.
 DMA is not limited to just disk-to-memory but also other high-speed
devices.
 DMA takes several instructions to initiate a DMA transfer, therefore is
not suitable for data transfer with small amount .

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5.3 I/O Handling Techniques
5.3.3 Direct Memory Access
(DMA)
 The working of DMA
1. Programmed I/O used to
prepare I/O module for
transfer by providing
required information &
initiating transfer
2. DMA transfer. In this case,
the data is transferred
from disk to memory
3. Upon completion, disk
controller sends
completion interrupt to
CPU

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5.4 I/O Architecture
Basic CPU-Memory-I/O Architecture

 2 key architectures
 Bus architecture
 Channel architecture

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5.4 I/O Architecture
5.4.1 Bus Architecture
 Used in almost all personal computers.
 Uses backbone for connections of various components, memory and I/O
to CPU.
 Simplest form of connection. Single system bus connects the CPU to
memory and all to all various I/O modules that control I/O devices.
 Consists of a number of interconnected buses, e.g.: CPU bus, PCI bus, ISA
bus, etc.
 These buses are interconnected by bus interface, e.g.: expansion bus
interface, bus bridges, etc. to expand the flexibility by converting bus
signals from one to another .
 The interconnect-ability makes it possible to design and use industry
standard buses on equipment of different vendors.

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5.4 I/O Architecture
5.4.1 Bus Architecture

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5.4 I/O Architecture
5.4.2 Channel Architecture
 Used in all IBM mainframe computers since late 70’s.
 Uses channel subsystem / Separate I/O processor.
 Serves as a separate CPU for I/O operations.
 Channel control words.
 Programs stored in memory, independent of CPU.
 Transfer data between memory and I/O device using DMA.
 Sub channel
 Each of it is connected to a control unit module.
 Similar role to a device controller.
 Up to 8 different channel paths between channel subsystem and
control unit (used as alternative, if busy).

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5.4 I/O Architecture
5.4.2 Channel Architecture

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Chapter 5: I/O Facilities
Self-review

5.1 Characteristic of I/O Devices 5.3.2 Interrupt I/O

5.1.1 I/O devices 5.3.2.1 Interrupts
5.1.1.1 Keyboard 5.3.2.2 Uses of Interrupt
5.1.1.2 Printer 5.3.2.3 Servicing interrupt(s)
5.1.1.3 Graphic output - Single interrupt
5.1.1.4 Disk - Multiple interrupts
5.1.2 Requirements for efficient I/O 5.3.2.4 Identifying devices that
handling initiate interrupt
5.1.3 Sample I/O configurations - Vectored interrupt
5.2 I/O Modules - Polled interrupt
5.3 I/O Handling Techniques 5.3.3 Direct Memory Access (DMA)
5.3.1 Programmed I/O (PIO) 5.4 I/O Architecture
5.4.1 Bus Architecture
5.4.2 Channel Architecture

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