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Static Properties and Methods

Static methods and properties in SystemVerilog allow for functionality that belongs to a class rather than an instance. Static properties share a single memory location across all class instances. Static methods can be accessed without creating an object and can only access static properties. Non-static methods can access static variables. Static methods are simulated in SystemVerilog using tasks or functions within a module that can be called without creating an instance.

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47 views4 pages

Static Properties and Methods

Static methods and properties in SystemVerilog allow for functionality that belongs to a class rather than an instance. Static properties share a single memory location across all class instances. Static methods can be accessed without creating an object and can only access static properties. Non-static methods can access static variables. Static methods are simulated in SystemVerilog using tasks or functions within a module that can be called without creating an instance.

Uploaded by

Purna satya srinivas Vempala
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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@shraddha_pawankar Date:15/08/23

STATIC METHODS AND PROPERTIES IN SYSTEM VERILOG

A static keyword is used in a class member to denote class has static properties or static
methods. It acts as global

Static Properties (static variables)


The static variable declared inside a class with static keyword shares a single memory
location across all class instances.
Syntax:

static <data_type> <property_name>;

Static Methods (static functions and static tasks)


Static functions and tasks can not be virtual

They can access only static properties (static members) of a class.

Accessing non-static members leads to compilation errors as it is illegal to use

But non-static functions or tasks can access static variables.

Both static methods and static members in a class can be accessed without creating an
object.

static task/function <method_name>;

Example without object creation

A. Using scope resolution operator


Syntax: <class_name>::<static method>
Ex: transaction::incr_s_id();
transaction::s_id
@shraddha_pawankar Date:15/08/23

B. Using class handle

Syntax: <instance_name>.<static method>


Ex: tr.incr_s_id();
tr.s_id;

Example:

//static properties

class transaction;

static int a;

int b;

function new();

a++;

b++;

endfunction

endclass

module tb;

transaction tx[4];

initial begin

foreach(tx[i]) begin

tx[i]=new();

$display("value of a=%0d b=%0d",tx[i].a,tx[i].b);

end

end
@shraddha_pawankar Date:15/08/23

endmodule

output :
# KERNEL: value of a=1 b=1
# KERNEL: value of a=2 b=1
# KERNEL: value of a=3 b=1
# KERNEL: value of a=4 b=1

https://www.edaplayground.com/x/mb8H

Static Methods examples

class transaction;

static int s_id;

static function void incr_s_id(); // Static function

s_id++;

endfunction

endclass

module class_example;

transaction tr;

initial begin

transaction::incr_s_id(); // Access static function without class handle

tr.incr_s_id(); // Access static function with class handle

$display("After incr_id function call");

$display("Value of s_id = %0h using tr handle", tr.s_id);

$display("Value of s_id = %0h using scope resolution operator", transaction::s_id);

end
@shraddha_pawankar Date:15/08/23

endmodule

Output:
# KERNEL: After incr_id function call
# KERNEL: Value of s_id = 2 using tr handle
# KERNEL: Value of s_id = 2 using scope resolution operator

https://edaplayground.com/x/cxf7

Q 1) How can you simulate static-like behavior in SystemVerilog?


You can simulate static-like behavior in SystemVerilog by using tasks or functions within a
module that encapsulate a specific operation.

These tasks or functions can be called without creating an instance of the module.

Q 2) Explain the purpose of static methods in traditional object-oriented programming

static methods belong to a class rather than an instance and are used for operations that
are not tied to a specific instance of the class.

They provide utility or common functionality that can be accessed without creating
objects.

Q 3) In SystemVerilog, what construct can you use to encapsulate a reusable


operation without creating an instance?

In SystemVerilog, you can use tasks or functions to encapsulate reusable operations without
creating an instance of a module.

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