COMPUTER ORGANIZATION AND DESIGN RISC-V

Edition
The Hardware/Software Interface

Chapter 4
The Processor
§4.1 Introduction
Introduction
n CPU performance factors
n Instruction count
n Determined by ISA and compiler
n CPI and Cycle time
n Determined by CPU hardware
n We will examine two RISC-V implementations
n A simplified version
n A more realistic pipelined version
n Simple subset, shows most aspects
n Memory reference: ld, sd
n Arithmetic/logical: add, sub, and, or
n Control transfer: beq

Chapter 4 — The Processor — 2

Instruction Execution
1. PC ® instruction memory, fetch instruction
2. Register numbers ® register file, read registers
3. Depending on instruction class
n Use ALU to calculate
n Arithmetic result
n Memory address for load/store
n Branch comparison
4. Access data memory for load/store
5. PC ¬ target address or PC + 4

Chapter 4 — The Processor — 3

CPU Overview
Updated PC value

PC

offset
PC

ALU result Data from memory

read

read

write

Instruction
Address Immediate Value
From instruction
Multiplexers
n Can’t just join
wires together
n Use multiplexers

Chapter 4 — The Processor — 5

Control
Selects (PC+4) or Target address

Branch control
From ALU

ALU or Memory

Reg. or Immediate

Input from instruction

output control signals to Datapath
§4.2 Logic Design Conventions
Logic Design Basics
n Information encoded in binary
n Low voltage = 0, High voltage = 1
n One wire per bit
n Multi-bit data encoded on multi-wire buses
n Combinational element
n Operate on data
n Output is a function of input
n State (sequential) elements
n Store information

Chapter 4 — The Processor — 7

Combinational Elements
n AND-gate n Adder A
Y
+
n Y=A&B n Y=A+B B

A
Y
B

n Arithmetic/Logic Unit
n Multiplexer n Y = F(A, B)
n Y = S ? I1 : I0
A
I0 M
u Y ALU Y
I1 x
B
S F

Chapter 4 — The Processor — 8

Sequential Elements
n Register: stores data in a circuit
n Uses a clock signal to determine when to
update the stored value
n Edge-triggered: update when Clk changes
from 0 to 1

Clk
D Q
D

Clk
Q

Chapter 4 — The Processor — 9

Sequential Elements
n Register with write control
n Only updates on clock edge when write
control input is 1
n Used when stored value is required later

Clk

D Q Write

Write D
Clk
Q

Chapter 4 — The Processor — 10

Clocking Methodology
n Combinational logic transforms data during
clock cycles
n Between clock edges
n Input from state elements, output to state
element
n Longest delay determines clock period

One clock cycle

§4.3 Building a Datapath
Building a Datapath
n Datapath
n Elements that process data and addresses
in the CPU
n Registers, ALUs, mux’s, memories, …
n We will build a RISC-V Datapath
incrementally
n Refining the overview design

Chapter 4 — The Processor — 12

Instruction Fetch
(PC+4)

Increment by
4 for next
64-bit instruction
register

Chapter 4 — The Processor — 13

R-Format Instructions
1. Read two register operands
2. Perform arithmetic/logical operation
3. Write register result

Register File

X5 X1 Data from X5
…
X6 Data from X6
X31
Load/Store Instructions
n Read register operands [lw x6, 32(x7)]
n Calculate address using 12-bit offset [x7+32]
n Use ALU, but sign-extend offset

n Load: Read memory and update register

n Store: Write register value to memory. [sw x6, 32(x7)]

32-bit
instruction Extracts 12 bits
Extend to 64 bits

Chapter 4 — The Processor — 15

Branch Instructions
n Read register operands [beq x6, x7, L3]
n Compare operands
n Use ALU, subtract and check Zero output
n Calculate target address
n Sign-extend displacement
n Shift left 1 place (halfword displacement)
n Add to PC value

Chapter 4 — The Processor — 16

Branch Instructions [beq x6, x7, L3]
Just
re-routes
wires

val(x6)

val(x7)

Extracts 12 bits
Extend to 64 bits
32-bit instruction Sign-bit wire
replicated

Chapter 4 — The Processor — 17

Composing the Elements
n First-cut data path does an instruction in
one clock cycle
n Each Datapath element can only do one
function at a time
n Hence, we need separate instruction and data
memories
n Use multiplexers where alternate data
sources are used for different instructions

Chapter 4 — The Processor — 18

R-Type/Load/Store Datapath
add x5, x6, x7; lw x6, 8(x7); sw x6, 16(x7);
R-Type/Load/Store Datapath
add x5, x6, x7

(x6)
0/x

0 0

(x5) (x7)

0/x

(x6) + (x7)
R-Type/Load/Store Datapath
lw x6, 8(x7)

(x7)
0

1 1

(x6) (x7)+8
8

00..0008 1

MEM[x7+8]
R-Type/Load/Store Datapath
sw x6, 16(x7)

(x7)
(x6) 1

1 x

(x7)+16
16

(x6)

00..0016 0
Full Datapath

Chapter 4 — The Processor — 23

§4.4 A Simple Implementation Scheme
ALU Control
n ALU used for
n Load/Store: F = add
n Branch: F = subtract
n R-type: F depends on opcode
ALU control Function
0000 AND
0001 OR
0010 add
0110 subtract

Chapter 4 — The Processor — 24

ALU Control
n Assume 2-bit ALUOp derived from opcode
n Combinational logic derives ALU control

ALU
opcode ALUOp Operation Opcode field ALU function control
ld 00 load register XXXXXXXXXXX add 0010
sd 00 store register XXXXXXXXXXX add 0010
beq 01 branch on equal XXXXXXXXXXX subtract 0110

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110
AND 100100 AND 0000
OR 100101 OR 0001
The Main Control Unit
n Control signals derived from instruction

Add
Sub
Add
Sub
And
Or

I[30] I[14-12]
Datapath With Control
R-Type Instruction

X
X

Chapter 4 — The Processor — 28

Load Instruction

X
X

X
X

add
X

Chapter 4 — The Processor — 29

BEQ Instruction

X X

sub
X

Chapter 4 — The Processor — 30

Performance Issues
n Longest delay determines clock period
n Critical path: load instruction
n Instruction memory ® register file ® ALU ®
data memory ® register file
n Not feasible to vary period for different
instructions
n Violates design principle
n Making the common case fast
n We will improve performance by pipelining

Chapter 4 — The Processor — 31